Export 140 results:
Author Title [ Type
] Year Filters: First Letter Of Last Name is P [Clear All Filters]
"ARTE: an Application-specific Run-Time Management Framework for Multi-cores based on Queuing Models",
Parallel Computing, 2013.
"Black-Hat High-Level Synthesis: Myth or Reality?",
IEEE Transactions on Very Large Scale Integration Systems, In Press.
"Breaking ECC2K-130",
IACR Cryptology ePrint Archive, vol. 2009, pp. 541, 11/2009.
"The Case for Polymorphic Registers in Dataflow Computing",
International Journal of Parallel Programming, vol. 54, issue 5, pp. 54-62, 10/2018.
"A Configurable Monitoring Infrastructure for NoC-Based Architectures",
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. PP, issue 99, 2013.
"Design-space Exploration and Runtime Resource Management for Multicores",
ACM Transactions on Embedded Computing Systems (TECS) - Special issue on application-specific processors, vol. 13, issue 2, pp. 20:1–20:27, 09/2013.
"Enabling Automated Bug Detection for IP-based Designs using High-Level Synthesis",
IEEE Design & Test, 2018, In Press.
"Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology",
Springer Transactions on Computational Science, vol. 5430, pp. 230–243, February, 2009.
"Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology",
Springer Transactions on Computational Science, vol. 5430, pp. 230–243, February, 2009.
"Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology",
Springer Transactions on Computational Science, vol. 5430, pp. 230–243, February, 2009.
"Linking run-time resource management of embedded multi-core platforms with automated design-time exploration",
IET Computers and Digital Techniques, vol. 5, no. -, pp. 123–135, 2011.
"OSCAR: an Optimization Methodology Exploiting Spatial Correlation in Multi-core Design Space",
IEEE Transactions on Computer-Aided Design, vol. 21, issue 5, no. -: IEEE, pp. 740-753, 05/2012.
"Secure Memory Accesses on Networks-on-Chip",
IEEE Transactions on Computers, vol. 57, no. 9, pp. 1216-1229, September, 2008.
"Securing Hardware Accelerators: a New Challenge for High-Level Synthesis",
IEEE Embedded Systems Letters, vol. 3, issue 10, pp. 77-80, 11/2017, 2018.
"Simulation-Time Security Margin Assessment against Power-Based Side Channel Attacks",
(IACR) Cryptology ePrint Archive, vol. 2014, 05/2014.
"Stealthy Dopant-Level Hardware Trojans: Extended Version",
Journal of Cryptographic Engineering, vol. 4, issue 1, pp. 19-31, 04/2014.
"System-Level Optimization of Accelerator Local Memory for Heterogeneous Systems-on-Chip",
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 36, pp. 435-448, 2017.
"TaintHLS: High-Level Synthesis For Dynamic Information Flow Tracking",
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, In Press.
Introduction to SysML,
, April 20, 2007.