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Education and Innovation in Embedded Systems Design

USI Università della Svizzera italiana, USI Faculty of Informatics, Advanced Learning and Research Institute USI Università della Svizzera italiana USI Faculty of Informatics USI Advanced Learning and Research Institute
TitleA Configurable Monitoring Infrastructure for NoC-Based Architectures
Publication TypeJournal Article
Year of Publication2013
AuthorsFiorin, L., G. Palermo, and C. Silvano
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
VolumePP
Issue99
ISSN1063-8210
Keywordshardware counters, networks-on-chip (NoCs), performance monitoring, systems-on-chip (SoCs).
Abstract

In this brief, we propose a monitoring architecture for networks-on-chip that provides system information useful for designers to efficiently exploit, at design time and run-time, the system resources available in multiprocessor system-on-chip platforms. We focus on the analysis of the architectural details and design challenges of such a system, by describing powerful tools for monitoring information that can be used both at run-time for detecting dynamic changes in system behavior and at post-execution time for debugging and profiling of applications. This brief describes the design of the monitoring probes, together with the events detectable by them, and discusses an architecture for collecting, storing, and analyzing the information gathered during an application execution.

DOI10.1109/TVLSI.2013.2290102