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Education and Innovation in Embedded Systems Design

USI Università della Svizzera italiana, USI Faculty of Informatics, Advanced Learning and Research Institute USI Università della Svizzera italiana USI Faculty of Informatics USI Advanced Learning and Research Institute
TitleDesign-space Exploration and Runtime Resource Management for Multicores
Publication TypeJournal Article
Year of Publication2013
AuthorsMariani, G., G. Palermo, V. Zaccaria, and C. Silvano
JournalACM Transactions on Embedded Computing Systems (TECS) - Special issue on application-specific processors
Volume13
Issue2
Pagination20:1–20:27
Date Published09/2013
ISSN1539-9087
Keywordsapplication-specific platforms, design-space exploration, genetic algorithms, Multicore architectures, operating systems, resource reservation, runtime resource management, throughput maximization
Abstract

Application-specific multicore architectures are usually designed by using a configurable platform in which a set of parameters can be tuned to find the best trade-off in terms of the selected figures of merit (such as energy, delay, and area). This multi-objective optimization phase is called Design-Space Exploration (DSE). Among the design-time (hardware) configurable parameters we can find the memory subsystem configuration (such as cache size and associativity) and other architectural parameters such as the instruction-level parallelism of the system processors. Among the runtime (software) configurable parameters we can find the degree of task-level parallelism associated with each application running on the platform.

The contribution of this article is twofold; first, we introduce an evolutionary (NSGA-II-based) methodology for identifying a hardware configuration which is robust with respect to applications and corresponding datasets. Second, we introduce a novel runtime heuristic that exploits design-time identified operating points to provide guaranteed throughput to each application. Experimental results show that the design-time/runtime combined approach improves the runtime performance of the system with respect to existing reference techniques, while meeting the overall power budget.

DOI10.1145/2514641.2514647