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Education and Innovation in Embedded Systems Design

USI Università della Svizzera italiana, USI Faculty of Informatics, Advanced Learning and Research Institute USI Università della Svizzera italiana USI Faculty of Informatics USI Advanced Learning and Research Institute
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Filters: Author is Luca Breveglieri  [Clear All Filters]
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Regazzoni, F., T. Eisenbarth, L. Breveglieri, P. Ienne, and I. Koren, "Can knowledge regarding the presence of countermeasures against fault attacks simplify power attacks on cryptographic devices?", Proceedings of 23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS 08), October 1-3, 2008.
Atasu, K., L. Breveglieri, and M. Macchetti, "Efficient AES implementations for ARM based platforms", SAC '04: Proceedings of the 2004 ACM symposium on Applied computing, Nicosia, Cyprus, ACM Press, New York, USA, pp. 841–845, 2004.
Cassoli, F., F. Polloni, S. Marchesin, M. Macchetti, G M. Bertoni, L. Breveglieri, and P. Fragneto, "Efficient C implementation of the ECC and AES cryptographic systems", Technology Leadership Day - organized by the MicroSwiss Network, Fribourg, October 10, 2001.
Bertoni, G M., L. Breveglieri, P. Fragneto, M. Macchetti, and S. Marchesin, "Efficient Software Implementation of AES on 32-Bit Platforms", CHES '02: Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems, London, UK, Springer-Verlag, pp. 159–171, 2003.
Barenghi, A., L. Breveglieri, I. Koren, G. Pelosi, and F. Regazzoni, "Low Cost Software Countermeasures Against Fault Attacks: Implementation and Performances Trade Offs", 5th Workshop on Embedded Systems Security (WESS), Scottsdale, Arizona, USA, October, 2010.
Regazzoni, F., T. Eisenbarth, J. Großschädl, L. Breveglieri, P. Ienne, I. Koren, and C. Paar, "Power Attacks Resistance of Cryptographic S-boxes with added Error Detection Circuits", proceedings of: '22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'07), Rome, Italy, September 26-28, 2007.
Bertoni, G M., L. Breveglieri, R. Farina, and F. Regazzoni, "Speeding Up AES By Extending a 32 bit Processor Instruction Set", ASAP '06: Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06), Washington, DC, USA, IEEE Computer Society, pp. 275-282, 2006.