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Education and Innovation in Embedded Systems Design

USI Università della Svizzera italiana, USI Faculty of Informatics, Advanced Learning and Research Institute USI Università della Svizzera italiana USI Faculty of Informatics USI Advanced Learning and Research Institute
TitleEfficient AES implementations for ARM based platforms
Publication TypeConference Paper
Year of Publication2004
AuthorsAtasu, K., L. Breveglieri, and M. Macchetti
Conference NameSAC '04: Proceedings of the 2004 ACM symposium on Applied computing
PublisherACM Press, New York, USA
Conference LocationNicosia, Cyprus
ISBN Number1-58113-812-1
Keywordsadvanced encryption standard (AES), ARM microprocessor, cache memories, code optimisation

The Advanced Encryption Standard (AES) contest, started by the U.S. National Institute of Standards and Technology (NIST), saw the Rijndael [13] algorithm as its winner [11]. Although the AES is fully defined in terms of functionality, it requires best exploitation of architectural parameters in order to reach the optimum performance on specific architectures. Our work concentrates on ARM cores [1] widely used in the embedded industry. Most promising implementation choices for the common ARM Instruction Set Architecture (ISA) are identified, and a new implementation for the linear mixing layer is proposed. The performance improvement over current implementations is demonstrated by a case study on the Intel StrongARM SA-1110 Microprocessor [2]. Further improvements based on exploitation of memory hierarchies are also described, and the corresponding performance figures are presented.