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Education and Innovation in Embedded Systems Design

USI Università della Svizzera italiana, USI Faculty of Informatics, Advanced Learning and Research Institute USI Università della Svizzera italiana USI Faculty of Informatics USI Advanced Learning and Research Institute
TitleInteraction between Fault Attack Countermeasures and the Resistance against Power Analysis Attacks
Publication TypeBook Chapter
Year of Publication2012
AuthorsRegazzoni, F., L. Breveglieri, P. Ienne, and I. Koren
EditorJoye, M., and M. Tunstall
Book TitleFault Analysis in Cryptography
Series TitleInformation Security and Cryptography Series, Springer
Pagination257-272
PublisherSpringer Berlin Heidelberg
ISBN Number978-3-642-29656-7
Abstract

Most of the countermeasures against fault attacks on cryptographic systems that have been developed so far are based on the addition of information redundancy. While these countermeasures have been evaluated with respect to their cost (implementation overhead) and efficiency (fault coverage), little attention has been devoted to the question of the impact their use has on the effectiveness of other types of side-channel attacks, in particular, power analysis attacks. This chapter presents an experimental study whose goal is to determine whether the added information redundancy can increase the vulnerability of a cryptographic circuit to power analysis attacks.

DOI10.1007/978-3-642-29656-7_15