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Education and Innovation in Embedded Systems Design

USI Università della Svizzera italiana, USI Faculty of Informatics, Advanced Learning and Research Institute USI Università della Svizzera italiana USI Faculty of Informatics USI Advanced Learning and Research Institute
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Derin, O., and A. Ferrante, "Simulation of a Self-adaptive Run-time Environment with Hardware and Software Components", SINTER '09: Proceedings of the 2009 ESEC/FSE workshop on Software integration and evolution @ runtime, Amsterdam, The Netherlands, ACM, pp. 37–40, August, 2009.
Nacul, A C., F. Regazzoni, and M. Lajolo, "HardwareScheduling Support in SMP Architecture", Design, Automation and Test in Europe(DATE), Nice, France, April 16-20, 2007.
Taddeo, A V., and A. Ferrante, "Scheduling Small packets in IPSec Multi-accelerator Based Systems", Journal of Communication(JCM) Academy publisher, vol. 2, no. 2, Stresa, Italy, pp. 53-60, March, 2007.
Sivakumar, G., and M. Prevostini, "Bridging the Gap between SysML and Design Space Exploration", FDL'06 Proceedings, Darmstadt, Germany, pp. 389-394, September 19-22, 2006.
Chandra, S., F. Regazzoni, and M. Lajolo, "Hardware/software partitioning of operating systems: a behavioral synthesis approach", GLSVLSI '06: Proceedings of the 16th ACM Great Lakes symposium on VLSI, Philadelphia, PA, USA, ACM Press, New York, USA, pp. 324–329, 2006.
Taddeo, A V., A. Ferrante, and V. Piuri, "Scheduling Small Packets in IPSec-based Systems", CCNC, Las Vegas, NV, USA, January 8, 2006.
Bertoni, G M., L. Breveglieri, R. Farina, and F. Regazzoni, "Speeding Up AES By Extending a 32 bit Processor Instruction Set", ASAP '06: Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06), Washington, DC, USA, IEEE Computer Society, pp. 275-282, 2006.
Ferrante, A., G. Piscopo, and S. Scaldaferri, "Application-Driven Optimization of VLIW Architectures: A Hardware-Software Approach", RTAS '05: Proceedings of the 11th IEEE Real Time on Embedded Technology and Applications Symposium, Washington, DC, USA, IEEE Computer Society, pp. 128–137, 03/2005.
Regazzoni, F., A C. Nacul, and M. Lajolo, "Automatic Synthesis of the Hardware/Software Interface in Multiprocessor Architectures", FDL'05 - Forum on Specification and Design Languages, Lausanne, Switzerland, September 27-30, 2005.
Basu, A S., M. Lajolo, and M. Prevostini, "Design and Synthesis of Reusable Platforms with Programmable Interconnects", UML-SoC 2005, Anaheim, California, pp. 43-48, June 12, 2005.
Regazzoni, F., and M. Lajolo, "Hardware/Software Partitioning and Interface Synthesis in Networks On Chip", IP Based SoC Design 2005, Grenoble, France, December 7-8, 2005.
Basu, A S., M. Lajolo, and M. Prevostini, "A Methodology for Bridging the Gap between UML and Codesign", UML for SOC Design, Dordrecht, The Netherlands, Springer, pp. 119-146, 2005.
Regazzoni, F., and M. Lajolo, "Interface Synthesis in Multiprocessing Systems-on-Chips", IP Based SoC Design 2004, Grenoble, December, 2004.
Basu, A S., M. Lajolo, and M. Prevostini, "UML in an Electronic System Level Design Methodology", UML-SOC'04, San Diego, California, pp. 47-52, June 6, 2004.
Lajolo, M., A S. Basu, and M. Prevostini, "UML Specifications Towards a Codesign Environment", FDL'04, Lille, France, pp. 313-324, September 14-17, 2004.