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Education and Innovation in Embedded Systems Design

USI Università della Svizzera italiana, USI Faculty of Informatics, Advanced Learning and Research Institute USI Università della Svizzera italiana USI Faculty of Informatics USI Advanced Learning and Research Institute
TitleHardwareScheduling Support in SMP Architecture
Publication TypeConference Paper
Year of Publication2007
AuthorsNacul, A C., F. Regazzoni, and M. Lajolo
Conference NameDesign, Automation and Test in Europe(DATE)
Date PublishedApril 16-20
Conference LocationNice, France
KeywordsHW/SW co-design, multiprocessor system-on-chip (MPSoC), real time operating systems
Abstract

In this paper the authors propose a hardware real time operating system (HW-RTOS) that implements the OS layer in a dual-processor SMP architecture. Intertask communication is specified by means of dedicated APIs and the HW-RTOS takes care of the communication requirements of the application and also implements the task scheduling algorithm. The HW-RTOS allows to have smaller footprints, since it avoids the need to link to the final executables traditional software RTOS libraries. Moreover, the HW-RTOS is able to exploit the easy task migration feature provided by an SMP architecture much more efficiently than a traditional software RTOS, due to its faster execution and the authors show how this significantly overcomes the performance achievable with optimal static task partitioning among two processors. Preliminary results show that the hardware overhead in a dual processor architecture is less than 20K gates.

DOI10.1109/DATE.2007.364666