@conference {100.DeFe09, title = {Simulation of a Self-adaptive Run-time Environment with Hardware and Software Components}, booktitle = {SINTER {\textquoteright}09: Proceedings of the 2009 ESEC/FSE workshop on Software integration and evolution @ runtime}, year = {2009}, month = {August}, pages = {37{\textendash}40}, publisher = {ACM}, organization = {ACM}, address = {Amsterdam, The Netherlands}, abstract = {In this paper we describe a new way for simulating self-adaptive systems developed by relying on a component-based approach, this approach proves to be useful both in easing self-adaptivity and in providing the ability to mix hardware and software elements. Our simulation method is based on SACRE (Self-Adaptive Component Run-time Environment), a framework we have defined in Java for simulating self-adaptive systems.}, keywords = {component-based design, HW/SW co-design, self-adaptive systems, simulation}, isbn = {978-1-60558-681-6}, doi = {http://doi.acm.org/10.1145/1596495.1596507}, author = {Derin, Onur and Ferrante, Alberto} } @conference {53.CoReLa07, title = {HardwareScheduling Support in SMP Architecture}, booktitle = {Design, Automation and Test in Europe(DATE)}, year = {2007}, month = {April 16-20}, address = {Nice, France}, abstract = {In this paper the authors propose a hardware real time operating system (HW-RTOS) that implements the OS layer in a dual-processor SMP architecture. Intertask communication is specified by means of dedicated APIs and the HW-RTOS takes care of the communication requirements of the application and also implements the task scheduling algorithm. The HW-RTOS allows to have smaller footprints, since it avoids the need to link to the final executables traditional software RTOS libraries. Moreover, the HW-RTOS is able to exploit the easy task migration feature provided by an SMP architecture much more efficiently than a traditional software RTOS, due to its faster execution and the authors show how this significantly overcomes the performance achievable with optimal static task partitioning among two processors. Preliminary results show that the hardware overhead in a dual processor architecture is less than 20K gates.}, keywords = {HW/SW co-design, multiprocessor system-on-chip (MPSoC), real time operating systems}, doi = {http://dx.doi.org/10.1109/DATE.2007.364666}, author = {Nacul, Andre Costi and Regazzoni, Francesco and Lajolo, Marcello} } @article {51.TaFe07, title = {Scheduling Small packets in IPSec Multi-accelerator Based Systems}, journal = {Journal of Communication(JCM) Academy publisher}, volume = {2}, number = {2}, year = {2007}, month = {March}, pages = {53-60}, address = {Stresa, Italy}, abstract = {IPSec is a suite of protocols that adds security to communications at the IP level. Protocols within the IPSec suite make extensive use of cryptographic algorithms. Since these algorithms are computationally very intensive, some hardware acceleration is needed to support high throughput. IPSec accelerator performance may heavily depend on the dimension of the packets to be processed. In fact, when packets are small, the time needed to transfer data and to set up the accelerators may exceed the one to process (e.g. to encrypt) the packets by software. In this paper we present a packet scheduling algorithm that tackles this problem. Packets belonging to the same Security Association are grouped before the transfer to the accelerators. Thus, the transfer and the initialization time have a lower influence on the total processing time of the packets. This algorithm also provides the capability of scheduling grouped packets over multiple cryptographic accelerators. High-level simulations of the scheduling algorithm have been performed and the results for a one-accelerator and for a two-accelerator system are also shown in this paper.}, keywords = {accelerator, HW/SW co-design, IPSec, scheduling algorithm, security}, author = {Taddeo, Antonio Vincenzo and Ferrante, Alberto} } @conference {44.SivaPrev2006, title = {Bridging the Gap between SysML and Design Space Exploration}, booktitle = {FDL{\textquoteright}06 Proceedings}, year = {2006}, month = {September 19-22}, pages = {389-394}, address = {Darmstadt, Germany}, abstract = {In the last few years the embedded systems design discipline required new design methodologies and new specification languages to support system engineers in developing heterogeneous systems where hardware and software are combined. One of the emerging modeling languages for system designers is the UML-based language called Systems Modeling Language (SysML). One of the most important tasks to be addressed early in the system design phase is the Design Space Exploration (DSE). DSE helps designers in discovering the optimal solutions among all possible combinations after mapping functional to architectural specifications. This paper describes an approach on how to use SysML for a DSE analysis within a system design phase.}, keywords = {design space exploration, HW/SW co-design, modeling languages, systems modeling language (SysML)}, author = {Sivakumar, Ganesan and Prevostini, Mauro} } @conference {40.1127983, title = {Hardware/software partitioning of operating systems: a behavioral synthesis approach}, booktitle = {GLSVLSI {\textquoteright}06: Proceedings of the 16th ACM Great Lakes symposium on VLSI}, year = {2006}, pages = {324{\textendash}329}, publisher = {ACM Press, New York, USA}, organization = {ACM Press, New York, USA}, address = {Philadelphia, PA, USA}, abstract = {In this paper we propose a hardware real time operating system(HW-RTOS) solution that makes use of a dedicated hardware in order to replace the standard support provided by the POSIX layer of a general purpose RTOS for implementing task synchronization and scheduling. By redefining only the I/O APIs of the tasks, the HW-RTOS then takes care of the communication requirements of the original application and also implements the task scheduling algorithm. The new software application can then be compiled without any need for POSIX support. The main advantages are smaller and faster executables. We present results that show how a small hardware area, less than 10K gates, can result in a 15X performance improvement when the original software scheduler is replaced by a dedicated HW-RTOS.}, keywords = {HW/SW co-design, real time operating systems, system-on-chip (SoC)}, isbn = {1-59593-347-6}, doi = {http://doi.acm.org/10.1145/1127908.1127983}, author = {Chandra, Satish and Regazzoni, Francesco and Lajolo, Marcello} } @conference {41.TaFePi2006, title = {Scheduling Small Packets in IPSec-based Systems}, booktitle = {CCNC}, year = {2006}, month = {January 8}, address = {Las Vegas, NV, USA}, abstract = {IPSec is a suite of protocols that adds security to communications at the IP level. Protocols within the IPSec suite make extensive use of cryptographic algorithms. Since these algorithms are computationally very intensive, some hardware acceleration is needed to support high throughput. IPSec accelerator performance may heavily depend on the dimension of the packets to be processed. When packets are small, the time needed to transfer data and to set up the accelerator may exceed the one to process the packets (e.g. to encrypt) by software. In this paper, we propose a solution for this problem. High-level simulations and the related results are provided to show the properties of the algorithm.}, keywords = {accelerator, HW/SW co-design, IPSec, scheduling algorithm, security}, doi = {http://dx.doi.org/10.1109/CCNC.2006.1593123}, author = {Taddeo, Antonio Vincenzo and Ferrante, Alberto and Piuri, Vincenzo} } @conference {39.1169233, title = {Speeding Up AES By Extending a 32 bit Processor Instruction Set}, booktitle = {ASAP {\textquoteright}06: Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP{\textquoteright}06)}, year = {2006}, pages = {275-282}, publisher = {IEEE Computer Society}, organization = {IEEE Computer Society}, address = {Washington, DC, USA}, abstract = {Nowadays the need of speed in cipher and decipher operations is more important than in the past. This is due to the diffusion of real time applications, which fact involves the use of cryptography. Many co-processors for cryptography were studied and presented in the past, but only few works were addressed to the enhancement of the instruction set architecture (ISA) of the embedded processor. This paper presents an extension of the ISA of a 32 bit processor, that aims at speeding up the software implementations of the AES algorithm. After the identification of the most frequently executed and the most time consuming sections of the algorithm, a set of dedicated instructions is designed in order to improve the performances of the cipher operations. We validate our instruction set extension by measuring the speed up for different optimized implementations of AES using an ARM processor simulator, but the enhancements we propose are general enough to be applied to almost all 32 bit processors.}, keywords = {cryptography, HW/SW co-design, instruction set extension}, isbn = {0-7695-2682-9}, doi = {http://dx.doi.org/10.1109/ASAP.2006.62}, author = {Bertoni, Guido Marco and Breveglieri, Luca and Farina, Roberto and Regazzoni, Francesco} } @conference {28.1049903, title = {Application-Driven Optimization of VLIW Architectures: A Hardware-Software Approach}, booktitle = {RTAS {\textquoteright}05: Proceedings of the 11th IEEE Real Time on Embedded Technology and Applications Symposium}, year = {2005}, month = {03/2005}, pages = {128{\textendash}137}, publisher = {IEEE Computer Society}, organization = {IEEE Computer Society}, address = {Washington, DC, USA}, abstract = {A large number of embedded multimedia applications are characterized by high instruction-level parallelism (ILP) expecially in the most critical internal loop bodies. Very Large Instruction Word (VLIW) architectures Application Specific Instruction Set Processors (ASIP) are best suited to exploit such parallelism. Fast design space exploration and optimization of VLIW architecture to a specific application target is increasingly becoming the crucial factor to achieve higher efficiency designs in a relatively small amount of time. In this paper we propose an example of VLIW architecture application driven optimization using the VEX (VLIW Example) system. A typical image processing application, the Imaging Pipeline, has been chosen as an example.}, keywords = {design space exploration, embedded systems, HW/SW co-design, HW/SW partitioning, system level design, very long instruction words (VLIW)}, isbn = {0-7695-2302-1}, doi = {http://dx.doi.org/10.1109/RTAS.2005.9}, author = {Ferrante, Alberto and Piscopo, Giuseppe and Scaldaferri, Stefano} } @conference {36.RegNacLaj2005, title = {Automatic Synthesis of the Hardware/Software Interface in Multiprocessor Architectures}, booktitle = {FDL{\textquoteright}05 - Forum on Specification and Design Languages}, year = {2005}, month = {September 27-30}, address = {Lausanne, Switzerland}, abstract = {Although Moore{\textquoteright}s Law, in principle, enables a huge number of components to be integrated into a single chip, design methods that will allow system architects to put the components together to achieve cost, power and time-to-market targets are severely lacking. System-level design and optimization techniques can significantly reduce the design gap by providing solutions that achieve correct-by-construction rather than the correct-by-iteration approach. This paper presents a programmatic interface generation tool for automating the generation of the hardware/software interfaces in the context of multiprocessor Systems-On-Chips. The solutions that we present are of crucial importance in a platform based design environment for building a flexible system with reusable IPs and CPU cores.}, keywords = {HW/SW co-design, system-on-chip (SoC)}, author = {Regazzoni, Francesco and Nacul, Andre Costi and Lajolo, Marcello} } @conference {34.BaLaPrevos2005, title = {Design and Synthesis of Reusable Platforms with Programmable Interconnects}, booktitle = {UML-SoC 2005}, year = {2005}, month = {June 12}, pages = {43-48}, address = {Anaheim, California}, abstract = {Platform based design requires to restrict the number of possible design choices in order to make it possible to come up with programmable solutions able to cope with the current complexity of System-On-Chip (SoC) designs. Nowadays there is a general consensus toward the fact that an effective Electronic System Level (ESL) design methodology must provide a specific support for platform specification, hardware/software partitioning and programmatic interfaces synthesis in order to allow designers to exploit the potentials of state-of-the-art technologies. In this work we present a methodology that leverages on UML for building new architectural platforms to be used to be used in the system design process. We show how our methodology can allow to reuse pre-designed platforms by adding new architectural components and by customizing their interconnections}, keywords = {HW/SW co-design, system-on-chip (SoC), unified modeling language (UML)}, author = {Basu, Ananda Shankar and Lajolo, Marcello and Prevostini, Mauro} } @conference {37.RegLaj2005, title = {Hardware/Software Partitioning and Interface Synthesis in Networks On Chip}, booktitle = {IP Based SoC Design 2005}, year = {2005}, month = {December 7-8}, address = {Grenoble, France}, abstract = {With deep sub-micron technology, chip designers are expected to create System-On-Chip (SOC) solutions by connecting different Intellectual Property (IP) blocks using efficient and reliable interconnection schemes. On chip networks are quite compelling because, by applying networking techniques to on-chip communication, they allow to implement a fully distributed communication pattern with little or no global coordination. This avoids the problems due to the difficulty of implementing future chips with one single clock source and negligible skew. On the other hand, in order to benefit from the NOC communication paradigm, designers should perform a careful functional mapping for taking advantage of spatial locality, by placing the blocks that communicate more frequently closer together. This reduces the use of long global paths and the corresponding energy dissipation. In this work we show how a tile based NOC architecture can be exploited in order to support a flexible hardware/software partitioning of a system-level specification and we present a methodology for the automatic synthesis of the hardware/software interfaces.}, keywords = {HW/SW co-design, network-on-chip (NoC), system-on-chip (SoC)}, author = {Regazzoni, Francesco and Lajolo, Marcello} } @inbook {30.BaLaPre2005, title = {A Methodology for Bridging the Gap between UML and Codesign}, booktitle = {UML for SOC Design}, year = {2005}, pages = {119-146}, publisher = {Springer}, organization = {Springer}, address = {Dordrecht, The Netherlands}, abstract = {The Unified Modeling Language (UML) is getting more popular among system designers due to the need to raise the level of abstraction in system specifications. We present here a methodology that integrates UML specifications with a hardware/software codesign platform. This work aims to give a contribution toward SoC Design Automation starting from system level specification down to hardware/software partitioning and integration.}, keywords = {HW/SW co-design, methodology, system specifications, unified modeling language (UML)}, author = {Basu, Ananda Shankar and Lajolo, Marcello and Prevostini, Mauro}, editor = {Martin, Grant and Muller, Wolfgang} } @conference {27.RegLaj2004, title = {Interface Synthesis in Multiprocessing Systems-on-Chips}, booktitle = {IP Based SoC Design 2004}, year = {2004}, month = {December}, address = {Grenoble}, abstract = {Although Moore{\textquoteright}s Law, in principle, enables a huge number of components to be integrated into a single chip, design methods that will allow system architects to put the components together to achieve cost, power and time-to-market targets are severely lacking. System-level design and optimization techniques can significantly reduce the design gap by providing solutions that achieve correct-by-construction approach rather than the correct-by-iteration approach. This paper presents a programmatic interface generation tool for automating the generation of the hardware/software interfaces in the context of multi-processor Systems-On-Chips. The solutions that we present are of crucial importance in a platform based design environment for building a flexible system with reusable IPs and CPU cores.}, keywords = {HW/SW co-design, system-on-chip (SoC)}, author = {Regazzoni, Francesco and Lajolo, Marcello} } @conference {23.BaLaPre2004, title = {UML in an Electronic System Level Design Methodology}, booktitle = {UML-SOC{\textquoteright}04}, year = {2004}, month = {June 6}, pages = {47-52}, address = {San Diego, California}, abstract = {The interest in System-On-Chip (SoC) design using the Unifed Modeling Language (UML) has been growing significantly during the last couple of years. In this paper we would like to present a methodology that aims to address embedded systems design issues at multiple levels of abstraction and to support a function/architecture codesign process. Our approach integrates UML with high-level synthesis and hardware/software co-verification techniques in order to provide an automated flow for SoC design starting from system-level specifications down to hardware/software partitioning and integration. UML has been selected because it is platform independent and helps team members to share very efficiently relevant information during the various design phases, while high-level synthesis helps to evaluate constraints that the embedded system must satisfy: e.g. performance, power and cost starting from behavioral specifications. The paper aims to give a contribution towards SoC Design automation from System-level specification to hardware/software partitioning.}, keywords = {HW/SW co-design, methodology, system-on-chip (SoC), unified modeling language (UML)}, author = {Basu, Ananda Shankar and Lajolo, Marcello and Prevostini, Mauro} } @conference {24.LaBaPre2004, title = {UML Specifications Towards a Codesign Environment}, booktitle = {FDL{\textquoteright}04}, year = {2004}, month = {September 14-17}, pages = {313-324}, address = {Lille, France}, abstract = {The Unified Modeling Language (UML) is receiving more and more attention from system designers that need to model both hardware and software related aspects of a system. On the ground of the growing consensus toward the need to raise the level of abstraction in system specifications, we would like to present a methodology that aims to address embedded systems design issues at multiple levels of abstraction and to support a function/architecture codesign process. Our approach integrates UML with high-level synthesis and hardware/software co-verification techniques in order to provide an automated flow for SoC design starting from system-level specifications down to hardware/software partitioning and integration. UML has been selected because it is platform independent and helps team member to share very efficiently relevant information during the various design phases, while high-level synthesis helps to evaluate constraints that the embedded system must satisfy: e.g. performance, power and cost starting from behavioral specifications.}, keywords = {embedded systems, HW/SW co-design, system-on-chip (SoC), unified modeling language (UML)}, author = {Lajolo, Marcello and Basu, Ananda Shankar and Prevostini, Mauro} }