|Title||Scheduling Small Packets in IPSec-based Systems|
|Publication Type||Conference Paper|
|Year of Publication||2006|
|Authors||Taddeo, A V., A. Ferrante, and V. Piuri|
|Date Published||January 8|
|Conference Location||Las Vegas, NV, USA|
|Keywords||accelerator, HW/SW co-design, IPSec, scheduling algorithm, security|
IPSec is a suite of protocols that adds security to communications at the IP level. Protocols within the IPSec suite make extensive use of cryptographic algorithms. Since these algorithms are computationally very intensive, some hardware acceleration is needed to support high throughput. IPSec accelerator performance may heavily depend on the dimension of the packets to be processed. When packets are small, the time needed to transfer data and to set up the accelerator may exceed the one to process the packets (e.g. to encrypt) by software. In this paper, we propose a solution for this problem. High-level simulations and the related results are provided to show the properties of the algorithm.