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Education and Innovation in Embedded Systems Design

USI Università della Svizzera italiana, USI Faculty of Informatics, Advanced Learning and Research Institute USI Università della Svizzera italiana USI Faculty of Informatics USI Advanced Learning and Research Institute
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Barenghi, A., C. Hocquet, D. Bol, F-X. Standaert, F. Regazzoni, and I. Koren, "A Combined Design-Time/Test-Time Study of the Vulnerability of Sub-Threshold Devices to Low Voltage Fault Attacks", IEEE Transactions on Emerging Topics in Computing, vol. PP, issue 99, 04/2014.
Barenghi, A., C. Hocquet, D. Bol, F-X. Standaert, F. Regazzoni, and I. Koren, "Exploring the Feasibility of Low Cost Fault Injection Attacks on Sub-Threshold Devices through an Example of a 65nm AES Implementation", 7th Workshop on RFID Security and Privacy (RFIDSec), Amherst, Massachussets, USA, June, 2011.
Barenghi, A., G. Pelosi, and F. Regazzoni, "Simulation-Time Security Margin Assessment against power-based Side Channel Attacks", 7th Workshop on Embedded Systems Security (WESS), Tampere, Finland, October, 2012.
Basu, A S., M. Lajolo, and M. Prevostini, "Design and Synthesis of Reusable Platforms with Programmable Interconnects", UML-SoC 2005, Anaheim, California, pp. 43-48, June 12, 2005.
Basu, A S., M. Lajolo, and M. Prevostini, "UML in an Electronic System Level Design Methodology", UML-SOC'04, San Diego, California, pp. 47-52, June 6, 2004.
Basu, A S., M. Lajolo, and M. Prevostini, "A Methodology for Bridging the Gap between UML and Codesign", UML for SOC Design, Dordrecht, The Netherlands, Springer, pp. 119-146, 2005.
Bayrak, A. Galip, F. Regazzoni, D. Novo, P. Brisk, F-X. Standaert, and P. Ienne, "Automatic Application of Power Analysis Countermeasures", IEEE Transactions on Computers , vol. 64, issue 2, pp. 329-341, 02/2015.
Bayrak, A. Galip, N. Velickovic, F. Regazzoni, D. Novo Bruna, P. Brisk, and P. Ienne, "An eda-friendly protection scheme against side-channel attacks", Design, Automation and Test in Europe (DATE), Grenoble, France, March, 2013.
Bayrak, A. Galip, F. Regazzoni, D. Novo Bruna, P. Brisk, F-X. Standaert, and P. Ienne, "Automatic Application of Power Analysis Countermeasures", IEEE Transactions on Computers, vol. PP, issue 99, 12/2013.
Bayrak, A. Galip, F. Regazzoni, P. Brisk, F-X. Standaert, and P. Ienne, "A First Step Towards Automatic Application of Power Analysis Countermeasures", 48th Design Automation Conference (DAC), San Diego, Califorina, June, 2011.
Bayrak, A. Galip, F. Regazzoni, D. Novo Bruna, and P. Ienne, "Sleuth: Automated Verification of Software Power Analysis Countermeasures", Workshop on Cryptographic Hardware and Embedded Systems (CHES), Santa Barbara, California, USA, August, 2013.
Becker, G., F. Regazzoni, C. Paar, and W. Burleson, "Stealthy Dopant-Level Hardware Trojans", Workshop on Cryptographic Hardware and Embedded Systems (CHES), Santa Barbara, California, USA, August, 2013.
Becker, G., F. Regazzoni, C. Paar, and W. Burleson, "Stealthy Dopant-Level Hardware Trojans: Extended Version", Journal of Cryptographic Engineering, vol. 4, issue 1, pp. 19-31, 04/2014.
Bellon, S., C. Favi, M. Malek, M. Macchetti, and F. Regazzoni, "Evaluating the Impact of Environmental Factors on Physically Unclonable Functions", International Symposium on Field-Programmable Gate Arrays FPGA 2016, Monterey, CA, USA, ACM New York, NY, USA, pp. 279, 02/2016.
Bertoni, G M., L. Breveglieri, R. Farina, and F. Regazzoni, "A 640 Mbit/s 32-bit Pipelined Implementation of the AES Algorithm", SECRYPT, Porto, Portugal, July 26, 2008.
Bertoni, G M., L. Breveglieri, P. Fragneto, M. Macchetti, and S. Marchesin, "Efficient Software Implementation of AES on 32-Bit Platforms", CHES '02: Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems, London, UK, Springer-Verlag, pp. 159–171, 2003.
Bertoni, G M., L. Breveglieri, R. Farina, and F. Regazzoni, "Speeding Up AES By Extending a 32 bit Processor Instruction Set", ASAP '06: Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06), Washington, DC, USA, IEEE Computer Society, pp. 275-282, 2006.
Bhasin, S., P. Maistri, and F. Regazzoni, "Malicious Wave: a Survey on Actively Tampering Using Electromagnetic Glitch", International Symposium on Electromagnetic Compatibility 2014, 08/2014.
Bhasin, S., and F. Regazzoni, "A survey on hardware trojan detection techniques", IEEE International Symposium on Circuits and Systems (ISCAS) 2015, 2015, Lisbon, Portugal, IEEE, pp. 2021-2024, 08/2015.
Bianchi, F. Maria, L. Livi, C. Alippi, and R. Jenssen, "Multiplex visibility graphs to investigate recurrent neural network dynamics", Nature-Scientific reports, vol. 7, pp. 44037-44049, 03/2017.

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