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"Exploring the Feasibility of Low Cost Fault Injection Attacks on Sub-Threshold Devices through an Example of a 65nm AES Implementation", 7th Workshop on RFID Security and Privacy (RFIDSec), Amherst, Massachussets, USA, June, 2011.
"Simulation-Time Security Margin Assessment against power-based Side Channel Attacks", 7th Workshop on Embedded Systems Security (WESS), Tampere, Finland, October, 2012.
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"Stealthy Dopant-Level Hardware Trojans", Workshop on Cryptographic Hardware and Embedded Systems (CHES), Santa Barbara, California, USA, August, 2013.
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"Evaluating the Impact of Environmental Factors on Physically Unclonable Functions", International Symposium on Field-Programmable Gate Arrays FPGA 2016, Monterey, CA, USA, ACM New York, NY, USA, pp. 279, 02/2016.
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"Speeding Up AES By Extending a 32 bit Processor Instruction Set", ASAP '06: Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06), Washington, DC, USA, IEEE Computer Society, pp. 275-282, 2006.
"A 640 Mbit/s 32-bit Pipelined Implementation of the AES Algorithm", SECRYPT, Porto, Portugal, July 26, 2008.
"Malicious Wave: a Survey on Actively Tampering Using Electromagnetic Glitch", International Symposium on Electromagnetic Compatibility 2014, 08/2014.
"A survey on hardware trojan detection techniques", IEEE International Symposium on Circuits and Systems (ISCAS) 2015, 2015, Lisbon, Portugal, IEEE, pp. 2021-2024, 08/2015.
"Time series kernel similarities for predicting Paroxysmal Atrial Fibrillation from ECGs", IJCNN 2018 : International Joint Conference on Neural Networks, Rio, Brazil, IEEE, 07/2018.