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Education and Innovation in Embedded Systems Design

USI Università della Svizzera italiana, USI Faculty of Informatics, Advanced Learning and Research Institute USI Università della Svizzera italiana USI Faculty of Informatics USI Advanced Learning and Research Institute
TitleSimulation-Time Security Margin Assessment against power-based Side Channel Attacks
Publication TypeConference Paper
Year of Publication2012
AuthorsBarenghi, A., G. Pelosi, and F. Regazzoni
Conference Name7th Workshop on Embedded Systems Security (WESS)
Date PublishedOctober
Conference LocationTampere, Finland