Export 105 results:Author Title Type [ Year]
Filters: Author is Francesco Regazzoni [Clear All Filters]
Reconfigurable Logic Circuit, , no. GB1719355.8, 11/2017, Submitted.
"Black-Hat High-Level Synthesis: Myth or Reality?", IEEE Transactions on Very Large Scale Integration Systems, In Press.
"Compact Circuits for Combined AES", Journal of Cryptographic Engineering, In Press.
"Customized Instructions for Protection Against Memory Integrity Attacks", IEEE Embedded Systems Letters, In Press.
"On Practical Discrete Gaussian Samplers For Lattice-Based Cryptography", IEEE Transaction on Computers, In Press.
"TaintHLS: High-Level Synthesis For Dynamic Information Flow Tracking", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, In Press.
"Towards Low Energy Stream Ciphers", IACR Transactions on Symmetric Cryptology, In Press.
"High-Level Synthesis of Benevolent Trojans", Proceedings of the IEEE Design, Automation and Test in Europe Conference (DATE), 2019.
"Power and Performance Optimized Hardware Classifiers for Eefficient On-device Malware Detection", Cryptography and Security in Computing Systems, Valencia, Spain, ACM, 01/2019.
"Compact, Scalable, and Efficient Gaussian Samplers for Lattice-Based Cryptography", Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) 2018, 2018.
"Efficient Configurations for Block Ciphers with Unified ENC/DEC Paths", Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust (HOST) 2017, 2018.
"Exploring the Vulnerability of R-LWE Encryption to Fault Attacks", Workshop on Cryptography and Security in Computing Systems of the HiPEAC2018 Conference, CS2 '18, New York, NY, USA, ACM, 2018.
"Inverse Gating for Low Energy Block Ciphers", Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2018.
"Quantum Era Challenges for Classical Computers", Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, New York, NY, USA, ACM, 2018.
"Rethinking Secure FPGAs: TowardsCryptography-friendly Configurable Cell Architecture and its Automated Design Flow", Proceedings of FCCM, 05/2018.
"SCA-Resistance for AES: How Cheap Can We Go?", Progress in Cryptology – AFRICACRYPT 2018, Cham, Springer International Publishing, 2018.
"Securing Hardware Accelerators: a New Challenge for High-Level Synthesis", IEEE Embedded Systems Letters, vol. 3, issue 10, pp. 77-80, 11/2017, 2018.
"Security: The Dark Side of Approximate Computing?", Proceedings of the International Conference on Computer-Aided Design, New York, NY, USA, ACM, 11/2018.
"TAO: Techniques for Algorithmic Obscuration during High-Level Synthesis", Proceedings of the ACM/IEEE Design Automation Conference (DAC), 2018.
"Cross-layer Design of Reconfigurable Cyber-Physical Systems", Proceedings of Design, Automation and Test in Europe (DATE) 2017, 2017.