Export 131 results:
Author [ Title
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"MULTICUBE: Multi-Objective Design Space Exploration of Multiprocessor Architectures for Embedded Multimedia Applications",
Proceedings of the DATE'09 workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications, Nice, France, April, 2009.
"MULTICUBE: Multi-Objective Design Space Exploration of Multi-Core Architectures",
VLSI 2010 Annual Symposium, vol. 105, Netherlands, Springer, pp. 47-63, 2011.
"MULTICUBE: Multi-Objective Design Space Exploration of Multi-Core Architectures",
VLSI 2010 Annual Symposium, vol. 105, Netherlands, Springer, pp. 47-63, 2011.
"Multicube: Multi-objective design space exploration of multi-core architectures",
ISVLSI 2010: IEEE Annual Symposium on VLSI, Lixouri, Kefalonia - Greece, pp. 488–493, July, 2010.
"Multicube: Multi-objective design space exploration of multi-core architectures",
ISVLSI 2010: IEEE Annual Symposium on VLSI, Lixouri, Kefalonia - Greece, pp. 488–493, July, 2010.
"Multicube Explorer: An Open Source Framework for Design Space Exploration of Chip Multi-Processors",
2PARMA: Proceedings of the Workshop on Parallel Programming and Run-time Management Techniques for Many-core Architectures, Hannover, Germany, February, 2010.
"Multicube Explorer - A Design Space Exploration Framework for Embedded Systems-on-Chip",
Proceedings of the DATE'09 workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications, Nice, France, April, 2009.
"The MULTICUBE Design Flow",
Multi-objective Design Space Exploration of Multiprocessor SoC Architectures: Springer New York, pp. 3-17, 2011.
"The MULTICUBE Design Flow",
Multi-objective Design Space Exploration of Multiprocessor SoC Architectures: Springer New York, pp. 3-17, 2011.
"MPSoCs Run-Time Monitoring through Networks-on-Chip",
The 2009 Conference on Design, Automation and Test In Europe (DATE'09), Nice, France, April/2009.
"A Monitoring System for NoCs",
Proceedings of the Third International Workshop on Network on Chip Architectures (NoCArc'2010), Atlanta, Georgia, USA, December, 2010.
"Modelling the Power Cost of Security in Wireless Sensor Networks : the Case of 802.15.4",
Proceedings of IEEE ICT08, Saint Petersburg, Russia, June, 2008.
"Midori: (A) Block Cipher for Low Energy (Extended Version)",
(IACR) Cryptology ePrint Archive, vol. 2015, 12/2015.
"Midori: A Block Cipher for Low Energy",
21st International Conference on the Theory and Application of Cryptology and Information Security ASIACRYPT 2015, vol. 9453, Auckland, New Zealand, Springer Berlin Heidelberg, pp. 411-436, 11/2015.
"Middleware Approaches for Adaptivity of Kahn Process Networks on Networks-on-Chip",
DASIP'11: Proceedings of the Conference on Design and Architectures for Signal and Image Processing, Tampere, Finland, pp. 1–8, November 2-4, 2011.
"A Methodology for efficient architectural exploration of energy-delay trade-offs for embedded systems",
SAC 2003, Melbourne, pp. 672-678, March, 2003.
"A Methodology for efficient architectural exploration of energy-delay trade-offs for embedded systems",
SAC 2003, Melbourne, pp. 672-678, March, 2003.
"A Methodology for efficient architectural exploration of energy-delay trade-offs for embedded systems",
SAC 2003, Melbourne, pp. 672-678, March, 2003.
"A Methodology for efficient architectural exploration of energy-delay trade-offs for embedded systems",
SAC 2003, Melbourne, pp. 672-678, March, 2003.
"Meta-model Assisted Optimization for Design Space Exploration of Multi-Processor Systems-on-Chip",
Euromicro Proceedings of DSD'09 - Conference on Digital System Design, Patras, Greece, August, 2009.