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Education and Innovation in Embedded Systems Design

USI Università della Svizzera italiana, USI Faculty of Informatics, Advanced Learning and Research Institute USI Università della Svizzera italiana USI Faculty of Informatics USI Advanced Learning and Research Institute
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Filters: Author is Alessandro Barenghi  [Clear All Filters]
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C
Barenghi, A., C. Hocquet, D. Bol, F-X. Standaert, F. Regazzoni, and I. Koren, "A Combined Design-Time/Test-Time Study of the Vulnerability of Sub-Threshold Devices to Low Voltage Fault Attacks", IEEE Transactions on Emerging Topics in Computing, vol. PP, issue 99, 04/2014.
E
Barenghi, A., C. Hocquet, D. Bol, F-X. Standaert, F. Regazzoni, and I. Koren, "Exploring the Feasibility of Low Cost Fault Injection Attacks on Sub-Threshold Devices through an Example of a 65nm AES Implementation", 7th Workshop on RFID Security and Privacy (RFIDSec), Amherst, Massachussets, USA, June, 2011.
L
Barenghi, A., L. Breveglieri, I. Koren, G. Pelosi, and F. Regazzoni, "Low Cost Software Countermeasures Against Fault Attacks: Implementation and Performances Trade Offs", 5th Workshop on Embedded Systems Security (WESS), Scottsdale, Arizona, USA, October, 2010.
S
Barenghi, A., G. Pelosi, and F. Regazzoni, "Simulation-Time Security Margin Assessment against power-based Side Channel Attacks", 7th Workshop on Embedded Systems Security (WESS), Tampere, Finland, October, 2012.
Barenghi, A., G. Pelosi, and F. Regazzoni, "Simulation-Time Security Margin Assessment against Power-Based Side Channel Attacks", (IACR) Cryptology ePrint Archive, vol. 2014, 05/2014.