Export 105 results:Author Title [ Type] Year
Filters: Author is Francesco Regazzoni [Clear All Filters]
Reconfigurable Logic Circuit, , no. GB1719355.8, 11/2017, Submitted.
Hardware scheduled SMP architectures, , no. US 11/947,278, 06/2008.
"Towards Low Energy Stream Ciphers", IACR Transactions on Symmetric Cryptology, In Press.
"TaintHLS: High-Level Synthesis For Dynamic Information Flow Tracking", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, In Press.
"Stealthy Dopant-Level Hardware Trojans: Extended Version", Journal of Cryptographic Engineering, vol. 4, issue 1, pp. 19-31, 04/2014.
"Simulation-Time Security Margin Assessment against Power-Based Side Channel Attacks", (IACR) Cryptology ePrint Archive, vol. 2014, 05/2014.
"Securing Hardware Accelerators: a New Challenge for High-Level Synthesis", IEEE Embedded Systems Letters, vol. 3, issue 10, pp. 77-80, 11/2017, 2018.
"On Practical Discrete Gaussian Samplers For Lattice-Based Cryptography", IEEE Transaction on Computers, In Press.
"Midori: (A) Block Cipher for Low Energy (Extended Version)", (IACR) Cryptology ePrint Archive, vol. 2015, 12/2015.
"An Investigation of Sources of Randomness Within Discrete Gaussian Sampling", IACR Cryptology ePrint Archive, vol. 2017, pp. 298, 2017.
"Harvesting the potential of nano-CMOS for lightweight cryptography: An ultra-low-voltage 65 nm AES coprocessor for passive RFID tags", Springer Journal of Cryptographic Engineering, vol. 1, issue 1, 2011.
"A Fast ULV Logic Synthesis Flow in Many-Vt CMOS Processes for Minimum Energy under Timing Constraints", IEEE Transactions on Circuits and Systems II, vol. 59, issue 12, pp. 947-951, 2013.
"A Fast ULV Logic Synthesis Flow in Many-Vt CMOS Processes for Minimum Energy Under Timing Constraints", IEEE Transactions on Circuits and Systems II: Express Briefs , vol. 59-II, issue 12, pp. 947-951, 02/2012.
"Exploring Energy Efficiency of Lightweight Block Ciphers", (IACR) Cryptology ePrint Archive, vol. 2015, 09/2015.
"Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology", Springer Transactions on Computational Science, vol. 5430, pp. 230–243, February, 2009.
"Customized Instructions for Protection Against Memory Integrity Attacks", IEEE Embedded Systems Letters, In Press.
"Compact Circuits for Combined AES", Journal of Cryptographic Engineering, In Press.
"A Combined Design-Time/Test-Time Study of the Vulnerability of Sub-Threshold Devices to Low Voltage Fault Attacks", IEEE Transactions on Emerging Topics in Computing, vol. PP, issue 99, 04/2014.
"Breaking ECC2K-130", IACR Cryptology ePrint Archive, vol. 2009, pp. 541, 11/2009.
"Black-Hat High-Level Synthesis: Myth or Reality?", IEEE Transactions on Very Large Scale Integration Systems, In Press.