"Simulation-Time Security Margin Assessment against Power-Based Side Channel Attacks",
(IACR) Cryptology ePrint Archive, vol. 2014, 05/2014.
"Simulation-Time Security Margin Assessment against power-based Side Channel Attacks",
7th Workshop on Embedded Systems Security (WESS), Tampere, Finland, October, 2012.
"Low Cost Software Countermeasures Against Fault Attacks: Implementation and Performances Trade Offs",
5th Workshop on Embedded Systems Security (WESS), Scottsdale, Arizona, USA, October, 2010.