Export 140 results:
Author Title Type [ Year
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"Topology Optimization of Wireless Localization Networks",
European Wireless 2016 , Oulu, Finland, 05/2016.
"Trojans in Early Design Steps - An Emerging Threat",
TRUDEVICE Final Conference (FCTRUâ16), 2016.
"Cross-layer Design of Reconfigurable Cyber-Physical Systems",
Proceedings of Design, Automation and Test in Europe (DATE) 2017, 2017.
"Cross-layer Design of Reconfigurable Cyber-Physical Systems",
Proceedings of Design, Automation and Test in Europe (DATE) 2017, 2017.
"Cross-layer Design of Reconfigurable Cyber-Physical Systems",
Proceedings of Design, Automation and Test in Europe (DATE) 2017, 2017.
"Detecting changes at the sensor level in cyber-physical systems: Methodology and technological implementation",
2017 International Joint Conference on Neural Networks (IJCNN), May, 2017.
"Fault Attacks, Injection Techniques and Tools for Simulation",
Hardware Security and Trust: Design and Deployment of Integrated Circuits in a Threatened Environment, First edition; 2016: Springer, pp. 149-167, 2017.
"System-Level Optimization of Accelerator Local Memory for Heterogeneous Systems-on-Chip",
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 36, pp. 435-448, 2017.
"Bridging the Gap between Software and Hardware Designers Using High-Level Synthesis",
Advances in Parallel Computing, 2018.
"The Case for Polymorphic Registers in Dataflow Computing",
International Journal of Parallel Programming, vol. 54, issue 5, pp. 54-62, 10/2018.
"DarkMem: Fine-Grained Power Management of Local Memories for Accelerators in Embedded Systems",
Proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC), 2018.
"Panel IoT and pervasive computing: are new definitions of security and privacy needed?",
Malicious Software and Hardware in Internet of Things Co-located with ACM International Conference on Computing Frontiers 2018, Ischia, Naples, Italy, 05/2018.
"Quantum Era Challenges for Classical Computers",
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, New York, NY, USA, ACM, 2018.
"Securing Hardware Accelerators: a New Challenge for High-Level Synthesis",
IEEE Embedded Systems Letters, vol. 3, issue 10, pp. 77-80, 11/2017, 2018.
"Security: The Dark Side of Approximate Computing?",
Proceedings of the International Conference on Computer-Aided Design, New York, NY, USA, ACM, 11/2018.
"TAO: Techniques for Algorithmic Obscuration during High-Level Synthesis",
Proceedings of the ACM/IEEE Design Automation Conference (DAC), 2018.
"High-Level Synthesis of Benevolent Trojans",
Proceedings of the IEEE Design, Automation and Test in Europe Conference (DATE), 2019.
"Black-Hat High-Level Synthesis: Myth or Reality?",
IEEE Transactions on Very Large Scale Integration Systems, In Press.
"Enabling Automated Bug Detection for IP-based Designs using High-Level Synthesis",
IEEE Design & Test, 2018, In Press.
"TaintHLS: High-Level Synthesis For Dynamic Information Flow Tracking",
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, In Press.