"Power Attacks Resistance of Cryptographic S-boxes with added Error Detection Circuits", proceedings of: '22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'07), Rome, Italy, September 26-28, 2007.
"Can knowledge regarding the presence of countermeasures against fault attacks simplify power attacks on cryptographic devices?", Proceedings of 23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS 08), October 1-3, 2008.
"Low Cost Software Countermeasures Against Fault Attacks: Implementation and Performances Trade Offs", 5th Workshop on Embedded Systems Security (WESS), Scottsdale, Arizona, USA, October, 2010.
"Exploring the Feasibility of Low Cost Fault Injection Attacks on Sub-Threshold Devices through an Example of a 65nm AES Implementation", 7th Workshop on RFID Security and Privacy (RFIDSec), Amherst, Massachussets, USA, June, 2011.
"Interaction between Fault Attack Countermeasures and the Resistance against Power Analysis Attacks", Fault Analysis in Cryptography: Springer Berlin Heidelberg, pp. 257-272, 2012.
"A Combined Design-Time/Test-Time Study of the Vulnerability of Sub-Threshold Devices to Low Voltage Fault Attacks", IEEE Transactions on Emerging Topics in Computing, vol. PP, issue 99, 04/2014.