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Education and Innovation in Embedded Systems Design

USI Università della Svizzera italiana, USI Faculty of Informatics, Advanced Learning and Research Institute USI Università della Svizzera italiana USI Faculty of Informatics USI Advanced Learning and Research Institute
Title200 MS/s ADC implemented in a FPGA employing TDCs
Publication TypeConference Paper
Year of Publication2015
AuthorsHomulle, H., F. Regazzoni, and E. Charbon
Conference NameFPGA International Symposium on Field-Programmable Gate Arrays ACM/SIGDA 2015
Date Published02/2015
PublisherACM
Conference LocationMonterey, CA, USA
ISBN Number978-1-4503-3315-3
Keywordsanalog-through time to digital convertor, FPGA-based design, reference voltage
Abstract

Analog signals are used in many applications and systems, such as cyber physical systems, sensor networks and automotive applications. These are also applications where the use of FPGAs is continuously growing. To date, however there is no direct integration between FPGAs, which are digital, and the analog world (except for the newest generation of FPGAs). Currently, an external analog-to-digital converter (ADC) has to be added to the system, thus limiting its overall compactness and flexibility.

To address this issue we propose a novel architecture implementing a high speed ADC in reconfigurable devices. The system exploits picosecond resolution time-to-digital converters (TDCs) to reach a conversion as fast as its clock speed. The resulting analog-through-time-to-digital converter (ATDC) can achieve a sampling rate of 200 MS/s with a 7 bit resolution for signals ranging from 0 to 2.5 V. Except for the external resistor needed for the analog reference ramp, the system is fully integrated inside the target FPGA. Moreover, our design can be easily scaled for multichannel ADCs, proving the suitability of reconfigurable devices for applications requiring a deep integration between analog and digital world.

URLhttp://doi.acm.org/10.1145/2684746.2689070
DOI10.1145/2684746.2689070