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Education and Innovation in Embedded Systems Design

USI Università della Svizzera italiana, USI Faculty of Informatics, Advanced Learning and Research Institute USI Università della Svizzera italiana USI Faculty of Informatics USI Advanced Learning and Research Institute
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In Press
Pilato, C., K. Basu, F. Regazzoni, and R. Karri, "Black-Hat High-Level Synthesis: Myth or Reality?", IEEE Transactions on Very Large Scale Integration Systems, In Press.
Fezzardi, P., C. Pilato, and F. Ferrandi, "Enabling Automated Bug Detection for IP-based Designs using High-Level Synthesis", IEEE Design & Test, 2018, In Press.
Pilato, C., S. Garg, K. Wu, R. Karri, and F. Regazzoni, "TaintHLS: High-Level Synthesis For Dynamic Information Flow Tracking", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, In Press.
2019
Pilato, C., K. Basu, M. Shayan, F. Regazzoni, and R. Karri, "High-Level Synthesis of Benevolent Trojans", Proceedings of the IEEE Design, Automation and Test in Europe Conference (DATE), 2019.
2018
Pilato, C., "Bridging the Gap between Software and Hardware Designers Using High-Level Synthesis", Advances in Parallel Computing, 2018.
Ciobanu, C. B., G. Gaydadjiev, C. Pilato, and D. Sciuto, "The Case for Polymorphic Registers in Dataflow Computing", International Journal of Parallel Programming, vol. 54, issue 5, pp. 54-62, 10/2018.
Pilato, C., and L. P. Carloni, "DarkMem: Fine-Grained Power Management of Local Memories for Accelerators in Embedded Systems", Proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC), 2018.
Ferrante, A., "Panel IoT and pervasive computing: are new definitions of security and privacy needed?", Malicious Software and Hardware in Internet of Things Co-located with ACM International Conference on Computing Frontiers 2018, Ischia, Naples, Italy, 05/2018.
Regazzoni, F., A. Fowler, and I. Polian, "Quantum Era Challenges for Classical Computers", Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, New York, NY, USA, ACM, 2018.
Pilato, C., S. Garg, R. Karri, and F. Regazzoni, "Securing Hardware Accelerators: a New Challenge for High-Level Synthesis", IEEE Embedded Systems Letters, vol. 3, issue 10, pp. 77-80, 11/2017, 2018.
Regazzoni, F., C. Alippi, and I. Polian, "Security: The Dark Side of Approximate Computing?", Proceedings of the International Conference on Computer-Aided Design, New York, NY, USA, ACM, 11/2018.
Pilato, C., F. Regazzoni, R. Karri, and S. Garg, "TAO: Techniques for Algorithmic Obscuration during High-Level Synthesis", Proceedings of the ACM/IEEE Design Automation Conference (DAC), 2018.
2017
Masin, M., F. Palumbo, H. Myrhaug, J. A. de Oliv Filho, M. Pastena, M. Pelcat, L. Raffo, F. Regazzoni, A. A. Sanchez, A. Toffetti, et al., "Cross-layer Design of Reconfigurable Cyber-Physical Systems", Proceedings of Design, Automation and Test in Europe (DATE) 2017, 2017.
Masin, M., F. Palumbo, H. Myrhaug, J. A. de Oliv Filho, M. Pastena, M. Pelcat, L. Raffo, F. Regazzoni, A. A. Sanchez, A. Toffetti, et al., "Cross-layer Design of Reconfigurable Cyber-Physical Systems", Proceedings of Design, Automation and Test in Europe (DATE) 2017, 2017.
Masin, M., F. Palumbo, H. Myrhaug, J. A. de Oliv Filho, M. Pastena, M. Pelcat, L. Raffo, F. Regazzoni, A. A. Sanchez, A. Toffetti, et al., "Cross-layer Design of Reconfigurable Cyber-Physical Systems", Proceedings of Design, Automation and Test in Europe (DATE) 2017, 2017.
Alippi, C., V. D'Alto, M. Falchetto, D. Pau, and M. Roveri, "Detecting changes at the sensor level in cyber-physical systems: Methodology and technological implementation", 2017 International Joint Conference on Neural Networks (IJCNN), May, 2017.
Piscitelli, R., S. Bhasin, and F. Regazzoni, "Fault Attacks, Injection Techniques and Tools for Simulation", Hardware Security and Trust: Design and Deployment of Integrated Circuits in a Threatened Environment, First edition; 2016: Springer, pp. 149-167, 2017.
Pilato, C., P. Mantovani, G. Di Guglielmo, and L. P. Carloni, "System-Level Optimization of Accelerator Local Memory for Heterogeneous Systems-on-Chip", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 36, pp. 435-448, 2017.
2016
Banik, S., A. Bogdanov, T. Fanni, C. Sau, L. Raffo, F. Palumbo, and F. Regazzoni, "Adaptable AES implementation with power-gating support", International Conference on Computing Frontiers CF'16, Como, Italy, ACM Ney York, NY, USA, pp. 331-334, 05/2016.
Balać, K., M. Akhmedov, M. Prevostini, and M. Malek, "Topology Optimization of Wireless Localization Networks", European Wireless 2016 , Oulu, Finland, 05/2016.

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