Export 131 results:
Author Title [ Type] Year Filters: First Letter Of Last Name is S [Clear All Filters]
"A system-level approach to adaptivity and fault-tolerance in NoC-based MPSoCs: The MADNESS project.",
Microprocessors and Microsystems - Embedded Hardware Design, vol. 37, issue 6-7, pp. 515–529, 2013.
"A system-level approach to adaptivity and fault-tolerance in NoC-based MPSoCs: The MADNESS project.",
Microprocessors and Microsystems - Embedded Hardware Design, vol. 37, issue 6-7, pp. 515–529, 2013.
"Secure Memory Accesses on Networks-on-Chip",
IEEE Transactions on Computers, vol. 57, no. 9, pp. 1216-1229, September, 2008.
"OSCAR: an Optimization Methodology Exploiting Spatial Correlation in Multi-core Design Space",
IEEE Transactions on Computer-Aided Design, vol. 21, issue 5, no. -: IEEE, pp. 740-753, 05/2012.
"Midori: (A) Block Cipher for Low Energy (Extended Version)",
(IACR) Cryptology ePrint Archive, vol. 2015, 12/2015.
"Linking run-time resource management of embedded multi-core platforms with automated design-time exploration",
IET Computers and Digital Techniques, vol. 5, no. -, pp. 123–135, 2011.
"An Investigation of Sources of Randomness Within Discrete Gaussian Sampling",
IACR Cryptology ePrint Archive, vol. 2017, pp. 298, 2017.
"Harvesting the potential of nano-CMOS for lightweight cryptography: An ultra-low-voltage 65 nm AES coprocessor for passive RFID tags",
Springer Journal of Cryptographic Engineering, vol. 1, issue 1, 2011.
"Fault-Tolerant Network Interfaces for Networks-on-Chip",
IEEE Trans. Dependable Secur. Comput., vol. 11, issue 1, pp. 16–29, 01/2014.
"Design-space Exploration and Runtime Resource Management for Multicores",
ACM Transactions on Embedded Computing Systems (TECS) - Special issue on application-specific processors, vol. 13, issue 2, pp. 20:1–20:27, 09/2013.
"A Configurable Monitoring Infrastructure for NoC-Based Architectures",
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. PP, issue 99, 2013.
"A Combined Design-Time/Test-Time Study of the Vulnerability of Sub-Threshold Devices to Low Voltage Fault Attacks",
IEEE Transactions on Emerging Topics in Computing, vol. PP, issue 99, 04/2014.
"The Case for Polymorphic Registers in Dataflow Computing",
International Journal of Parallel Programming, vol. 54, issue 5, pp. 54-62, 10/2018.
"Breaking ECC2K-130",
IACR Cryptology ePrint Archive, vol. 2009, pp. 541, 11/2009.
"Automatic Application of Power Analysis Countermeasures",
IEEE Transactions on Computers , vol. 64, issue 2, pp. 329-341, 02/2015.
"Automatic Application of Power Analysis Countermeasures",
IEEE Transactions on Computers, vol. PP, issue 99, 12/2013.
"ARTE: an Application-specific Run-Time Management Framework for Multi-cores based on Queuing Models",
Parallel Computing, 2013.
"An Application Level Synthesis Methodology for Multidimensional Embedded Processing Systems",
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 11, pp. 1457-1470, November, 2003.
"Adaptivity Support for MPSoCs based on Process Migration in Polyhedral Process Networks",
VLSI Design, vol. 2012, no. Article ID 987209: Hindawi, pp. 15 pages, February, 2012.