Export 65 results:
Author Title [ Type] Year Filters: First Letter Of Last Name is C [Clear All Filters]
Reconfigurable Logic Circuit,
, no. GB1719355.8, 11/2017, Submitted.
"Towards Self-adaptive KPN Applications on NoC-based MPSoCs",
Advances in Software Engineering, vol. 2012, pp. 16 pages, September, 2012.
"System-Level Optimization of Accelerator Local Memory for Heterogeneous Systems-on-Chip",
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 36, pp. 435-448, 2017.
"A system-level approach to adaptivity and fault-tolerance in NoC-based MPSoCs: The MADNESS project.",
Microprocessors and Microsystems - Embedded Hardware Design, vol. 37, issue 6-7, pp. 515–529, 2013.
"Secure Memory Accesses on Networks-on-Chip",
IEEE Transactions on Computers, vol. 57, no. 9, pp. 1216-1229, September, 2008.
"Customized Instructions for Protection Against Memory Integrity Attacks",
IEEE Embedded Systems Letters, In Press.
"Credit Card Fraud Detection: A Realistic Modeling and a Novel Learning Strategy",
IEEE Transactions on Neural Networks and Learning Systems, pp. 1-14, 2018.
"The Case for Polymorphic Registers in Dataflow Computing",
International Journal of Parallel Programming, vol. 54, issue 5, pp. 54-62, 10/2018.
"Breaking ECC2K-130",
IACR Cryptology ePrint Archive, vol. 2009, pp. 541, 11/2009.
"Breaking ECC2K-130",
IACR Cryptology ePrint Archive, vol. 2009, pp. 541, 11/2009.
"Adaptivity Support for MPSoCs based on Process Migration in Polyhedral Process Networks",
VLSI Design, vol. 2012, no. Article ID 987209: Hindawi, pp. 15 pages, February, 2012.
"CCM: Controlling the Change Magnitude in High Dimensional Data",
In Proceedings of the 2nd INNS Conference on Big Data 2016 (INNS Big Data 2016), Thessaloniki, Greece, pp. 1-10, 10/2016.
"Yield Enhancement by Robust Application-specific Mapping on Network-on-Chips",
NoCArc'09: Proceedings of the Second International Workshop on Network on-Chip Architectures, New York City, USA, pp. 37–42, December, 2009.
"Trace-based KPN Composability Analysis for Mapping Simultaneous Applications to MPSoC Platforms",
Proceedings of Design, Automation and Test in Europe(DATE) Conference, Dresden, Germany, March, 2010.
"Trace-based KPN Composability Analysis for Mapping Simultaneous Applications to MPSoC Platforms",
Proceedings of Design, Automation and Test in Europe(DATE) Conference, Dresden, Germany, March, 2010.
"Towards an ESL design framework for adaptive and fault-tolerant MPSoCs: MADNESS or not?",
Embedded Systems for Real-Time Multimedia (ESTIMedia), 2011 9th IEEE Symposium on, 2011.
"A Topology Design Customization Approach for (STNoC)",
Nano-Nets 07, in proceedings of 2nd International Conference on Nano-Networks (Nano-Nets 2007)., Catania, Italy, September 24-26, 2007.
"A system level model of possible integration of Building Management System in SmartGrid",
Complexity in Engineering (COMPENG 2010), Rome, Italy, February 22-24, 2010.