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Education and Innovation in Embedded Systems Design

USI Università della Svizzera italiana, USI Faculty of Informatics, Advanced Learning and Research Institute USI Università della Svizzera italiana USI Faculty of Informatics USI Advanced Learning and Research Institute
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A
Luković, S., "Adapting Multi-Agent Systems Approach for Integration of Prosumers in Smart Grids", Proceedings of the IEEE Eurocon 2013, July, 2013.
Luković, S., I. Kaitović, and U. Bondi, "Adopting system engineering methodology to Virtual Power Systems design flow", CPSWEEK/GREEMBED 2010: Proceedings of the First Workshop on Green and Smart Embedded System Technology: Infrastructures, Methods and Tools, Stockholm, Sweden, April, 2010.
Kaitović, I., and S. Luković, "Adoption of Model-Driven methodology to aggregations design in Power Grid", INDIN '11: Proceedings of the 9th IEEE International Conference on Industrial Informatics, Caparica, Lisbon, Portugal, pp. 1–6, July 26-29, 2011.
Cappiello, C., A. Hinostroza, B. Pernici, M. Sami, E. Henis, R. I. Kat, K. Z. Meth, and M. Mura, "ADSC: Application-Driven Storage Control for Energy Efficiency", Information and Communication on Technology for the Fight against Global Warming - First International Conference ICT-GLOW, vol. 6868, Toulouse, France, Springer, pp. 165-179, 08/2011.
Gamrat, C., J-M. Philippe, C. Jesshope, A. Shafarenko, L. Bisdounis, U. Bondi, A. Ferrante, J. Cabestany, M. Huebner, J. Parsinnen, et al., "AETHER: Self-Adaptive Networked Entities: Autonomous Computing Elements for Future Pervasive Applications and Technologies", Reconfigurable Computing: From FPGAs to Hardware/Software Codesign, New York, USA, Springer, pp. 149–184, 2011.
Kozma, R., C. Alippi, Y. Choe, and F. Morabito, "Artificial Intelligence in the Age of Neural Networks and Brain Computing", Academic Press , 1, pp. 420, 2018.
B
Krdu, A., Y. Lebrun, U. Ahmad, S. Pollin, and M. Li, "Beamforming for interference mitigation and its implementation on an SDR baseband processor", SiPS'11: Proceedings of the IEEE Workshop on Signal Processing Systems, Beirut, Lebanon, pp. 1–6, October 4-7, 2011.
Pilato, C., K. Basu, F. Regazzoni, and R. Karri, "Black-Hat High-Level Synthesis: Myth or Reality?", IEEE Transactions on Very Large Scale Integration Systems, In Press.
Bailey, D. V., L. Batina, D. J. Bernstein, P. Birkner, J. W. Bos, H. - Chung Chen, C. - Mou Cheng, G. van Damme, T. Güneysu, F. Gurkaynak, et al., "Breaking ECC2K-130", IACR Cryptology ePrint Archive, vol. 2009, pp. 541, 11/2009.
C
Regazzoni, F., T. Eisenbarth, L. Breveglieri, P. Ienne, and I. Koren, "Can knowledge regarding the presence of countermeasures against fault attacks simplify power attacks on cryptographic devices?", Proceedings of 23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS 08), October 1-3, 2008.
Bailey, D. V., B. Baldwin, L. Batina, D. J. Bernstein, P. Birkner, J. W. Bos, G. van Damme, G. de Meulenaer, J. Fan, F. Gurkaynak, et al., "The Certicom Challenges ECC2-X", Workshop on Special Purpose Hardware for Attacking Cryptographic Systems (SHARCS), Lausanne, Switzerland, September, 2009.
Barenghi, A., C. Hocquet, D. Bol, F-X. Standaert, F. Regazzoni, and I. Koren, "A Combined Design-Time/Test-Time Study of the Vulnerability of Sub-Threshold Devices to Low Voltage Fault Attacks", IEEE Transactions on Emerging Topics in Computing, vol. PP, issue 99, 04/2014.
Eisenbarth, T., Z. Gong, T. Gneysu, S. Heyse, S. Indesteege, S. Kerckhof, F. Koeune, T. Nad, T. Plos, F. Regazzoni, et al., "Compact Implementation and Performance Evaluation of Block Ciphers in ATtiny Devices", Progress in Cryptology - Africacrypt, Ifrance, Morocco, July, 2012.
Eisenbarth, T., Z. Gong, T. Gneysu, S. Heyse, S. Indesteege, S. Kerckhof, F. Koeune, T. Nad, T. Plos, F. Regazzoni, et al., "Compact Implementation and Performance Evaluation of Block Ciphers in ATtiny Devices", Progress in Cryptology - Africacrypt, Ifrance, Morocco, July, 2012.
Balasch, J., B. Ege, T. Eisenbarth, B. Grard, Z. Gong, T. Gneysu, S. Heyse, S. Kerckhof, F. Koeune, T. Plos, et al., "Compact Implementation and Performance Evaluation of Hash Functions in ATtiny Devices", 11th Smart Card Research and Advanced Application Conference (CARDIS), Graz, Austria, November, 2012.
Balasch, J., B. Ege, T. Eisenbarth, B. Grard, Z. Gong, T. Gneysu, S. Heyse, S. Kerckhof, F. Koeune, T. Plos, et al., "Compact Implementation and Performance Evaluation of Hash Functions in ATtiny Devices", 11th Smart Card Research and Advanced Application Conference (CARDIS), Graz, Austria, November, 2012.
Khalid, A., J. Howe, C. Rafferty, F. Regazzoni, and M. O'Neil, "Compact, Scalable, and Efficient Gaussian Samplers for Lattice-Based Cryptography", Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) 2018, 2018.
D
Regazzoni, F., A. Cevrero, F-X. Standaert, S. Badel, T. Kluter, P. Brisk, Y. Leblebici, and P. Ienne, "A Design Flow and Evaluation Framework for DPA-resistant Instruction Set Extensions", Cryptographic Hardware and Embedded Systems (CHES), vol. 5747, Lausanne, Switzerland, Springer Berlin Heidelberg, pp. 205-219, September, 2009.
Kavka, C., A. Turco, G. Palermo, C. Silvano, V. Zaccaria, G. Mariani, S. Bocchio, and F. Dongrui, "Design Space Exploration of Parallel Architectures", Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach, New York, USA, Springer, 2011.
Valencia, F., A. Khalid, E. O'Sullivan, and F. Regazzoni, "The design space of the number theoretic transform: A survey", 2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, {SAMOS} 2017, Pythagorion, Greece, July 17-20, 2017 (Invited), 2017.

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