Export 54 results:
Author [ Title] Type Year Filters: First Letter Of Last Name is D [Clear All Filters]
"Adaptivity Support for MPSoCs based on Process Migration in Polyhedral Process Networks",
VLSI Design, vol. 2012, no. Article ID 987209: Hindawi, pp. 15 pages, February, 2012.
"AETHER: Self-Adaptive Networked Entities: Autonomous Computing Elements for Future Pervasive Applications and Technologies",
Reconfigurable Computing: From FPGAs to Hardware/Software Codesign, New York, USA, Springer, pp. 149–184, 2011.
"AETHER: Self-Adaptive Networked Entities: Autonomous Computing Elements for Future Pervasive Applications and Technologies",
Reconfigurable Computing: From FPGAs to Hardware/Software Codesign, New York, USA, Springer, pp. 149–184, 2011.
"An ASIC design for a high speed implementation of the hash function SHA-256 (384, 512)",
GLSVLSI '04: Proceedings of the 14th ACM Great Lakes symposium on VLSI, Boston, MA, USA, ACM Press, New York, USA, pp. 421–425, 2004.
"The Certicom Challenges ECC2-X",
Workshop on Special Purpose Hardware for Attacking Cryptographic Systems (SHARCS), Lausanne, Switzerland, September, 2009.
"Challenges in designing trustworthy cryptographic co-processors",
IEEE International Symposium on Circuits and Systems (ISCAS) 2015, Lisbon, Portugal, IEEE, pp. 2009-2012, 09/2015.
"COOPER: Towards A Collaborative Open Environment of Project-centred Learning",
proceedings to EC-TEL'06 conference, Crete, Greece, October 1-4, 2006.
"Coordinated management of hardware and software self-adaptivity",
Journal of Systems Architecture, vol. 55, issue 3, no. {3}, pp. 170 - 179, 03/2009.
"Credit Card Fraud Detection: A Realistic Modeling and a Novel Learning Strategy",
IEEE Transactions on Neural Networks and Learning Systems, pp. 1-14, 2018.
"Cross-layer Design of Reconfigurable Cyber-Physical Systems",
Proceedings of Design, Automation and Test in Europe (DATE) 2017, 2017.
"The Design of a High Speed ASIC Unit for the Hash Function SHA-256 (384,512)",
DATE '04: Proceedings of the conference on Design, automation and test in Europe, Washington, DC, USA, IEEE Computer Society, pp. 30070, 2004.
"Design Space Exploration of Parallel Architectures",
Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach, New York, USA, Springer, 2011.
"Detecting changes at the sensor level in cyber-physical systems: Methodology and technological implementation",
2017 International Joint Conference on Neural Networks (IJCNN), May, 2017.
"Enabling Self-adaptivity in Component-based Streaming Applications",
ACM SIGBED Review - Special Issue on the 2nd International Workshop on Adaptive and Reconfigurable Embedded Systems, vol. 6, no. {3}: ACM SIGBED, pp. 14:1-14:4, 10/2009.
"Energy-Throughput Simulation Approach for Heterogeneous LTE scenarios",
ISWCS'11: Proceedings of The Eighth International Symposium on Wireless Communication Systems, Aachen, Germany, pp. 1–5, November 6-9, 2011.
"ExCovery – A Framework for Distributed System Experiments and a Case Study of Service Discovery",
28th International Parallel & Distributed Processing Symposium, Workshops and Phd Forum (IPDPSW), Phoenix, AZ, USA, IEEE Computer Society, 05/2014.
Hardware Security and Trust: Design and Deployment of Integrated Circuits in a Threatened Environment,
, First edition; 2016: Springer, 2017.
"Learning Java by a Card Game: A Case Study",
LG2007: Proceedings of Learning with Games Conference, Sophia Antipolis, France, pp. 221–228, September 24-27, 2007.
"Low Cost FPGA Implementations of the SHA-3 Finalists",
10th Smart Card Research and Advanced Application Conference (CARDIS), Leuven, Belgium, September, 2011.
"Low Cost FPGA Implementations of the SHA-3 Finalists",
10th Smart Card Research and Advanced Application Conference (CARDIS), Leuven, Belgium, September, 2011.