Export 60 results:
[ Author] Title Type Year Filters: First Letter Of Last Name is M [Clear All Filters]
"Small-scale Variants of the Secure Hash Standard",
ECRYPT workshop on RFID and lightweight cryptography, Graz, Austria, July 14-15, 2005.
"Quasi-Pipelined Hash Circuits",
IEEE ARITH 17, Cape Cod, pp. 222-229, June, 2005.
Method of implementing one-to-one binary function and relative hardware device, especially for a Rijndael S-box,
, no. US 10/816,791 -- EP 20030425211, 10/2004.
"ASIC Hardware Implementation of the IDEA NXT Encryption Algorithm",
IEEE International Symposium on Circuits and Systems, Kos, Greece, May 21-24, 2006.
Method and circuit for data encryption/decryption,
, no. US 09/974,705, April, 2003.
"Hardware Implementation of the Rijndael Sbox: a Case Study",
ST Journal of System Research, pp. 84-91, July, 2003.
"Design Space Exploration of PISA Architecture For ONU Auto-discovery Process",
proceedings of 6th International Conference of Electrical Engineering (ICEENG), Cairo, Egypt, May 27-29, 2009.
"Securability: the Key Challenge for Autonomic and Trusted Computing",
IEEE International Conference on Ubiquitous Intelligence Computing / International Conference on Autonomic Trusted Computing (UIC/ATC), 9, 03/2012.
"Predictive Analytics: A Shortcut to Dependable Computing",
Software Engineering for Resilient Systems, Cham, Springer International Publishing, 2017.
"Design-space Exploration and Runtime Resource Management for Multicores",
ACM Transactions on Embedded Computing Systems (TECS) - Special issue on application-specific processors, vol. 13, issue 2, pp. 20:1–20:27, 09/2013.
"An industrial design space exploration framework for supporting run-time resource management on multi-core systems",
Proceedings of Design, Automation and Test in Europe (DATE) Conference, Dresden, Germany, March, 2010.
"Multicube Explorer - A Design Space Exploration Framework for Embedded Systems-on-Chip",
Proceedings of the DATE'09 workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications, Nice, France, April, 2009.
"Design Space Exploration of a Reconfigurable System for Supporting Video Streaming Run-time Management",
Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach, New York, USA, Springer, 2011.
"Design Space Exploration for Run-Time Management of a Reconfigurable System for Video Streaming",
Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach, 1: Springer, pp. 189-204, 2011.
"An Efficient Run-Time Management Methodology for Stereo Matching Application",
2PARMA: Proceedings of the Workshop on Parallel Programming and Run-time Management Techniques for Many-core Architectures, Hannover, Germany, February, 2010.
"An Efficient Design Space Exploration Methodology for Multi-Cluster VLIW Architectures based on Artificial Neural Networks",
Proc. IFIP International Conference on Very Large Scale Integration VLSI - SoC 2008, Rhodes Island, Greece, October 13-15, 2008.
"Meta-model Assisted Optimization for Design Space Exploration of Multi-Processor Systems-on-Chip",
Euromicro Proceedings of DSD'09 - Conference on Digital System Design, Patras, Greece, August, 2009.
"ARTE: an Application-specific Run-Time Management Framework for Multi-cores based on Queuing Models",
Parallel Computing, 2013.
"Run-time Optimization of a Dynamically Reconfigurable Embedded System Through Performance Prediction",
23rd International Conference on Field Programmable Logic and Applications (FPL), Porto, Portugal, IEEE, 09/2013.
"A Correlation-based Design Space Exploration Methodology for Multi-Processor Systems-on-Chip",
Proceedings of DAC 2010: Design Automation Conference, Anheim, CA, USA, pp. 120–125, June, 2010.