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Education and Innovation in Embedded Systems Design

USI Università della Svizzera italiana, USI Faculty of Informatics, Advanced Learning and Research Institute USI Università della Svizzera italiana USI Faculty of Informatics USI Advanced Learning and Research Institute
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Conference Paper
Meloni, P., G. Tuveri, L. Raffo, E. Cannella, T. Stefanov, O. Derin, L. Fiorin, and M. Sami, "System Adaptivity and Fault-tolerance in NoC-based MPSoCs: the MADNESS Project Approach", Proceedings of the 15th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD'12), Izmir, Turkey, September 5-8, 2012.
Meloni, P., G. Tuveri, L. Raffo, E. Cannella, T. Stefanov, O. Derin, L. Fiorin, and M. Sami, "System Adaptivity and Fault-tolerance in NoC-based MPSoCs: the MADNESS Project Approach", Proceedings of the 15th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD'12), Izmir, Turkey, September 5-8, 2012.
Luković, S., and A. Srivastava, "System Level Approach to Denial-of-Service Detection in MPSoCs", Proceedings of the 7th Workshop on Embedded Systems Security (WESS'2012), A Workshop of the Embedded Systems Week (ESWEEK'12), 10/2012.
Güneys, T., F. Regazzoni, P. Sasdrich, and M. Wojcik, "(THOR) - The hardware onion router", 24th International Conference on Field Programmable Logic and Applications, (FPL) 2014, Munich, Germany, IEEE, 09/2014.
Palermo, G., G. Mariani, C. Silvano, R. Locatelli, and M. Coppola, "A Topology Design Customization Approach for (STNoC)", Nano-Nets 07, in proceedings of 2nd International Conference on Nano-Networks (Nano-Nets 2007)., Catania, Italy, September 24-26, 2007.
Castrillón, J., R. Velásquez, A. Stulova, W. Sheng, J. Ceng, R. Leupers, G. Ascheid, and H. Meyr, "Trace-based KPN Composability Analysis for Mapping Simultaneous Applications to MPSoC Platforms", Proceedings of Design, Automation and Test in Europe(DATE) Conference, Dresden, Germany, March, 2010.
Castrillón, J., R. Velásquez, A. Stulova, W. Sheng, J. Ceng, R. Leupers, G. Ascheid, and H. Meyr, "Trace-based KPN Composability Analysis for Mapping Simultaneous Applications to MPSoC Platforms", Proceedings of Design, Automation and Test in Europe(DATE) Conference, Dresden, Germany, March, 2010.
Piscopo, G., M. Prevostini, and I. Stefanini, "UML System-Level Analysis and Design of Secure Communication Schemes for Embedded Systems", FDL'04, Lille, France, pp. 301-312, September 14-17, 2004.
Mariani, G., V-M. Sima, G. Palermo, V. Zaccaria, C. Silvano, and K. Bertels, "Using Multi-objective Design Space Exploration to Enable Run-time Resource Management for Reconfigurable Architectures", Proc. Design, Automation Test in Europe Conf. Exhibition (DATE), March, 2012.
Mariani, G., V-M. Sima, G. Palermo, V. Zaccaria, C. Silvano, and K. Bertels, "Using Multi-objective Design Space Exploration to Enable Run-time Resource Management for Reconfigurable Architectures", Proc. Design, Automation Test in Europe Conf. Exhibition (DATE), March, 2012.
Choudhury, A D., G. Palermo, C. Silvano, and V. Zaccaria, "Yield Enhancement by Robust Application-specific Mapping on Network-on-Chips", NoCArc'09: Proceedings of the Second International Workshop on Network on-Chip Architectures, New York City, USA, pp. 37–42, December, 2009.
Journal Article
Cannella, E., O. Derin, P. Meloni, G. Tuveri, and T. Stefanov, "Adaptivity Support for MPSoCs based on Process Migration in Polyhedral Process Networks", VLSI Design, vol. 2012, no. Article ID 987209: Hindawi, pp. 15 pages, February, 2012.
Alippi, C., A. Galbusera, and M. Stellini, "An Application Level Synthesis Methodology for Multidimensional Embedded Processing Systems", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 11, pp. 1457-1470, November, 2003.
Mariani, G., G. Palermo, V. Zaccaria, and C. Silvano, "ARTE: an Application-specific Run-Time Management Framework for Multi-cores based on Queuing Models", Parallel Computing, 2013.
Bayrak, A. Galip, F. Regazzoni, D. Novo Bruna, P. Brisk, F-X. Standaert, and P. Ienne, "Automatic Application of Power Analysis Countermeasures", IEEE Transactions on Computers, vol. PP, issue 99, 12/2013.
Bayrak, A. Galip, F. Regazzoni, D. Novo, P. Brisk, F-X. Standaert, and P. Ienne, "Automatic Application of Power Analysis Countermeasures", IEEE Transactions on Computers , vol. 64, issue 2, pp. 329-341, 02/2015.
Bailey, D. V., L. Batina, D. J. Bernstein, P. Birkner, J. W. Bos, H. - Chung Chen, C. - Mou Cheng, G. van Damme, T. Güneysu, F. Gurkaynak, et al., "Breaking ECC2K-130", IACR Cryptology ePrint Archive, vol. 2009, pp. 541, 11/2009.
Ciobanu, C. B., G. Gaydadjiev, C. Pilato, and D. Sciuto, "The Case for Polymorphic Registers in Dataflow Computing", International Journal of Parallel Programming, vol. 54, issue 5, pp. 54-62, 10/2018.
Barenghi, A., C. Hocquet, D. Bol, F-X. Standaert, F. Regazzoni, and I. Koren, "A Combined Design-Time/Test-Time Study of the Vulnerability of Sub-Threshold Devices to Low Voltage Fault Attacks", IEEE Transactions on Emerging Topics in Computing, vol. PP, issue 99, 04/2014.
Fiorin, L., G. Palermo, and C. Silvano, "A Configurable Monitoring Infrastructure for NoC-Based Architectures", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. PP, issue 99, 2013.

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