Export 140 results:
Author [ Title
] Type Year Filters: First Letter Of Last Name is P [Clear All Filters]
"An industrial design space exploration framework for supporting run-time resource management on multi-core systems",
Proceedings of Design, Automation and Test in Europe (DATE) Conference, Dresden, Germany, March, 2010.
"Implementation of a Reconfigurable Data Protection Module for NoC-based MPSoCs",
Proceedings of the 21st IPDPS 2007 Reconfigurable Architecture Workshop (RAW), 21th IEEE International Parallel and Distributed Processing Symposium, Miami, USA/FL, April, 2008.
"High-Level Synthesis of Benevolent Trojans",
Proceedings of the IEEE Design, Automation and Test in Europe Conference (DATE), 2019.
"High-level Architecture of an IPSec-dedicated System on Chip",
proceedings of NGI 2007, Trondheim, Norway, IEEE Press, May, 2007.
"Hardware-assisted Security Enhanced Linux in Embedded Systems: a Proposal",
Proceedings of the 5th Workshop on Embedded Systems Security (WESS'2010), Scottsdale, Arizona, USA, October 24, 2010.
"Functional model of Virtual Power Plant (VPP)",
Proceedings of the 2010 CIGRE (International Council on Large Electric Systems) Session, Paris, France, July, 2010.
"Fresh Re-Keying II: Securing Multiple Parties against Side-Channel and Fault Attacks",
10th Smart Card Research and Advanced Application Conference (CARDIS), Leuven, Belgium, September, 2011.
"Fault Attacks, Injection Techniques and Tools for Simulation",
Hardware Security and Trust: Design and Deployment of Integrated Circuits in a Threatened Environment, First edition; 2016: Springer, pp. 149-167, 2017.
"Fault attacks, injection techniques and tools for simulation",
10th International Conference on Design Technology of Integrated Systems in Nanoscale Era DTIS 2015, Naples, Italy, IEEE, pp. 1-6, 04/2015.
"Executable Models and Verification from MARTE and SysML: a Comparative Study of Code Generation Capabilities",
Proceedings of MARTE Workshop (DATE08), Munich, Germany, March, 2008.
"Executable Models and Verification from MARTE and SysML: a Comparative Study of Code Generation Capabilities",
Proceedings of MARTE Workshop (DATE08), Munich, Germany, March, 2008.
"Evaluating Run-time Resource Management Policies for Multi-core Embedded Platforms with the EMME Evaluation Framework",
Workshop on Parallel Programming and Run-time Management Techniques for Many-core Architectures, February, 2012.
"Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology",
Springer Transactions on Computational Science, vol. 5430, pp. 230–243, February, 2009.
"Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology",
Springer Transactions on Computational Science, vol. 5430, pp. 230–243, February, 2009.
"Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology",
Springer Transactions on Computational Science, vol. 5430, pp. 230–243, February, 2009.
"An Enhanced Service Provider Communication Interface with Client Priorization",
proceedings of IEEE/WFMC International Conference on e-Business, July 26-29, 2008.
"Enabling Automated Bug Detection for IP-based Designs using High-Level Synthesis",
IEEE Design & Test, 2018, In Press.
"An Efficient Design Space Exploration Methodology for Multi-Cluster VLIW Architectures based on Artificial Neural Networks",
Proc. IFIP International Conference on Very Large Scale Integration VLSI - SoC 2008, Rhodes Island, Greece, October 13-15, 2008.
"Efficient C implementation of the ECC and AES cryptographic systems",
Technology Leadership Day - organized by the MicroSwiss Network, Fribourg, October 10, 2001.
"DRuiD: Designing Reconfigurable Architectures with Decision-making Support",
19th Asia and South Pacific Design Automation Conference (ASP-DAC), Singapore, 01/2014.