Export 105 results:
Author Title [ Type
] Year Filters: Author is Francesco Regazzoni [Clear All Filters]
"High-Level Synthesis of Benevolent Trojans",
Proceedings of the IEEE Design, Automation and Test in Europe Conference (DATE), 2019.
"Instruction Set Extensions for secure applications",
Design, Automation Test in Europe Conference DATE 2016, Dresden, Germany, IEEE, pp. 1529-1534, 03/2016.
"Interface Synthesis in Multiprocessing Systems-on-Chips",
IP Based SoC Design 2004, Grenoble, December, 2004.
"Inverse Gating for Low Energy Block Ciphers",
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2018.
"Jailbreak Imagers: Transforming a Single-Photon Image Sensor into a True Random Number Generator",
International Image Sensor Workshop (IISW), Snowbird Resort, Utah, USA, June, 2013.
"Lattice-based cryptography: From reconfigurable hardware to ASIC",
2016 International Symposium on Integrated Circuits (ISIC): IEEE, 12/2016.
"LEXCOMM: A low energy, secure and flexible communication protocol for a heterogenous body sensor network",
IEEE-EMBS International Conference on Biomedical and Health Informatics, Hong Kong, China, January, 2012.
"Lightweight AES-Based Authenticated Encryption",
Fast Software Encryption (FSE), Singapore, March, 2013.
"Low Cost FPGA Implementations of the SHA-3 Finalists",
10th Smart Card Research and Advanced Application Conference (CARDIS), Leuven, Belgium, September, 2011.
"Low Cost Software Countermeasures Against Fault Attacks: Implementation and Performances Trade Offs",
5th Workshop on Embedded Systems Security (WESS), Scottsdale, Arizona, USA, October, 2010.
"Malicious Wave: a Survey on Actively Tampering Using Electromagnetic Glitch",
International Symposium on Electromagnetic Compatibility 2014, 08/2014.
"Midori: A Block Cipher for Low Energy",
21st International Conference on the Theory and Application of Cryptology and Information Security ASIACRYPT 2015, vol. 9453, Auckland, New Zealand, Springer Berlin Heidelberg, pp. 411-436, 11/2015.
"Physical Attacks and Beyond",
Proceedings of the Selected Areas in Cryptography: 23nd International Conference (SAC) 2016, 2016.
"Physical attacks, introduction and application to embedded processors",
10th International Conference on Design Technology of Integrated Systems in Nanoscale Era DTIS 2015, Napoli, Italy, IEEE, pp. 1, 06/2015.
"Power and Performance Optimized Hardware Classifiers for Eefficient On-device Malware Detection",
Cryptography and Security in Computing Systems, Valencia, Spain, ACM, 01/2019.
"Power Attacks Resistance of Cryptographic S-boxes with added Error Detection Circuits",
proceedings of: '22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'07), Rome, Italy, September 26-28, 2007.
"Power-Gated MOS Current Mode Logic (PG-MCML): A Power-Aware DPA-Resistant Standard Cell Library",
48th Design Automation Conference (DAC), San Diego, Califorina, June, 2011.
"Quantum Era Challenges for Classical Computers",
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, New York, NY, USA, ACM, 2018.
"Rapid Creation of Application Models from Bandwidth Aware Core Graphs",
Proceedings of: IP Based SoC Design 2007, Grenoble, France, December 5-6, 2007.
"A Reconfigurable Multiprocessor Architecture for a Reliable Face Recognition Implementation",
Proceedings of Design, Automation and Test in Europe (DATE) Conference, Dresden, Germany, March, 2010.