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"Security: The Dark Side of Approximate Computing?",
Proceedings of the International Conference on Computer-Aided Design, New York, NY, USA, ACM, 11/2018.
"Security IPs and IP Security with FPGAs",
Secure Smart Embedded Devices Platform and Applications, 2014.
"Security Enhanced Linux on Embedded Systems: a Hardware-accelerated Implementation",
17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012, Sydney, Australia, 02/2012.
"Security Challenges for Hardware Designers of Mobile Systems",
2015 Mobile Systems Technologies Workshop (MST), May, 2015.
"Securing Hardware Accelerators: a New Challenge for High-Level Synthesis",
IEEE Embedded Systems Letters, vol. 3, issue 10, pp. 77-80, 11/2017, 2018.
"Secure architectures of future emerging cryptography",
International Conference on Computing Frontiers CF'16, Como, italy, ACM New York, pp. 315-322, 05/2016.
"SCA-Resistance for AES: How Cheap Can We Go?",
Progress in Cryptology – AFRICACRYPT 2018, Cham, Springer International Publishing, 2018.
"Round gating for low energy block ciphers",
2016 IEEE International Symposium on Hardware Oriented Security and Trust, HOST, McLean, VA, USA, IEEE Computer Society, pp. 55-60, 05/2016.
"Rethinking Secure FPGAs: TowardsCryptography-friendly Configurable Cell Architecture and its Automated Design Flow",
Proceedings of FCCM, 05/2018.
"A Reconfigurable Multiprocessor Architecture for a Reliable Face Recognition Implementation",
Proceedings of Design, Automation and Test in Europe (DATE) Conference, Dresden, Germany, March, 2010.
Reconfigurable Logic Circuit,
, no. GB1719355.8, 11/2017, Submitted.
"Rapid Creation of Application Models from Bandwidth Aware Core Graphs",
Proceedings of: IP Based SoC Design 2007, Grenoble, France, December 5-6, 2007.
"Quantum Era Challenges for Classical Computers",
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, New York, NY, USA, ACM, 2018.
"On Practical Discrete Gaussian Samplers For Lattice-Based Cryptography",
IEEE Transaction on Computers, In Press.
"Power-Gated MOS Current Mode Logic (PG-MCML): A Power-Aware DPA-Resistant Standard Cell Library",
48th Design Automation Conference (DAC), San Diego, Califorina, June, 2011.
"Power Attacks Resistance of Cryptographic S-boxes with added Error Detection Circuits",
proceedings of: '22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'07), Rome, Italy, September 26-28, 2007.
"Power and Performance Optimized Hardware Classifiers for Eefficient On-device Malware Detection",
Cryptography and Security in Computing Systems, Valencia, Spain, ACM, 01/2019.
"Physical attacks, introduction and application to embedded processors",
10th International Conference on Design Technology of Integrated Systems in Nanoscale Era DTIS 2015, Napoli, Italy, IEEE, pp. 1, 06/2015.
"Physical Attacks and Beyond",
Proceedings of the Selected Areas in Cryptography: 23nd International Conference (SAC) 2016, 2016.
"Midori: (A) Block Cipher for Low Energy (Extended Version)",
(IACR) Cryptology ePrint Archive, vol. 2015, 12/2015.