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Education and Innovation in Embedded Systems Design

USI Università della Svizzera italiana, USI Faculty of Informatics, Advanced Learning and Research Institute USI Università della Svizzera italiana USI Faculty of Informatics USI Advanced Learning and Research Institute
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Pilato, C., and L. P. Carloni, "DarkMem: Fine-Grained Power Management of Local Memories for Accelerators in Embedded Systems", Proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC), 2018.
Fiorin, L., G. Palermo, S. Luković, and C. Silvano, "A Data protection Unit for NoC-based Architecture", CODES+ISSS 2007, in proceedings of the Fifth IEEE/ACM/FIP International Conference of Hardware/Software Codesign and System Synthesis (CODES+ISSS 2007), Salzburg, Austria, September 30, 2007.
Basu, A S., M. Lajolo, and M. Prevostini, "Design and Synthesis of Reusable Platforms with Programmable Interconnects", UML-SoC 2005, Anaheim, California, pp. 43-48, June 12, 2005.
Ferrari, F., and E. Amador, "Design exploration for an Ogg/Vorbis decoder for VLIW architectures", Workshop on Application Specific Processors (WASP '07), Salzburg, Austria, October, 2007.
Regazzoni, F., A. Cevrero, F-X. Standaert, S. Badel, T. Kluter, P. Brisk, Y. Leblebici, and P. Ienne, "A Design Flow and Evaluation Framework for DPA-resistant Instruction Set Extensions", Cryptographic Hardware and Embedded Systems (CHES), vol. 5747, Lausanne, Switzerland, Springer Berlin Heidelberg, pp. 205-219, September, 2009.
Faruque, M. Abdullah A., F. Regazzoni, and M. Pajic, "Design methodologies for securing cyber-physical systems", 2015 International Conference on Hardware/Software Codesign and System Synthesis CODES+ISSS, Amsterdam, Netherlands, IEEE, pp. 30-36, 10/2015.
Dadda, L., M. Macchetti, and J. Owen, "The Design of a High Speed ASIC Unit for the Hash Function SHA-256 (384,512)", DATE '04: Proceedings of the conference on Design, automation and test in Europe, Washington, DC, USA, IEEE Computer Society, pp. 30070, 2004.
Fiorin, L., L. Micconi, and M. Sami, "Design of Fault Tolerant Network Interfaces for NoCs", Proceedings of 14th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD'11), Oulu, Finland, September, 2011.
Mariani, G., P. Avasare, C. Ykman-Couvreur, G. Vanmeerbeeck, G. Palermo, C. Silvano, and V. Zaccaria, "Design Space Exploration for Run-Time Management of a Reconfigurable System for Video Streaming", Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach, 1: Springer, pp. 189-204, 2011.
Mariani, G., G. Palermo, C. Silvano, and V. Zaccaria, "A Design Space Exploration Methodology Supporting Run-Time Resource Management for Multi-Processors System on-Chip", Proceedings IEEE SASP'09 - Symposium on Application Specific Processors, San Francisco, CA, USA, July, 2009.
Mariani, G., P. Avasare, C. Ykman-Couvreur, G. Vanmeerbeeck, G. Palermo, C. Silvano, and V. Zaccaria, "Design Space Exploration of a Reconfigurable System for Supporting Video Streaming Run-time Management", Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach, New York, USA, Springer, 2011.
Kavka, C., A. Turco, G. Palermo, C. Silvano, V. Zaccaria, G. Mariani, S. Bocchio, and F. Dongrui, "Design Space Exploration of Parallel Architectures", Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach, New York, USA, Springer, 2011.
Mady, A E-D., A. Tonini, and D. Finardi, "Design Space Exploration of PISA Architecture For ONU Auto-discovery Process", proceedings of 6th International Conference of Electrical Engineering (ICEENG), Cairo, Egypt, May 27-29, 2009.
Avasare, P., C. Ykman-Couvreur, G. Vanmeerbeeck, G. Mariani, G. Palermo, C. Silvano, and V. Zaccaria, "Design Space Exploration Supporting Run-time Resource Management", Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach, New York, USA, Springer, 2011.
Valencia, F., A. Khalid, E. O'Sullivan, and F. Regazzoni, "The design space of the number theoretic transform: A survey", 2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, {SAMOS} 2017, Pythagorion, Greece, July 17-20, 2017 (Invited), 2017.
Mariani, G., G. Palermo, V. Zaccaria, and C. Silvano, "Design-space Exploration and Runtime Resource Management for Multicores", ACM Transactions on Embedded Computing Systems (TECS) - Special issue on application-specific processors, vol. 13, issue 2, pp. 20:1–20:27, 09/2013.
Alippi, C., V. D'Alto, M. Falchetto, D. Pau, and M. Roveri, "Detecting changes at the sensor level in cyber-physical systems: Methodology and technological implementation", 2017 International Joint Conference on Neural Networks (IJCNN), May, 2017.
Zambon, D., L. Livi, and C. Alippi, "Detecting changes in sequences of attributed graphs", 2017 IEEE Symposium Series on Computational Intelligence (SSCI), Nov, 2017.
Livi, L., F. Maria Bianchi, and C. Alippi, "Determination of the Edge of Criticality in Echo State Networks Through Fisher Information Maximization", IEEE Transactions on Neural Networks and Learning Systems, vol. 29, pp. 706-717, March, 2018.
Fornaciari, W., F. Salice, U. Bondi, and E. Magini, "Development cost and size estimation starting from high-level specifications", CODES '01: Proceedings of the ninth international symposium on Hardware/software codesign, Copenhagen, Denmark, ACM Press, New York, USA, pp. 86-91, 2001.

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