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Education and Innovation in Embedded Systems Design

USI Università della Svizzera italiana, USI Faculty of Informatics, Advanced Learning and Research Institute USI Università della Svizzera italiana USI Faculty of Informatics USI Advanced Learning and Research Institute
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Author [ Title(Desc)] Type Year
Filters: Author is François-Xavier Standaert  [Clear All Filters]
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A
Bayrak, A. Galip, F. Regazzoni, D. Novo Bruna, P. Brisk, F-X. Standaert, and P. Ienne, "Automatic Application of Power Analysis Countermeasures", IEEE Transactions on Computers, vol. PP, issue 99, 12/2013.
Bayrak, A. Galip, F. Regazzoni, D. Novo, P. Brisk, F-X. Standaert, and P. Ienne, "Automatic Application of Power Analysis Countermeasures", IEEE Transactions on Computers , vol. 64, issue 2, pp. 329-341, 02/2015.
C
Barenghi, A., C. Hocquet, D. Bol, F-X. Standaert, F. Regazzoni, and I. Koren, "A Combined Design-Time/Test-Time Study of the Vulnerability of Sub-Threshold Devices to Low Voltage Fault Attacks", IEEE Transactions on Emerging Topics in Computing, vol. PP, issue 99, 04/2014.
Eisenbarth, T., Z. Gong, T. Gneysu, S. Heyse, S. Indesteege, S. Kerckhof, F. Koeune, T. Nad, T. Plos, F. Regazzoni, et al., "Compact Implementation and Performance Evaluation of Block Ciphers in ATtiny Devices", Progress in Cryptology - Africacrypt, Ifrance, Morocco, July, 2012.
Balasch, J., B. Ege, T. Eisenbarth, B. Grard, Z. Gong, T. Gneysu, S. Heyse, S. Kerckhof, F. Koeune, T. Plos, et al., "Compact Implementation and Performance Evaluation of Hash Functions in ATtiny Devices", 11th Smart Card Research and Advanced Application Conference (CARDIS), Graz, Austria, November, 2012.
D
Regazzoni, F., A. Cevrero, F-X. Standaert, S. Badel, T. Kluter, P. Brisk, Y. Leblebici, and P. Ienne, "A Design Flow and Evaluation Framework for DPA-resistant Instruction Set Extensions", Cryptographic Hardware and Embedded Systems (CHES), vol. 5747, Lausanne, Switzerland, Springer Berlin Heidelberg, pp. 205-219, September, 2009.
E
Barenghi, A., C. Hocquet, D. Bol, F-X. Standaert, F. Regazzoni, and I. Koren, "Exploring the Feasibility of Low Cost Fault Injection Attacks on Sub-Threshold Devices through an Example of a 65nm AES Implementation", 7th Workshop on RFID Security and Privacy (RFIDSec), Amherst, Massachussets, USA, June, 2011.
F
Bayrak, A. Galip, F. Regazzoni, P. Brisk, F-X. Standaert, and P. Ienne, "A First Step Towards Automatic Application of Power Analysis Countermeasures", 48th Design Automation Conference (DAC), San Diego, Califorina, June, 2011.
Regazzoni, F., W. Yi, and F-X. Standaert, "FPGA Implementations of the AES Masked Against Power Analysis Attacks", 2nd International Workshop on Constructive Side-Channel Analysis and Secure Design (COSADE), Darmstadt, Germany, February, 2011.
Medwed, M., C. Petit, F. Regazzoni, M. Renauld, and F-X. Standaert, "Fresh Re-Keying II: Securing Multiple Parties against Side-Channel and Fault Attacks", 10th Smart Card Research and Advanced Application Conference (CARDIS), Leuven, Belgium, September, 2011.
Medwed, M., F-X. Standaert, J. Großschädl, and F. Regazzoni, "Fresh Re-Keying: Security against Side-Channel and Fault Attacks for Low-Cost Devices", Proceedings of Progress in Cryptology - Africacrypt, Stellenbosch, South Africa, May, 2010.
H
Hocquet, C., D. Kamel, F. Regazzoni, J-D. Legat, D. Flandre, D. Bol, and F-X. Standaert, "Harvesting the potential of nano-CMOS for lightweight cryptography: An ultra-low-voltage 65 nm AES coprocessor for passive RFID tags", Springer Journal of Cryptographic Engineering, vol. 1, issue 1, 2011.
L
Kerckhof, S., F. Durvaux, N. Veyrat-Charvillon, F. Regazzoni, G. Meurice de Dormale, and F-X. Standaert, "Low Cost FPGA Implementations of the SHA-3 Finalists", 10th Smart Card Research and Advanced Application Conference (CARDIS), Leuven, Belgium, September, 2011.
S
Durvaux, F., S. Kerckhof, F. Regazzoni, and F-X. Standaert, "Security IPs and IP Security with FPGAs", Secure Smart Embedded Devices Platform and Applications, 2014.