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Filters: Author is Thomas Eisenbarth [Clear All Filters]
"Power Attacks Resistance of Cryptographic S-boxes with added Error Detection Circuits", proceedings of: '22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'07), Rome, Italy, September 26-28, 2007.
"Simulation-based Methodology for Evaluating DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies", International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS IC 07), Samos, Greece, July 16-19, 2007.
"Can knowledge regarding the presence of countermeasures against fault attacks simplify power attacks on cryptographic devices?", Proceedings of 23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS 08), October 1-3, 2008.
"Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology", Springer Transactions on Computational Science, vol. 5430, pp. 230–243, February, 2009.
"Compact Implementation and Performance Evaluation of Block Ciphers in ATtiny Devices", Progress in Cryptology - Africacrypt, Ifrance, Morocco, July, 2012.
"Compact Implementation and Performance Evaluation of Hash Functions in ATtiny Devices", 11th Smart Card Research and Advanced Application Conference (CARDIS), Graz, Austria, November, 2012.