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"A 640 Mbit/s 32-bit Pipelined Implementation of the AES Algorithm", SECRYPT, Porto, Portugal, July 26, 2008.
"About the Performances of the Advanced Encryption Standard in Embedded Systems with Cache Memory", ISCAS 2003, Bangkok, pp. 145-148, May 25-28, 2003.
"Can knowledge regarding the presence of countermeasures against fault attacks simplify power attacks on cryptographic devices?", Proceedings of 23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS 08), October 1-3, 2008.
"Efficient AES implementations for ARM based platforms", SAC '04: Proceedings of the 2004 ACM symposium on Applied computing, Nicosia, Cyprus, ACM Press, New York, USA, pp. 841–845, 2004.
"Efficient C implementation of the ECC and AES cryptographic systems", Technology Leadership Day - organized by the MicroSwiss Network, Fribourg, October 10, 2001.
"Efficient Software Implementation of AES on 32-Bit Platforms", CHES '02: Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems, London, UK, Springer-Verlag, pp. 159–171, 2003.
"Interaction between Fault Attack Countermeasures and the Resistance against Power Analysis Attacks", Fault Analysis in Cryptography: Springer Berlin Heidelberg, pp. 257-272, 2012.
"Low Cost Software Countermeasures Against Fault Attacks: Implementation and Performances Trade Offs", 5th Workshop on Embedded Systems Security (WESS), Scottsdale, Arizona, USA, October, 2010.
Method and circuit for data encryption/decryption, , no. US 09/974,705, April, 2003.
"Power Attacks Resistance of Cryptographic S-boxes with added Error Detection Circuits", proceedings of: '22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'07), Rome, Italy, September 26-28, 2007.
"Speeding Up AES By Extending a 32 bit Processor Instruction Set", ASAP '06: Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06), Washington, DC, USA, IEEE Computer Society, pp. 275-282, 2006.