]
"Area and Power Efficient Synthesis of DPA-Resistant Cryptographic SBoxes",
International Conference on VLSI Design & Embedded Systems, Bangalore, India, January 6-10, 2007.
"ARTE: an Application-specific Run-Time Management Framework for Multi-cores based on Queuing Models",
Parallel Computing, 2013.
"ARTE: an Application-specific Run-Time Management Framework for Multi-core Systems",
Proceedings IEEE SASP'11 - Symposium on Application Specific Processors, San Diego, CA, USA, June, 2011.
"Artificial Intelligence in the Age of Neural Networks and Brain Computing",
Academic Press , 1, pp. 420, 2018.
"An ASIC design for a high speed implementation of the hash function SHA-256 (384, 512)",
GLSVLSI '04: Proceedings of the 14th ACM Great Lakes symposium on VLSI, Boston, MA, USA, ACM Press, New York, USA, pp. 421–425, 2004.
"ASIC Hardware Implementation of the IDEA NXT Encryption Algorithm",
IEEE International Symposium on Circuits and Systems, Kos, Greece, May 21-24, 2006.
"Atomic-AES: A Compact Implementation of the AES Encryption/Decryption Core",
Proceedings of 17th International Conference on Cryptology in India (INDOCRYPT) 2016, 2016.
"An Automated Design Flow for NoC-based MPSoCs on FPGA",
RSP 2008, The 19th IEEE/IFIP International Symposium on Rapid System Prototyping, Monterey, USA/CA, June 2-5, 2008.
"Automatic Application of Power Analysis Countermeasures",
IEEE Transactions on Computers, vol. PP, issue 99, 12/2013.
"Automatic Application of Power Analysis Countermeasures",
IEEE Transactions on Computers , vol. 64, issue 2, pp. 329-341, 02/2015.
"Automatic Synthesis of the Hardware/Software Interface in Multiprocessor Architectures",
FDL'05 - Forum on Specification and Design Languages, Lausanne, Switzerland, September 27-30, 2005.
"Beamforming for interference mitigation and its implementation on an SDR baseband processor",
SiPS'11: Proceedings of the IEEE Workshop on Signal Processing Systems, Beirut, Lebanon, pp. 1–6, October 4-7, 2011.
"Black-Hat High-Level Synthesis: Myth or Reality?",
IEEE Transactions on Very Large Scale Integration Systems, In Press.
"Breaking ECC2K-130",
IACR Cryptology ePrint Archive, vol. 2009, pp. 541, 11/2009.
"Bridging the Gap between Software and Hardware Designers Using High-Level Synthesis",
Advances in Parallel Computing, 2018.
"Bridging the Gap between SysML and Design Space Exploration",
FDL'06 Proceedings, Darmstadt, Germany, pp. 389-394, September 19-22, 2006.
"Calibration and in-Field Validation Tests of a Web-based Adaptive Management System for Monitoring - Scaphoideus titanus",
Future Integrated Pest Management in Europe, 2013.
"Can knowledge regarding the presence of countermeasures against fault attacks simplify power attacks on cryptographic devices?",
Proceedings of 23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS 08), October 1-3, 2008.
"Can we Achieve both Privacy Protection and Efficient Malware Detection on Smartphones?",
1st Interdisciplinary Cyber Research Workshop 2015, Tallin, Estona, Tallinn University of Technology, 07/2015.
"The Case for Polymorphic Registers in Dataflow Computing",
International Journal of Parallel Programming, vol. 54, issue 5, pp. 54-62, 10/2018.