@conference {18546,
	title = {Moving Convolutional Neural Networks to Embedded Systems: The Alexnet and VGG-16 Case},
	booktitle = {Proceedings of the 17th ACM/IEEE International Conference on Information Processing in Sensor Networks},
	year = {2018},
	publisher = {IEEE Press},
	organization = {IEEE Press},
	address = {Piscataway, NJ, USA},
	keywords = {approximate computing, convolutional neural networks, deep learning, embedded systems},
	isbn = {978-1-5386-5298-5},
	doi = {10.1109/IPSN.2018.00049},
	url = {https://doi.org/10.1109/IPSN.2018.00049},
	author = {Alippi, Cesare and Disabato, Simone and Roveri, Manuel}
}
@inbook {18466,
	title = {Malware Threats and Solutions for Trustworthy Mobile Systems Design},
	booktitle = {Hardware Security and Trust: Design and Deployment of Integrated Circuits in a Threatened Environment},
	year = {2017},
	pages = {149-167},
	publisher = {Springer},
	organization = {Springer},
	edition = {First edition; 2016},
	keywords = {malware, mobile systems, security metric, trusting},
	doi = {https://doi.org/10.1007/978-3-319-44318-8_8},
	author = {Milosevic, Jelena and Regazzoni, Francesco and Malek, Miroslaw}
}
@article {18531,
	title = {Model-Free Fault Detection and Isolation in Large-Scale Cyber-Physical Systems},
	journal = {IEEE Transactions on Emerging Topics in Computational Intelligence},
	volume = {1},
	year = {2017},
	month = {Feb},
	pages = {61-71},
	keywords = {Change detection algorithms, clustering methods, Computational modeling, cyber-physical systems, Fault detection, Hidden Markov models, monitoring, Sensor phenomena and characterization, Sensor systems},
	doi = {10.1109/TETCI.2016.2641452},
	author = {Alippi, Cesare and Ntalampiras, Stavros and Roveri, Manuel}
}
@article {18532,
	title = {Multiplex visibility graphs to investigate recurrent neural network dynamics},
	journal = {Nature-Scientific reports},
	volume = {7},
	year = {2017},
	month = {03/2017},
	pages = {44037-44049},
	chapter = {44037},
	doi = {doi:10.1038/srep44037},
	author = {Bianchi, Filippo Maria and Livi, Lorenzo and Alippi, Cesare and Jenssen, Robert}
}
@conference {18461,
	title = {MalAware: Effective and Efficient Run-time Mobile Malware Detector},
	booktitle = {The 14th  IEEE International Conference on Dependable,  Autonomic and Secure Computing (DASC 2016)},
	year = {2016},
	month = {08/2016},
	publisher = {IEEE Computer Society Press},
	organization = {IEEE Computer Society Press},
	address = {Auckland, New Zealand},
	author = {Milosevic, Jelena and Ferrante, Alberto and Malek, Miroslaw}
}
@conference {18503,
	title = {A Methodology for Proactive Maintenance of Uninterruptible Power Supplies},
	booktitle = {Latin-American Symposium on Dependable Computing  (LADC2016) - Workshop on Dependability in Evolving Systems (WDES)},
	year = {2016},
	month = {10/2016},
	address = {Cali, Colombia},
	abstract = {We propose a methodology for proactive maintenance of Uninterruptible Power Supply (UPS) devices based on online health-status monitoring and application of data analytics for prediction of UPS components{\textquoteright} failures. The goals of the work are (i) improvement of reliability of UPS devices by ensuring prompt action prior to a failure of a component, and (ii) provision of more cost-effective maintenance by servicing the device only when required instead of periodically. Improving reliability of UPS{\textquoteright}es also enhances dependability of critical infrastructures that require high quality power supply.},
	author = {Lukovi{\'c}, Slobodan and Kaitovi{\'c}, Igor and Lecuona, Gerardo and Malek, Miroslaw}
}
@article {18543,
	title = {Model Complexity, Regularization, and Sparsity [Guest Editorial]},
	year = {2016},
	keywords = {Adaptation models, Computational complexity, machine learning, Sparse matrices, Special issues and sections},
	doi = {10.1109/MCI.2016.2602071},
	author = {Alippi, Cesare and Boracchi, Giacomo and Wohlberg, Brendt}
}
@conference {18483,
	title = {Midori: A Block Cipher for Low Energy},
	booktitle = {21st International Conference on the Theory and Application of Cryptology and Information Security ASIACRYPT 2015},
	series = {Lecture Notes in Computer Science},
	volume = {9453},
	year = {2015},
	month = {11/2015},
	pages = {411-436},
	publisher = {Springer Berlin Heidelberg},
	organization = {Springer Berlin Heidelberg},
	address = {Auckland, New Zealand},
	abstract = {In the past few years, lightweight cryptography has become a popular research discipline with a number of ciphers and hash functions proposed. The designers{\textquoteright} focus has been predominantly to minimize the hardware area, while other goals such as low latency have been addressed rather recently only. However, the optimization goal of low energy for block cipher design has not been explicitly addressed so far. At the same time, it is a crucial measure of goodness for an algorithm. Indeed, a cipher optimized with respect to energy has wide applications, especially in constrained environments running on a tight power/energy budget such as medical implants.

This paper presents the block cipher Midori (The name of the cipher is the Japanese translation for the word Green.) that is optimized with respect to the energy consumed by the circuit per bt in encryption or decryption operation. We deliberate on the design choices that lead to low energy consumption in an electrical circuit, and try to optimize each component of the circuit as well as its entire architecture for energy. An added motivation is to make both encryption and decryption functionalities available by small tweak in the circuit that would not incur significant area or energy overheads. We propose two energy-efficient block ciphers Midori128 and Midori64 with block sizes equal to 128 and 64 bits respectively. These ciphers have the added property that a circuit that provides both the functionalities of encryption and decryption can be designed with very little overhead in terms of area and energy. We compare our results with other ciphers with similar characteristics: it was found that the energy consumptions of Midori64  and Midori128  are by far better when compared ciphers like PRINCE and NOEKEON.
},
	keywords = {lightweight block cipher, low energy circuits},
	isbn = {978-3-662-48799-0},
	issn = {0302-9743},
	doi = {10.1007/978-3-662-48800-3_17},
	url = {http://dx.doi.org/10.1007/978-3-662-48800-3_17},
	author = {Banik, Subhadeep and Bogdanov, Andrey and Isobe, Takanori and Shibutani, Kyoji and Hiwatari, Harunaga and Akishita, Toru and Regazzoni, Francesco}
}
@article {18472,
	title = {Midori: (A) Block Cipher for Low Energy (Extended Version)},
	journal = {(IACR) Cryptology ePrint Archive},
	volume = {2015},
	year = {2015},
	month = {12/2015},
	chapter = {1142},
	abstract = {In the past few years, lightweight cryptography has become a popular research discipline with a number of ciphers and hash functions proposed. The designers{\textquoteright} focus has been predominantly to minimize the hardware area, while other goals such as low latency have been addressed rather recently only. However, the optimization goal of low energy for block cipher design has not been explicitly addressed so far. At the same time, it is a crucial measure of goodness for an algorithm. Indeed, a cipher optimized with respect to energy has wide applications, especially in constrained environments running on a tight power/energy budget such as medical implants. 

This paper presents the block cipher Midori that is optimized with respect to the energy consumed by the circuit per bit in encryption or decryption operation. We deliberate on the design choices that lead to low energy consumption in an electrical circuit, and try to optimize each component of the circuit as well as its entire architecture for energy. An added motivation is to make both encryption and decryption functionalities available by small tweak in the circuit that would not incur significant area or energy overheads. 

We propose two energy-efficient block ciphers Midori128 and Midori64 with block sizes equal to 128 and 64 bits respectively. These ciphers have the added property that a circuit that provides both the functionalities of encryption and decryption can be designed with very little overhead in terms of area and energy. We compare our results with other ciphers with similar characteristics: it was found that the energy consumptions of Midori64 and Midori128 are by far better when compared ciphers like PRINCE and NOEKEON. 
},
	keywords = {AES, lightweight block cipher, low energy circuits, secret-key cryptography},
	url = {http://eprint.iacr.org/2015/1142},
	author = {Regazzoni, Francesco and Banik, Subhadeep and Bogdanov, Andrey and Isobe, Takanori and Shibutani, Kyoji and Hiwatari, Harunaga and Akishita, Toru}
}
@conference {18088,
	title = {Malicious Wave: a Survey on Actively Tampering Using Electromagnetic Glitch},
	booktitle = {International Symposium on Electromagnetic Compatibility 2014},
	year = {2014},
	month = {08/2014},
	author = {Bhasin, Shivam and Maistri, Paolo and Regazzoni, Francesco}
}
@conference {18233,
	title = {Modeling Requirements For Security-enhanced Design of Embedded Systems},
	booktitle = {ICETE SECRYPT},
	year = {2014},
	month = {08/2014},
	publisher = {ICETE},
	organization = {ICETE},
	address = {Vienna, Austria},
	author = {Ferrante, Alberto and Kaitovi{\'c}, Igor and Milosevic, Jelena}
}
@inbook {18024,
	title = {Modeling Responsiveness of Decentralized Service Discovery in Wireless Mesh Networks},
	booktitle = {MMB \& DFT},
	series = {Lecture Notes in Computer Science},
	volume = {8376},
	year = {2014},
	pages = {88-102},
	publisher = {Springer International Publishing Switzerland},
	organization = {Springer International Publishing Switzerland},
	abstract = {In modern service networks, discovery plays a crucial role as a layer where providing instances of a given service can be published and enumerated. Since successful discovery is mandatory for service usage, comprehensive service dependability assessment needs to incorporate the dependability of the discovery layer. This work focuses on the responsiveness of the discovery layer, the probability to operate successfully within a deadline, even in the presence of faults. It proposes a hierarchy of stochastic models for decentralized discovery and uses it to describe the discovery of a single service using three well-known discovery protocols: domain name system based service discovery (DNS-SD), simple service discovery protocol (SSDP) and service location protocol (SLP). Further, a methodology to use the model hierarchy in wireless mesh networks is introduced. Given a pair service requester and provider, a discovery protocol and a deadline, it estimates packet loss probabilities and transmission time distributions for each link on the communication paths between the pair, generates specific model instances and calculates the expected responsiveness. Finally, the paper introduces a new metric, the expected responsiveness distance d_er to estimate the maximum distance from a provider where requesters are still able to discover it with a required responsiveness. The models and their methodology are demonstrated using monitoring data from the distributed embedded systems (DES) testbed at Freie Universit{\"a}t Berlin. It is shown how the responsiveness and d_er of the protocols change depending on the position of requester and provider and the overall link quality in the network.},
	keywords = {fault tolerance, Markov Models, Real time systems, Responsiveness, Service Discovery, Wireless mesh networks},
	isbn = {978-3-319-05358-5},
	issn = {0302-9743},
	doi = {10.1007/978-3-319-05359-2_7},
	url = {http://andreas-dittrich.eu/2013/12/modeling-responsiveness-of-decentralized-service-discovery-in-wireless-mesh-networks},
	author = {Dittrich, Andreas and Lichtblau, Bj{\"o}rn and Rezende, Rafael and Malek, Miroslaw},
	editor = {Fischbach, K. and Krieger, U. R.}
}
@conference {17729,
	title = {A Model for the Evaluation of User-Perceived Service Properties},
	booktitle = {International Symposium on Parallel Distributed Processing, Workshops and Phd Forum (IPDPSW)},
	year = {2013},
	month = {May},
	publisher = {IEEE Computer Society},
	organization = {IEEE Computer Society},
	address = {Boston, Massachusetts, USA},
	abstract = {An ever-increasing number of both functional and non-functional requirements has resulted in growing system complexity which demands new solutions in system modeling and evaluation. As a remedy, service-oriented architecture (SOA) offers services as basic building elements of system design. Service dependability is highly dependent on the properties of the underlying information and communications technology (ICT) infrastructure. This is especially true for the user-perceived dependability of a specific pair service client and provider as every pair may utilize different ICT components. We provide a model for the description of ICT components and their non-functional properties based on the Unified Modeling Language (UML). Given a service description, a network topology model and a pair service client and provider, we propose a methodology to automatically identify relevant ICT components and generate a user-perceived service infrastructure model (UPSIM). We demonstrate the feasibility of the methodology by applying it to parts of the service network infrastructure at Universit{\`a} della Svizzera italiana, Switzerland. We then show how this methodology can be used to facilitate user-perceived service dependability analysis.},
	keywords = {availability, design engineering, metamodeling, modeling, object oriented modeling, quality of service (QoS), service dependability, service network management, service networks},
	isbn = {978-0-7695-4979-8},
	doi = {10.1109/IPDPSW.2013.163},
	url = {http://andreas-dittrich.eu/2013/03/a-model-for-the-evaluation-of-user-perceived-service-properties},
	author = {Dittrich, Andreas and Kaitovi{\'c}, Igor and Murillo, Cristina and Rezende, Rafael}
}
@inbook {17731,
	title = {Model-Driven Evaluation of User-Perceived Service Availability},
	booktitle = {Dependable Computing},
	series = {Lecture Notes in Computer Science},
	volume = {7869},
	year = {2013},
	month = {May},
	pages = {39-53},
	publisher = {Springer Berlin Heidelberg},
	organization = {Springer Berlin Heidelberg},
	abstract = {Service-oriented architecture (SOA), which proposes services as basic building elements of system design, has emerged as an approach to master growing system complexity. However, it remains difficult to evaluate dependability of such distributed and heterogeneous functionality as it depends highly on the properties of the enabling information and communications technology (ICT) infrastructure. Moreover, every specific pair service client and provider can utilize different ICT components, constituting for the user-perceived view of a service. We provide a model-driven methodology to automatically create reliability block diagrams of such views. Given a service description, a network topology model and a pair service client and provider, it identifies relevant ICT components and generates a user-perceived service availability model (UPSAM). We then use this UPSAM to calculate the steady-state availability of different views on an examplary mail service deployed in the network infrastructure of University of Lugano.},
	keywords = {availability, design engineering, modeling, object oriented modeling, quality of service (QoS), service dependability, service network management, service networks},
	issn = {978-3-642-38788-3},
	doi = {10.1007/978-3-642-38789-0_4},
	url = {http://andreas-dittrich.eu/2013/04/model-driven-evaluation-of-user-perceived-service-availability},
	author = {Dittrich, Andreas and Rezende, Rafael},
	editor = {Vieira, Marco and Cunha, Jo{\~a}o Carlos}
}
@conference {17732,
	title = {Model-driven approach to design ICT infrastructure for precision farming},
	booktitle = {17th IEEE Conference on Emerging Technologies and Factory Automation (ETFA)},
	year = {2012},
	month = {09/2012},
	publisher = {IEEE Industrial Electronics Society},
	organization = {IEEE Industrial Electronics Society},
	address = {Krak{\'o}w, Poland},
	abstract = {Design of complex systems involving a number of experts from various fields necessarily includes modeling at different levels of abstraction. Modeling is particularly important in the initial phase of a joint project when all system requirements and constraints have to be clearly defined and understood by all the partners. Once an unambiguous structural model has been achieved and components interfaces fixed, design of components can be done independently. For the initial phase, a very simplified modeling methodology based on UML that can be easily understood and applied has been proposed. The application of the methodology has been presented through the design of full structural model of the infrastructure for precision farming. Modeled infrastructure is an open ICT hardware-software solution based on ISOBUS specification, that enables partial automation of tractors increasing safety and production efficiency. Model achieved through several steps presents a mutual understanding platform between the partners. Most importantly, a precise model has been achieved without the necessity of in deep study of UML by all the partners.},
	keywords = {agriculture, ICT infrastructure Design, ISOBUS, model-driven approach, precision farming, Safety, Unified Modeling Language},
	isbn = {978-1-4673-4736-5},
	doi = {10.1109/ETFA.2012.6489709},
	author = {Kaitovi{\'c}, Igor and Rezende, Rafael and Murillo, Cristina and Fantuzzi, Cesare}
}
@article {146.DeDiFi11.IJRC,
	title = {A Middleware Approach to Achieving Fault-tolerance of Kahn Process Networks on Networks-on-Chips},
	journal = {International Journal of Reconfigurable Computing},
	volume = {2011},
	number = {Article ID 295385},
	year = {2011},
	note = {Selected Papers from the International Workshop on Reconfigurable Communication-centric Systems on Chips (ReCoSoC{\textquoteright} 2010)},
	month = {February},
	pages = {14 pages},
	publisher = {Hindawi},
	abstract = {Kahn process networks (KPN) is a distributed model of computation used for describing systems where streams of data are transformed by processes executing in sequence or parallel. Autonomous processes communicate through unbounded FIFO channels in absence of a global scheduler. In this work, we propose a task-aware middleware concept that allows adaptivity in KPN implemented over a Network-on-Chip (NoC). We also list our ideas on the development of a simulation platform as an initial step towards creating fault-tolerance strategies for KPNs applications running on NoCs. In doing that, we extend our SACRE (Self-adaptive Component Run-time Environment) framework by integrating it with an open source NoC simulator, Noxim. We evaluate the overhead that the middleware brings to the the total execution time and to the total amount of data transferred in the NoC. With this work, we also provide a methodology that can help in identifying the requirements and implementing fault tolerance and adaptivity support on real platforms.},
	keywords = {fault tolerance, kahn process networks (KPN), middleware, network-on-chip (NoC), self-adaptivity},
	issn = {1687-7195},
	doi = {doi:10.1155/2011/295385},
	author = {Derin, Onur and Diken, Erkan and Fiorin, Leandro}
}
@conference {153.CaDeSt11.DASIP,
	title = {Middleware Approaches for Adaptivity of Kahn Process Networks on Networks-on-Chip},
	booktitle = {DASIP{\textquoteright}11: Proceedings of the Conference on Design and Architectures for Signal and Image Processing},
	year = {2011},
	month = {November 2-4},
	pages = {1{\textendash}8},
	address = {Tampere, Finland},
	abstract = {We investigate and propose a number of different middleware approaches, namely virtual connector, virtual connector with variable rate, and request-based, which implement the semantics of Kahn Process Networks on Network-on-Chip architectures. All of the presented solutions allow for run-time system adaptivity. We implement the approaches on a Network-on-Chip multiprocessor platform prototyped on an FPGA. Their comparison in terms of the introduced overhead is presented on two case studies with different communication characteristics. We found out that the virtual connector mechanism outperforms other approaches in the communication-intensive application. In the other case study, which has a higher computation/communication ratio, the middleware approaches show similar performance.},
	keywords = {kahn process networks (KPN), middleware, network-on-chip (NoC), self-adaptivity},
	doi = {http://dx.doi.org/10.1109/DASIP.2011.6136862},
	author = {Cannella, Emanuele and Derin, Onur and Stefanov, Todor}
}
@inbook {17734,
	title = {The MULTICUBE Design Flow},
	booktitle = {Multi-objective Design Space Exploration of Multiprocessor SoC Architectures},
	year = {2011},
	pages = {3-17},
	publisher = {Springer New York},
	organization = {Springer New York},
	isbn = {978-1-4419-8836-2},
	doi = {10.1007/978-1-4419-8837-9_1},
	url = {http://dx.doi.org/10.1007/978-1-4419-8837-9_1},
	author = {Silvano, Cristina and Fornaciari, William and Palermo, Gianluca and Zaccaria, Vittorio and Castro, Fabrizio and Martinez, Marcos and Bocchio, Sara and Zafalon, Roberto and Avasare, Prabhat and Vanmeerbeeck, Geert and Ykman-Couvreur, Chantal and Wouters, Maryse and Kavka, Carlos and Onesti, Luka and Turco, Alessandro and Bondi, Umberto and Mariani, Giovanni and Posadas, Hector and Villar, Eugenio and Wu, Chris and Dongrui, Fan and Hao, Zhang},
	editor = {Silvano, Cristina and Fornaciari, William and Villar, Eugenio}
}
@inbook {139.Sietal2.2011,
	title = {MULTICUBE: Multi-Objective Design Space Exploration of Multi-Core Architectures},
	booktitle = {VLSI 2010 Annual Symposium},
	volume = {105},
	year = {2011},
	pages = {47-63},
	publisher = {Springer},
	organization = {Springer},
	address = {Netherlands},
	abstract = {Given the increasing complexity of Chip Multi-Processors (CMPs), a wide range of architecture parameters must be explored at design time to find the best trade-off in terms of multiple competing objectives (such as energy, delay, bandwidth, area, etc.) The design space of the target architectures is huge because it should consider all possible combinations of each hardware parameter (e.g., number of processors, processor issue width, L1 and L2 cache sizes, etc.). In this complex scenario, intuition and past experience of design architects is no more a sufficient condition to converge to an optimal design of the system. Indeed, Automatic Design Space Exploration (DSE) is needed to systematically support the analysis and quantitative comparison of a large amount of design alternatives in terms of multiple competing objectives (by means of Pareto analysis). The main goal of the MULTICUBE project consists of the definition of an automatic Design Space Exploration framework to support the design of next generation many-core architectures.},
	isbn = {978-94-007-1487-8},
	url = {http://dx.doi.org/10.1007/978-94-007-1488-5_4},
	author = {Silvano, Cristina and Fornaciari, William and Palermo, Gianluca and Zaccaria, Vittorio and Castro, Fabrizio and Martinez, Marcos and Bocchio, Sara and Zafalon, Roberto and Avasare, Prabhat and Vanmeerbeeck, Geert and Ykman-Couvreur, Chantal and Wouters, Maryse and Kavka, Carlos and Onesti, Luka and Turco, Alessandro and Bondi, Umberto and Mariani, Giovanni and Posadas, Hector and Villar, Eugenio and Wu, Chris and Dongrui, Fan and Hao, Zhang and Shibin, Tang}
}
@inbook {17693,
	title = {MDE Support for HW/SW Codesign: a UML-based Design Flow},
	booktitle = {Advances in Design Methods from Modeling Languages for Embedded Systems and SoC{\textquoteright}s},
	year = {2010},
	pages = {19-37},
	publisher = {Springer},
	organization = {Springer},
	address = {Dordrecht, The Netherlands},
	author = {Murillo, Luis Gabriel and Mura, Marcello and Prevostini, Mauro}
}
@conference {136.FiPaSi10,
	title = {A Monitoring System for NoCs},
	booktitle = {Proceedings of the Third International Workshop on Network on Chip Architectures (NoCArc{\textquoteright}2010)},
	year = {2010},
	month = {December},
	address = {Atlanta, Georgia, USA},
	abstract = {In this paper, we propose and discuss a monitoring architecture for Networks-on-Chip (NoCs) that provides system information useful for helping designers in efficiently exploiting resources available in new complex Multiprocessor System-on-Chip (MPSoC) platforms, and in understanding their behavior. We focus on the analysis of the architectural details and design challenges of such systems, by describing power- ful tools for detecting information that can be used both at run-time for detecting dynamic changes in system behavior and at post-execution time for debugging and profiling of applications. We detail the design of the probes monitoring the events and discuss an architecture for collection, storage, and analysis of information generated by them. We evaluate cost of the implementation of the system in terms of area and traffic overhead, and we present results obtained when monitoring a use-case multimedia application.},
	keywords = {hardware counters, network-on-chip (NoC), performance monitoring, system-on-chip (SoC)},
	author = {Fiorin, Leandro and Palermo, Gianluca and Silvano, Cristina}
}
@conference {115.ZaPaCaSiMa10,
	title = {Multicube Explorer: An Open Source Framework for Design Space Exploration of Chip Multi-Processors},
	booktitle = {2PARMA: Proceedings of the Workshop on Parallel Programming and Run-time Management Techniques for Many-core Architectures},
	year = {2010},
	month = {February},
	address = {Hannover, Germany},
	abstract = {Given the increasing complexity of Chip Multi-Processors (CMPs), a wide range of architecture parameters must be explored at design time to find the best trade-off in terms of multiple competing objectives (such as energy, delay, bandwidth, area, etc.) The design space of the target architecture is huge because of it should consider all possible combinations of each parameter (number of processors, processor issue width, L1 and L2 cache sizes, etc.). In this complex scenario, the multi-objective exploration of the huge design space of next generation CMPs cannot be anymore based on intuition and past experience of the design architects. An Automatic Design Space Exploration methodology is needed to support systematically the exploration and the quantitative comparison of the design alternatives in terms of multiple competing objectives (Pareto analysis). An overall design space exploration framework is needed to combine all optimizations into a global search space with a common interface to the simulation and evaluation tools. Our work1 focuses on the definition of an automatic multi-objective Design Space Exploration (DSE) framework for tuning Chip Multi-Processor architectures by evaluating a set of metrics (such as energy and delay) for the next generation embedded computing platforms. Multicube Explorer is an interactive open-source framework to enable the designer to automatically explore a design space of configurations for a parameterized architecture for which an executable model (use case simulator) exists. Multicube Explorer is an advanced multi-objective optimization framework which is entirely command-line/script driven and can be re-targeted to any configurable platform by writing a suitable XML design space definition file and providing a configurable simulator},
	author = {Zaccaria, Vittorio and Palermo, Gianluca and Castro, Fabrizio and Silvano, Cristina and Mariani, Giovanni}
}
@conference {129.Sietal.ISVLSI11,
	title = {Multicube: Multi-objective design space exploration of multi-core architectures},
	booktitle = {ISVLSI 2010: IEEE Annual Symposium on VLSI},
	year = {2010},
	month = {July},
	pages = {488{\textendash}493},
	address = {Lixouri, Kefalonia - Greece},
	abstract = {Technology trends enable the integration of many processor cores in a System-on-Chip (SoC). In these complex architectures, several architectural parameters can be tuned to find the best trade-off in terms of multiple metrics such as energy and delay. The main goal of the MULTICUBE project consists of the definition of an automatic Design Space Exploration framework to support the design of next generation many-core architectures.},
	doi = {http://dx.doi.org/10.1109/ISVLSI.2010.67},
	author = {Silvano, Cristina and Fornaciari, William and Palermo, Gianluca and Zaccaria, Vittorio and Castro, Fabrizio and Martinez, Marcos and Bocchio, Sara and Zafalon, Roberto and Avasare, Prabhat and Vanmeerbeeck, Geert and Ykman-Couvreur, Chantal and Wouters, Maryse and Kavka, Carlos and Onesti, Luka and Turco, Alessandro and Bondi, Umberto and Mariani, Giovanni and Posadas, Hector and Villar, Eugenio and Wu, Chris and Dongrui, Fan and Hao, Zhang and Shibin, Tang}
}
@conference {101.MaPaSiZa209,
	title = {Meta-model Assisted Optimization for Design Space Exploration of Multi-Processor Systems-on-Chip},
	booktitle = {Euromicro Proceedings of DSD{\textquoteright}09 - Conference on Digital System Design},
	year = {2009},
	month = {August},
	address = {Patras, Greece},
	abstract = {Multi-processor Systems-on-chip are currently designed by using platform-based synthesis techniques. In this approach, a wide range of platform parameters are tuned to find the best trade-offs in terms of the selected system figures of merit (such as energy, delay and area). This optimization phase is called Design Space Exploration (DSE) and it generally consists of a Multi-Objective Optimization (MOO) problem. The design space of a Multi-processor architecture is too large to e evaluated comprehensively. So far, several heuristic techniques have been proposed to address the MOO problem, but they are haracterized by low efficiency to identify the Pareto front. In this paper, we address the MPSoC DSE problem by using an NSGA-II modified to be assisted by an Artificial Neural Network (ANN). In particular we exploit statistical methods to compute the prediction confidence intervals for the ANN approximations. These information are adopted in the evolution control strategy in order to carefully select which individuals should be simulated. Experimental results show that the proposed techniques is able to reduce the simulations needed for the optimization without decreasing the quality of the obtained Pareto Front. Results are compared with state of the art techniques to demonstrate that optimization time due to simulation can be speed up by adopting statistical methods during evolution control.},
	keywords = {artificial neural network, meta-model assisted optimization, multi-objective optimization, multiprocessor system-on-chip (MPSoC)},
	doi = {http://dx.doi.org/10.1109/DSD.2009.154},
	author = {Mariani, Giovanni and Palermo, Gianluca and Silvano, Cristina and Zaccaria, Vittorio}
}
@conference {95.FiPaSi09,
	title = {MPSoCs Run-Time Monitoring through Networks-on-Chip},
	booktitle = {The 2009 Conference on Design, Automation and Test In Europe (DATE{\textquoteright}09)},
	year = {2009},
	month = {April/2009},
	address = {Nice, France},
	abstract = {Networks-on-Chip (NoCs) have appeared as design strategy to overcome the limitations, in terms of scalability, efficiency, and power consumption of current buses. In this paper, we discuss the idea of using NoCs to monitor system behaviour at run-time by tracing activities at initiators and targets. Main goal of the monitoring system is to retrieve information useful for run-time optimization and resources allocation in adaptive systems. Information detected by probes embedded within NIs is sent to a central unit, in charge of collecting and elaborating the data. We detail the design of the basic blocks and analyse the overhead associated with the ASIC implementation of the monitoring system, as well as discussing implications in terms of the additional traffic generated in the NoC.},
	keywords = {monitoring, network-on-chip (NoC)},
	author = {Fiorin, Leandro and Palermo, Gianluca and Silvano, Cristina}
}
@conference {96.MaPaSiZa09.2,
	title = {Multicube Explorer - A Design Space Exploration Framework for Embedded Systems-on-Chip},
	booktitle = {Proceedings of the DATE{\textquoteright}09 workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications},
	year = {2009},
	month = {April},
	address = {Nice, France},
	abstract = {Multicube Explorer is a design space exploration tool for supporting platform-based design. It allows a fast optimization of parameterized system architecture towards a set of objective functions (e.g., energy, delay and area), by interacting with a system-level simulator. Multicube Explorer provides a set of innovative sampling and optimization techniques to help finding the best objective function trade-offs. It also provides an open XML interface for supporting new platforms/architectures.},
	keywords = {area, delay, energy, fast optimization, multicube explorer, optimization techniques, platform-based design, system-level simulator, XML},
	author = {Mariani, Giovanni and Palermo, Gianluca and Silvano, Cristina and Zaccaria, Vittorio}
}
@conference {97.Silvanoetal09,
	title = {MULTICUBE: Multi-Objective Design Space Exploration of Multiprocessor Architectures for Embedded Multimedia Applications},
	booktitle = {Proceedings of the DATE{\textquoteright}09 workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications},
	year = {2009},
	month = {April},
	address = {Nice, France},
	author = {Silvano, Cristina and Palermo, Gianluca and Zaccaria, Vittorio and Fornaciari, William and Zafalon, Roberto and Bocchio, Sara and Martinez, Marcos and Wouters, Maryse and Vanmeerbeeck, Geert and Avasare, Prabhat and Onesti, Luka and Kavka, Carlos and Bondi, Umberto and Mariani, Giovanni and Villar, Eugenio and Posadas, Hector and Wu, Chris and Dongrui, Fan and Hao, Zhang}
}
@conference {99.MaPaSiZa09,
	title = {Multiprocessor System-on-Chip Design Space Exploration based on Multi-level Modeling Techniques},
	booktitle = {Proceedings of IEEE IC-SAMOS{\textquoteright}09 - International Conference on Embedded Computer Systems: Architectures, MOdeling, and Simulation},
	year = {2009},
	month = {July},
	address = {Samos, Greece},
	abstract = {Multi-processor Systems-on-chip are currently designed by using platform-based synthesis techniques. In this approach, a wide range of platform parameters are tuned to find the best trade-offs in terms of the selected system figures of erit (such as energy, delay and area). This optimization phase is called Design Space Exploration (DSE) and it generally consists of a Multi-Objective Optimization (MOO) problem. The design space of a Multi-processor architecture is too large to be evaluated comprehensively. So far, several heuristic techniques have been proposed to address the MOO problem, but they are haracterized by low efficiency to identify the Pareto set. In this paper we propose a methodology for heuristic platform based design based on evolutionary algorithms and multi-level simulation techniques. In particular, we extend the NSGA-II with an approximate neural network meta-model for multi-processor architectures in order to replace expensive platform simulations with fast meta-model evaluation. The model accuracy and efficiency is improved by exploiting high-level platform simulation techniques. High-level simulation allows us to reduce the overall complexity of the neural network and improving its prediction power. Experimental results show that the proposed techniques is able to reduce the number of simulations needed for the optimization without decreasing the quality of the obtained Pareto set. Results are compared with state of the art echniques to demonstrate that optimization time due to simulation can be sped up by adopting multi-level simulation techniques.},
	keywords = {artificial neural network, design space exploration, genetic algorithm, multi level modelling, multiprocessor system-on-chip (MPSoC), platform-based design},
	doi = {http://dx.doi.org/10.1109/ICSAMOS.2009.5289222},
	author = {Mariani, Giovanni and Palermo, Gianluca and Silvano, Cristina and Zaccaria, Vittorio}
}
@conference {83.Stuttgart,
	title = {Model-based Design Space Exploration for RTES with SysML and MARTE},
	booktitle = {Proceedings of FDL08},
	year = {2008},
	month = {September},
	address = {Stuttgart, Germany},
	abstract = {The features of the emerging modeling languages for system design allow designers to build models of almost any kind of heterogeneous hardware-software systems, including Real Time Embedded Systems (RTES). An important goal to achieve is the implementation and use of these models in all the steps of a common design flow. One of these steps is the Design Space Exploration (DSE), which helps designers in discovering the optimal solutions among all possible combinations after mapping functional to architectural specifications; for RTES this step is particularly hard as it should include scheduling analysis in order to proof the time validity after the mapping. This paper presents some guidelines on how to use SysML and MARTE profiles to identify design points fulfilling the timing constraints of an RTES, and thus allowing to automatize DSE analysis within the system design phase.},
	keywords = {high level design, unified modeling language (UML)},
	doi = {http://dx.doi.org/10.1109/FDL.2008.4641446},
	author = {Mura, Marcello and Murillo, Luis Gabriel and Prevostini, Mauro}
}
@conference {79.Ptsbrg,
	title = {Modelling the Power Cost of Security in Wireless Sensor Networks : the Case of 802.15.4},
	booktitle = {Proceedings of IEEE ICT08},
	year = {2008},
	month = {June},
	address = {Saint Petersburg, Russia},
	abstract = {Pervasive applications and in particular Wireless Sensors Networks have very strict requirements in terms of power consumption. It is well known that radio activity is very expensive in terms of energy; we show here that intensive processing activities (as security) represent a major contribution to power budget. In this paper we extend our methodology for analyzing the impact of Security related operations on power consumption and optimizing it. The analysis is based on experimental data and was validated with measurements on a real platform.},
	keywords = {low power design, modeling, protocol, wireless sensor networks},
	doi = {http://dx.doi.org/10.1109/ICTEL.2008.4652616},
	author = {Mura, Marcello and Fabbri, Fabio and Sami, Mariagiovanna}
}
@conference {57.PaMaSiLoCo07,
	title = {Mapping and Topology Customization Approaches for Application-Specific STNoC Designs},
	booktitle = {IEEE Proceedings of ASAP{\textquoteright}07 - 18th International Conference on Application-specific Systems, Architectures and Processors},
	year = {2007},
	month = {July},
	address = {Montr{\'e}al, Qu{\'e}bec, Canada},
	abstract = {Application-specific network-oriented communication architectures have recently become an effective solution to support high bandwidth Systems on-Chip. The Network on-Chip architectures considered so far range from regular to fully customized topologies for application specific designs requiring high-level bandwidth. To this end, a networkcentric design flow is necessary to support the design space exploration of complex SoCs with tight design constraints. This paper introduces four different approaches based on the orthogonalization of core mapping and topology customization applied to STNoC, the Network on-Chip developed by STMicroelecronics. The four methods are derived from the combination of the initial mappings to two standard topologies (ring and spidergon) with two types of topology customization based on the insertion of cross-links to reduce the network distance of standard topologies},
	keywords = {application specific design, mapping, network-on-chip (NoC), STNoC, topology customization},
	doi = {http://dx.doi.org/10.1109/ASAP.2007.4429959},
	author = {Palermo, Gianluca and Mariani, Giovanni and Silvano, Cristina and Locatelli, Riccardo and Coppola, Marcello}
}
@conference {55.DaFeMa,
	title = {A Memory Unit for Priority Management in IPSec Accelerators},
	booktitle = {proceedings of ICC07. Glasgow, Scotland: IEEE Communications Society},
	year = {2007},
	month = {June 24},
	address = {Glasgow, Scotland},
	abstract = {This paper introduces a hardware architecture for high speed network processors, focusing on support for Quality of Service in IPSec-dedicated systems. The effort is aimed at defining a secure system on chip environment, where the speed and security requirements are of utmost importance. In particular, a method is devised to introduce and support Quality of Service through priorities at this level. An architecture of a memory system that provides automatic priority management is proposed.},
	keywords = {accelerator, IPSec, priority, quality of service (QoS), security, system-on-chip (SoC), SystemC},
	doi = {http://dx.doi.org/10.1109/ICC.2007.257},
	author = {Dadda, Luigi and Ferrante, Alberto and Macchetti, Marco}
}
@inbook {30.BaLaPre2005,
	title = {A Methodology for Bridging the Gap between UML and Codesign},
	booktitle = {UML for SOC Design},
	year = {2005},
	pages = {119-146},
	publisher = {Springer},
	organization = {Springer},
	address = {Dordrecht, The Netherlands},
	abstract = {The Unified Modeling Language (UML) is getting more popular among system designers due to the need to raise the level of abstraction in system specifications. We present here a methodology that integrates UML specifications with a hardware/software codesign platform. This work aims to give a contribution toward SoC Design Automation starting from system level specification down to hardware/software partitioning and integration.},
	keywords = {HW/SW co-design, methodology, system specifications, unified modeling language (UML)},
	author = {Basu, Ananda Shankar and Lajolo, Marcello and Prevostini, Mauro},
	editor = {Martin, Grant and Muller, Wolfgang}
}
@Patent {22.pat20040228482PATENT,
	title = {Method of implementing one-to-one binary function and relative hardware device, especially for a Rijndael S-box},
	number = {US 10/816,791 -- 	EP 20030425211},
	year = {2004},
	month = {10/2004},
	type = {Grant},
	chapter = {US 7502464 B2 -- EP 1465365 A1 },
	abstract = {A method for implementing one-to-one binary functions defined on the Galois field GF(2^8) is very useful for forming fast and low power hardware devices regardless of the binary function. The method includes decoding an input byte for generating at least one bit string that contains only one active bit, and logically combining the bits of the bit string according to the binary function for generating a 256-bit string representing a corresponding output byte. The 256-bit string is then encoded in a byte for obtaining the output byte.},
	issn = {US 7502464 B2},
	author = {Macchetti, Marco and Fragneto, Pasqualina and Bertoni, Guido Marco}
}
@conference {26.BoFeDuPi2004,
	title = {A Methodology for Testing IPSec-based Systems},
	booktitle = {SoftCOM 2004},
	year = {2004},
	month = {October},
	pages = {22-26},
	address = {Split},
	abstract = {{IPSec is a suite of protocols adding security to communications at the IP level. This suite of protocols is becoming more and more important as it is included as mandatory security mechanism in IPv6. This paper focuses on a methodology for testing IPSec implementations. A UML model of the IPSec suite of protocols was developed. Test cases were obtained applying a coverage method on the same model.}},
	keywords = {encapsulating security payload (ESP), IPSec, security, testing, unified modeling language (UML)},
	author = {Boiko, Uljana and Ferrante, Alberto and Lo Duca, Antonietta and Piuri, Vincenzo}
}
@Patent {10.pat20030068036PATENT,
	title = {Method and circuit for data encryption/decryption},
	number = {US 09/974,705},
	year = {2003},
	month = {April},
	type = {Grant},
	chapter = {US7801301 B2},
	abstract = {Data are converted between an unencrypted and an encrypted format according to the Rijndael algorithm, including a plurality of rounds. Each round is comprised of fixed set of transformations applied to a two-dimensional array, designated state, of rows and columns of bit words. At least a part of said transformations are applied on a transposed version of the state, wherein rows and columns are transposed for the columns and rows, respectively.},
	issn = {US7801301B2},
	author = {Macchetti, Marco and Marchesin, Stefano and Bondi, Umberto and Breveglieri, Luca and Bertoni, Guido Marco and Fragneto, Pasqualina}
}
@conference {9.SaSaSciSiZaZa2003,
	title = {A Methodology for efficient architectural exploration of energy-delay trade-offs for embedded systems},
	booktitle = {SAC 2003},
	year = {2003},
	month = {March},
	pages = {672-678},
	address = {Melbourne},
	abstract = {The main goal of this paper is to identify the best architecture of an embedded system by considering at the same time energy and delay, avoiding the comprehensive analysis of the architectural design space. We adopt the Energy-Delay Product (EDP) as the evaluation metric to compare the alternative architectures of the target system. The paper analyzes an extended adaptive random search algorithm (ADGREED) to efficiently explore the architectural design space. The ADGREED algorithm is a pseudo-random optimization algorithm that combines the best potentialities of the adaptive random search (ADRAS) and the Greedy deterministic algorithm. The analysis has been carried out through the architectural optimization of the memory subsystem of a real-word embedded system executing the set of Mediabench benchmarks for multimedia applications. The reported experimental results have shown a reduction up to one order of magnitude of the number of design alternatives analyzed during the exploration phase, while maintaining very high accuracy.},
	keywords = {design space exploration, embedded systems},
	doi = {http://dx.doi.org/10.1145/952532.952664},
	author = {Salvemini, Lorenzo and Sami, Mariagiovanna and Sciuto, Donatella and Silvano, Cristina and Zaccaria, Vittorio and Zafalon, Roberto}
}
