@conference {18485, title = {Evaluating the Impact of Environmental Factors on Physically Unclonable Functions}, booktitle = {International Symposium on Field-Programmable Gate Arrays FPGA 2016}, series = {Proceedings of the 2016 ACM/SIGDA}, year = {2016}, month = {02/2016}, pages = {279}, publisher = {ACM New York, NY, USA}, organization = {ACM New York, NY, USA}, address = {Monterey, CA, USA}, abstract = {Fabrication process introduces some inherent variability to the attributes of transistors (in particular length, widths, oxide thickness). As a result, every chip is physically unique. Physical uniqueness of microelectronics components can be used for multiple security applications. Physically Unclonable Functions (PUFs) are built to extract the physical uniqueness of microelectronics components and make it usable for secure applications. However, the microelectronics components used by PUFs designs suffer from external, environmental variations that impact the PUF behavior. Variations of temperature gradients during manufacturing can bias the PUF responses. Variations of temperature or thermal noise during PUF operation change the behavior of the circuit, and can introduce errors in PUF responses. Detailed knowledge of the behavior of PUFs operating over various environmental factors is needed to reliably extract and demonstrate uniqueness of the chips. In this work, we present a detailed and exhaustive analysis of the behavior of two PUF designs, a ring oscillator PUF and a timing path violation PUF. We have implemented both PUFs using FPGA fabricated by Xilinx, and analyzed their behavior while varying temperature and supply voltage. Our experiments quantify the robustness of each design, demonstrate their sensitivity to temperature and show the impact which supply voltage has on the uniqueness of the analyzed PUFs. }, isbn = {978-1-4503-3856-1}, doi = {10.1145/2847263.2847308}, url = {http://doi.acm.org/10.1145/2847263.2847308}, author = {Bellon, Sebastien and Favi, Claudio and Malek, Miroslaw and Macchetti, Marco and Regazzoni, Francesco} } @article {18064, title = {Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology}, journal = {Springer Transactions on Computational Science}, volume = {5430}, year = {2009}, month = {February}, pages = {230{\textendash}243}, author = {Regazzoni, Francesco and Eisenbarth, Thomas and Poschmann, Axel and Groschdl, Johann and Gurkaynak, Frank and Macchetti, Marco and Toprak, Zeynep and Pozzi, Laura and Paar, Christof and Leblebici, Yusuf and Ienne, Paolo} } @conference {21.968073, title = {Efficient AES implementations for ARM based platforms}, booktitle = {SAC {\textquoteright}04: Proceedings of the 2004 ACM symposium on Applied computing}, year = {2004}, pages = {841{\textendash}845}, publisher = {ACM Press, New York, USA}, organization = {ACM Press, New York, USA}, address = {Nicosia, Cyprus}, abstract = {The Advanced Encryption Standard (AES) contest, started by the U.S. National Institute of Standards and Technology (NIST), saw the Rijndael [13] algorithm as its winner [11]. Although the AES is fully defined in terms of functionality, it requires best exploitation of architectural parameters in order to reach the optimum performance on specific architectures. Our work concentrates on ARM cores [1] widely used in the embedded industry. Most promising implementation choices for the common ARM Instruction Set Architecture (ISA) are identified, and a new implementation for the linear mixing layer is proposed. The performance improvement over current implementations is demonstrated by a case study on the Intel StrongARM SA-1110 Microprocessor [2]. Further improvements based on exploitation of memory hierarchies are also described, and the corresponding performance figures are presented.}, keywords = {advanced encryption standard (AES), ARM microprocessor, cache memories, code optimisation}, isbn = {1-58113-812-1}, doi = {http://doi.acm.org/10.1145/967900.968073}, author = {Atasu, Kubilay and Breveglieri, Luca and Macchetti, Marco} } @conference {8.752733, title = {Efficient Software Implementation of AES on 32-Bit Platforms}, booktitle = {CHES {\textquoteright}02: Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems}, year = {2003}, pages = {159{\textendash}171}, publisher = {Springer-Verlag}, organization = {Springer-Verlag}, address = {London, UK}, abstract = {Rijndael is the winner algorithm of the AES contest; therefore it should become the most used symmetric-key cryptographic algorithm. One important application of this new standard is cryptography on smart cards. In this paper we present an optimisation of the Rijndael algorithm to speed up execution on 32-bits processors with memory constraints, such as those used in smart cards. First a theoretical analysis of the Rijndael algorithm and of the proposed optimisation is discussed, and then simulation results of the optimised algorithm on different processors are presented and compared with other reference implementations, as known from the technical literature.}, isbn = {3-540-00409-2}, author = {Bertoni, Guido Marco and Breveglieri, Luca and Fragneto, Pasqualina and Macchetti, Marco and Marchesin, Stefano} } @conference {3.CaPoMaMaBeBreFra2001, title = {Efficient C implementation of the ECC and AES cryptographic systems}, booktitle = {Technology Leadership Day - organized by the MicroSwiss Network}, year = {2001}, month = {October 10}, address = {Fribourg}, author = {Cassoli, Federico and Polloni, Flavio and Marchesin, Stefano and Macchetti, Marco and Bertoni, Guido Marco and Breveglieri, Luca and Fragneto, Pasqualina} }