@conference {18551,
	title = {Dark{M}em: Fine-Grained Power Management of Local Memories for Accelerators in Embedded Systems},
	booktitle = {Proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC)},
	year = {2018},
	doi = {10.1109/ASPDAC.2018.8297403},
	author = {Pilato, Christian and Carloni, Luca P.}
}
@article {18533,
	title = {Determination of the Edge of Criticality in Echo State Networks Through Fisher Information Maximization},
	journal = {IEEE Transactions on Neural Networks and Learning Systems},
	volume = {29},
	year = {2018},
	month = {March},
	pages = {706-717},
	keywords = {Echo state network (ESN), echo state networks, edge of criticality, ESN, Fisher information, Fisher information matrix, Fisher information maximization, Jacobian matrices, Learning systems, Neurons, nonparametric estimation, nonparametric estimator, nonparametric statistics, prediction error, Probability density function, recurrent neural nets, recurrent neural networks, Reservoirs, RNN, short-term memory capacity, Training},
	issn = {2162-237X},
	doi = {10.1109/TNNLS.2016.2644268},
	author = {Livi, Lorenzo and Bianchi, Filippo Maria and Alippi, Cesare}
}
@conference {18560,
	title = {The design space of the number theoretic transform: {A} survey},
	booktitle = {2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, {SAMOS} 2017, Pythagorion, Greece, July 17-20, 2017 (Invited)},
	year = {2017},
	doi = {10.1109/SAMOS.2017.8344640},
	url = {https://doi.org/10.1109/SAMOS.2017.8344640},
	author = {Valencia, Felipe and Khalid, Ayesha and O{\textquoteright}Sullivan, Elizabeth and Regazzoni, Francesco}
}
@conference {18539,
	title = {Detecting changes at the sensor level in cyber-physical systems: Methodology and technological implementation},
	booktitle = {2017 International Joint Conference on Neural Networks (IJCNN)},
	year = {2017},
	month = {May},
	keywords = {actuators, adaptation mechanisms, adaptive systems, Change detection, change-point method, Computational modeling, cyber-physical systems, datastreams, fault detection and diagnosis, fault tolerant computing, ICI-based change detection test, Intelligence for Embedded and Cyber-physical Systems, Mann-Whitney change-point method, Mathematical model, model-free change detection test, Predictive models, Random variables, self-adaptive CPS, self-adaptive cyber-physical systems, self-configuration, self-healing skills, self-management, sensor acquisitions, sensor level, sensors, signal detection, Smart Sensor Networks, ST STM32 Nucleo platform, time-variant environments, Training},
	doi = {10.1109/IJCNN.2017.7966066},
	author = {Alippi, Cesare and D{\textquoteright}Alto, Viviana and Falchetto, Mirko and Pau, Danilo and Roveri, Manuel}
}
@conference {18542,
	title = {Detecting changes in sequences of attributed graphs},
	booktitle = {2017 IEEE Symposium Series on Computational Intelligence (SSCI)},
	year = {2017},
	month = {Nov},
	keywords = {Aerospace electronics, Anomaly detection, application domains, Attributed graph, attributed graphs, Change detection, Concept drift, Dynamic/Evolving graph, Electronic mail, Embedding, geometric graphs, Graph matching, graph theory, graph-based representations, Markov chains, Markov processes, Microsoft Windows, pair-wise relations, Prototypes, real-world systems, Stationarity, topology, Training, variable order},
	doi = {10.1109/SSCI.2017.8285273},
	author = {Zambon, Daniele and Livi, Lorenzo and Alippi, Cesare}
}
@conference {18481,
	title = {Design methodologies for securing cyber-physical systems},
	booktitle = {2015 International Conference on Hardware/Software Codesign and System Synthesis CODES+ISSS},
	year = {2015},
	month = {10/2015},
	pages = {30-36},
	publisher = {IEEE},
	organization = {IEEE},
	address = {Amsterdam, Netherlands},
	abstract = {Cyber-Physical Systems (CPS) are in most cases safety- and mission-critical. Standard design techniques used for securing embedded systems are not suitable for CPS due to the restricted computation and communication budget available in the latter. In addition, the sensitivity of sensed data and the presence of actuation components further increase the security requirements of CPS. To address these issues, it is necessary to provide new design methods in which security is considered from the beginning of the whole design flow and addressed in a holistic way. In this paper, we focus on the design of secure CPS as part of the complete CPS design process, and provide insights into new requirements on platform-aware design of control components, design methodologies and architectures posed by CPS design. We start by discussing methods for the multi-disciplinary modeling, simulation, tools, and software synthesis challenges for CPS. We also present a framework for design of secure control systems for CPS, while taking into account properties of the underlying computation and communication platforms. Finally, we describe the security challenges in the computing hardware that is used in CPS},
	keywords = {cyber-physical system security, design flow, embedded systems, platform-aware design, safety-critical system, security of data, sensed data sensitivity},
	isbn = {978-1-4673-8321-9},
	doi = {10.1109/CODESISSS.2015.7331365},
	url = {http://dx.doi.org/10.1109/CODESISSS.2015.7331365},
	author = {Faruque, Mohammad Abdullah A and Regazzoni, Francesco and Pajic, Miroslav}
}
@conference {18091,
	title = {DRuiD: Designing Reconfigurable Architectures with Decision-making Support},
	booktitle = {19th Asia and South Pacific Design Automation Conference (ASP-DAC)},
	year = {2014},
	month = {01/2014},
	address = {Singapore},
	url = {http://home.deib.polimi.it/gpalermo/papers/ASPDAC14DRUID.pdf},
	author = {Mariani, Giovanni and Meeuws, Roel and Palermo, Gianluca and Sima, Vlad-Mihai and Silvano, Cristina and Bertels, Koen}
}
@article {18093,
	title = {Design-space Exploration and Runtime Resource Management for Multicores},
	journal = {ACM Transactions on Embedded Computing Systems (TECS) - Special issue on application-specific processors},
	volume = {13},
	issue = {2},
	year = {2013},
	month = {09/2013},
	pages = {20:1{\textendash}20:27},
	abstract = {Application-specific multicore architectures are usually designed by using a configurable platform in which a set of parameters can be tuned to find the best trade-off in terms of the selected figures of merit (such as energy, delay, and area). This multi-objective optimization phase is called Design-Space Exploration (DSE). Among the design-time (hardware) configurable parameters we can find the memory subsystem configuration (such as cache size and associativity) and other architectural parameters such as the instruction-level parallelism of the system processors. Among the runtime (software) configurable parameters we can find the degree of task-level parallelism associated with each application running on the platform.

The contribution of this article is twofold; first, we introduce an evolutionary (NSGA-II-based) methodology for identifying a hardware configuration which is robust with respect to applications and corresponding datasets. Second, we introduce a novel runtime heuristic that exploits design-time identified operating points to provide guaranteed throughput to each application. Experimental results show that the design-time/runtime combined approach improves the runtime performance of the system with respect to existing reference techniques, while meeting the overall power budget.},
	keywords = {application-specific platforms, design-space exploration, genetic algorithms, Multicore architectures, operating systems, resource reservation, runtime resource management, throughput maximization},
	issn = {1539-9087},
	doi = {10.1145/2514641.2514647},
	author = {Mariani, Giovanni and Palermo, Gianluca and Zaccaria, Vittorio and Silvano, Cristina}
}
@inbook {17695,
	title = {Dynamic Adaptation of Security and QoS in Energy-Harvesting Sensors Nodes},
	booktitle = {e-Business and Telecommunications},
	series = {Communications in Computer and Information Science},
	volume = {222},
	year = {2012},
	pages = {243-258},
	publisher = {Springer},
	organization = {Springer},
	address = { Berlin Heidelberg},
	keywords = {energy harvesting, priority, quality of service (QoS), security, wireless sensor networks},
	isbn = {978-3-642-25205-1},
	doi = {10.1007/978-3-642-25206-8_16},
	url = {http://dx.doi.org/10.1007/978-3-642-25206-8_16},
	author = {Taddeo, Antonio Vincenzo and Mura, Marcello and Ferrante, Alberto},
	editor = {Obaidat, Mohammad and Tsihrintzis, George and Filipe, Joaquim}
}
@conference {151.FiMiSa11,
	title = {Design of Fault Tolerant Network Interfaces for NoCs},
	booktitle = {Proceedings of 14th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD{\textquoteright}11)},
	year = {2011},
	month = {September},
	address = {Oulu, Finland},
	keywords = {fault tolerance, network interface, network-on-chip (NoC), system-on-chip (SoC)},
	doi = {http://dx.doi.org/10.1109/DSD.2011.54},
	author = {Fiorin, Leandro and Micconi, Laura and Sami, Mariagiovanna}
}
@inbook {18092,
	title = {Design Space Exploration for Run-Time Management of a Reconfigurable System for Video Streaming},
	booktitle = {Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach},
	year = {2011},
	pages = {189-204},
	publisher = {Springer},
	organization = {Springer},
	edition = {1},
	isbn = {978-1-4419-8836-2},
	author = {Mariani, Giovanni and Avasare, Prabhat and Ykman-Couvreur, Chantal and Vanmeerbeeck, Geert and Palermo, Gianluca and Silvano, Cristina and Zaccaria, Vittorio},
	editor = {Silvano, Cristina and Fornaciari, William and Villar, Eugenio}
}
@inbook {138.MaAvYkVaPaSiZa.2011,
	title = {Design Space Exploration of a Reconfigurable System for Supporting Video Streaming Run-time Management},
	booktitle = {Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach},
	year = {2011},
	publisher = {Springer},
	organization = {Springer},
	address = {New York, USA},
	abstract = {This paper reports a case study of Design Space Exploration for supporting Run-time Resource Management (RRM). In particular the management of system resources for an MPSoC dedicated to multiple MPEG4 encoding is addressed in the context of an Automotive Cognitive Safety System (ACSS). The runtime management problem is defined as the minimization of the platform power consumption under resource and Quality of Service (QoS) constraints. The paper provides an insight of both, design-time and run-time aspects of the problem. During the prelimiary design-time Design Space Exploration (DSE) phase, the best configurations of run-time tunable parameters are statically identified for providing the best trade-offs in terms of run-time costs and application QoS. To speed up the optimization process without reducing the quality of final results, a multi-simulator framework is used for modeling platform performance. At run-time, the RRM exploits the design-time DSE results for deciding an operating configuration to be loaded for each MPEG4 encoder. This operation is carried out dynamically, by following the QoS requirements of the specific use-case.},
	author = {Mariani, Giovanni and Avasare, Prabhat and Ykman-Couvreur, Chantal and Vanmeerbeeck, Geert and Palermo, Gianluca and Silvano, Cristina and Zaccaria, Vittorio}
}
@inbook {140.KaTuPaSiZaMaBoDo.2011,
	title = {Design Space Exploration of Parallel Architectures},
	booktitle = {Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach},
	year = {2011},
	publisher = {Springer},
	organization = {Springer},
	address = {New York, USA},
	abstract = {This chapter will present two significant applications of the MULTICUBE design space exploration framework. The first part will present the design space exploration of a low power processor developed by STMicroelectronics by using the modeFRONTIER tool to demonstrate the benefits DSE not only in terms of objective quality, but also in terms of impact on the design process within the corporate environment. The second part will describe the application of RSM models developed within MULTICUBE to a tiled, multiple-instruction, many-core architecture developed by ICT China. Overall, the results have showed that different models can present a trade-off of accuracy versus computational effort. In fact, throughout the evaluation, we observed that high accuracy models require high computational time (for both model construction time and prediction time); vice-versa low model construction and prediction time has led to low accuracy.},
	author = {Kavka, Carlos and Turco, Alessandro and Palermo, Gianluca and Silvano, Cristina and Zaccaria, Vittorio and Mariani, Giovanni and Bocchio, Sara and Dongrui, Fan}
}
@inbook {144.AvYkVaMaPaSiZa.2011,
	title = {Design Space Exploration Supporting Run-time Resource Management},
	booktitle = {Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach},
	year = {2011},
	publisher = {Springer},
	organization = {Springer},
	address = {New York, USA},
	abstract = {Running multiple applications optimally in terms of Quality of Service (e.g., performance and power consumption) on embedded multi-core platforms is a huge challenge.Moreover, current applications exhibit unpredictable changes of the environment and workload conditions which makes the task of running them optimally even more difficult. This dynamic trend in application runs will grow even more in future applications. This paper presents an automated tool flow which tackles this challenge by a two-step approach: first at design-time, a Design Space Exploration (DSE) tool is coupled with a platform simulator(s) to get optimum operating points for the set of target applications. Secondly, at run-time, a lightweight Run-time Resource Manager (RRM) leverages the design-time DSE results for deciding an operating configuration to be loaded at run-time for each application. This decision is performed dynamically, by taking into consideration available platform resources and the QoS requirements of the specific use-case. To keep RRM execution and resource overhead at minimum, a very fast optimisation heuristic is integrated. Application of this tool-flow on a real-life multimedia use case (described in Chapter 9 of the book of this paper) will demonstrate a significant speedup in optimisation process while maintaining desired Quality of Service.},
	author = {Avasare, Prabhat and Ykman-Couvreur, Chantal and Vanmeerbeeck, Geert and Mariani, Giovanni and Palermo, Gianluca and Silvano, Cristina and Zaccaria, Vittorio}
}
@inbook {18085,
	title = {A Design Flow and Evaluation Framework for DPA-resistant Instruction Set Extensions},
	booktitle = {Cryptographic Hardware and Embedded Systems (CHES)},
	series = {Lecture Notes in Computer Science},
	volume = {5747},
	year = {2009},
	month = {September},
	pages = {205-219},
	publisher = {Springer Berlin Heidelberg},
	organization = {Springer Berlin Heidelberg},
	address = {Lausanne, Switzerland},
	abstract = {Power-based side channel attacks are a significant security risk, especially for embedded applications. To improve the security of such devices, protected logic styles have been proposed as an alternative to CMOS. However, they should only be used sparingly, since their area and power consumption are both significantly larger than for CMOS. We propose to augment a processor, realized in CMOS, with custom instruction set extensions, designed with security and performance as the primary objectives, that are realized in a protected logic. We have developed a design flow based on standard CAD tools that can automatically synthesize and place-and-route such hybrid designs. The flow is integrated into a simulation and evaluation environment to quantify the security achieved on a sound basis. Using MCML logic as a case study, we have explored different partitions of the PRESENT block cipher between protected and unprotected logic. This experiment illustrates the tradeoff between the type and amount of application-level functionality implemented in protected logic and the level of security achieved by the design. Our design approach and evaluation tools are generic and could be used to partition any algorithm using any protected logic style.},
	isbn = {978-3-642-04137-2},
	doi = {10.1007/978-3-642-04138-9_15},
	author = {Regazzoni, Francesco and Cevrero, Alessandro and Standaert, Fran{\c c}ois-Xavier and Badel, St{\'e}phane and Kluter, Theo and Brisk, Philip and Leblebici, Yusuf and Ienne, Paolo}
}
@conference {98.MaPaSiZa309,
	title = {A Design Space Exploration Methodology Supporting Run-Time Resource Management for Multi-Processors System on-Chip},
	booktitle = {Proceedings IEEE SASP{\textquoteright}09 - Symposium on Application Specific Processors},
	year = {2009},
	month = {July},
	address = {San Francisco, CA, USA},
	abstract = {Application Specific multi-processor Systems-on-chip are currently designed by using platform-based synthesis techniques. In this approach, a wide range of platform parameters are tuned either at design-time or at run-time, to provide the best trade-offs in terms of the selected system figures of merit (such as power and throughput) for a dynamic application-specific workload. Among the design-time (hardware) configurable parameters we can find the memory sub-system configuration (e.g. cache size and associativity) and other architectural parameters such as the instruction-level parallelism of the system processors. Among the run-time (software) configurable parameters we can find the overall degree of task-level parallelism associated with each application running on the chip. Typically, while the design-time exploration is performed in the early development stages for a set of static parameters, the tuning of the run-time parameters is performed dynamically by a run-time management software module after the system has been deployed. In this paper, we introduce a methodology for identifying a hardware configuration which is robust with respect to the variable workload scenario introduced by the run-time management. Moreover, the proposed methodology is aimed at providing useful information about the optimal software operating points of the applications in terms of task-level parallelism. The proposed methodology is based on the NSGA-II evolutionary heuristic algorithm assisted by an Artificial Neural Network (ANN). We then introduce a run-time management policy which is able to exploit the above information to maximize the performance of the system under power budget constraints. Experimental results show that the proposed technique is able to reduce the overall design space exploration time yet providing a near-optimal solution, in terms of hardware parameters, to enable an innovative and efficient run-time anagement policy.},
	keywords = {artificial neural network, design space exploration, meta-model assisted optimization, multi-objective optimization, multiprocessor system-on-chip (MPSoC), run-time resource management},
	doi = {http://dx.doi.org/10.1109/SASP.2009.5226331},
	author = {Mariani, Giovanni and Palermo, Gianluca and Silvano, Cristina and Zaccaria, Vittorio}
}
@conference {77.MaToFi08,
	title = {Design Space Exploration of PISA Architecture For ONU Auto-discovery Process},
	booktitle = {proceedings of 6th International Conference of Electrical Engineering (ICEENG)},
	year = {2009},
	month = {May 27-29},
	address = {Cairo, Egypt},
	abstract = {The goal of the paper is to optimize the PISA architecture for the ONU Auto-discovery process. This Auto-discovery process has been written in C language following the IEEE 802.3ah MPCP standard. Using SimpleScalar [3] simulation tool, the architecture profile is evaluated in order to decide the range of the design exploration. Then, using Wattch [1] and CACTI [2] simulation tools the CPI, average power consumed and cache area are calculated for each design point, the cost function is defined and evaluated for each design point using greedy strategy. The Auto-discovery process has been written in VHDL and using Synopys power compiler [4] the power consumption has been calculated and then we compared between the VHDL implementation and the PISA architecture from the power consumption point of view.},
	keywords = {design space exploration},
	doi = {http://dx.doi.org/10.1109/ICNM.2009.4907186},
	author = {Mady, Alie El-Din and Tonini, Andrea and Finardi, Davide}
}
@conference {68.FiPaLuSi07,
	title = {A Data protection Unit for NoC-based Architecture},
	booktitle = {CODES+ISSS 2007, in proceedings of the Fifth IEEE/ACM/FIP International Conference of Hardware/Software Codesign and System Synthesis (CODES+ISSS 2007)},
	year = {2007},
	month = {September 30},
	address = {Salzburg, Austria},
	abstract = {Security is gaining increasing relevance in the development of embedded devices. Towards a secure system at each level of design, this paper addresses the security aspects related to Network-on-Chip (NoC) architectures, foreseen as the communication infrastructure of next generation embedded devices. In the context of NoC-based Multiprocessor systems, we focus on the topic, not thoroughly faced yet, of data protection. We present the architecture of a Data Protection Unit (DPU) designed for implementation within the Network Interface (NI). The DPU supports the capability to check and limit the access rights(none, read, write or both) of processors requesting access to data locations in a shared memory - in particular distinguishing between the operating roles (supervisor or user) of processing elements. We explore different alternative implementations and demonstrate how the DPU unit does not affect the network latency if the memory request has the appropriate rights. In the experimental section we show synthesis results for different ASIC implementations of the Data Protection Unit.},
	keywords = {data protection, embedded systems, multiprocessor system-on-chip (MPSoC), network-on-chip (NoC), security},
	doi = {http://dx.doi.org/10.1145/1289816.1289858},
	author = {Fiorin, Leandro and Palermo, Gianluca and Lukovi{\'c}, Slobodan and Silvano, Cristina}
}
@conference {72.Ferrari2007,
	title = {Design exploration for an Ogg/Vorbis decoder for VLIW architectures},
	booktitle = {Workshop on Application Specific Processors (WASP {\textquoteright}07)},
	year = {2007},
	month = {October},
	address = {Salzburg, Austria},
	abstract = {Parallel processing architectures are set to be the dominating design approach for a plethora of application domains, mainly because of the eminent reach of the so-called power wall, and furthermore because of the evident gap between the application/software development growth and Moore{\textquoteright}s law. In this work a design space for an audio codec is explored, targeted at a VLIW architecture. The Ogg/Vorbis codec is first analyzed and optimized for exposing potential parallelism to the VEX tools for compilation and parallel architecture exploration. Furthermore, the use of custom instructions is assessed and important results are obtained by means of a modification on the toolchain to reveal dynamic profiling information},
	author = {Ferrari, Federico and Amador, Erick}
}
@conference {34.BaLaPrevos2005,
	title = {Design and Synthesis of Reusable Platforms with Programmable Interconnects},
	booktitle = {UML-SoC 2005},
	year = {2005},
	month = {June 12},
	pages = {43-48},
	address = {Anaheim, California},
	abstract = {Platform based design requires to restrict the number of possible design choices in order to make it possible to come up with programmable solutions able to cope with the current complexity of System-On-Chip (SoC) designs. Nowadays there is a general consensus toward the fact that an effective Electronic System Level (ESL) design methodology must provide a specific support for platform specification, hardware/software partitioning and programmatic interfaces synthesis in order to allow designers to exploit the potentials of state-of-the-art technologies. In this work we present a methodology that leverages on UML for building new architectural platforms to be used to be used in the system design process. We show how our methodology can allow to reuse pre-designed platforms by adding new architectural components and by customizing their interconnections},
	keywords = {HW/SW co-design, system-on-chip (SoC), unified modeling language (UML)},
	author = {Basu, Ananda Shankar and Lajolo, Marcello and Prevostini, Mauro}
}
@conference {18.969266,
	title = {The Design of a High Speed ASIC Unit for the Hash Function SHA-256 (384,512)},
	booktitle = {DATE {\textquoteright}04: Proceedings of the conference on Design, automation and test in Europe},
	year = {2004},
	pages = {30070},
	publisher = {IEEE Computer Society},
	organization = {IEEE Computer Society},
	address = {Washington, DC, USA},
	abstract = {After recalling the basic algorithms published by NIST for implementing the hash functions SHA-256 (384, 512), a basic circuit characterized by a cascade of full adder arrays is given. Implementation options are discussed and two methods for improving speed are exposed: the delay balancing and the pipelining. An application of the former is first given, obtaining a circuit that reduces the length of the critical path by a full adder array. A pipelined version is then given, obtaining a reduction of two full adder arrays in the critical path. The two methods are afterwards combined and the results obtained through hardware synthesis are exposed, where a comparison between the new circuits is also given.},
	isbn = {0-7695-2085-5-3},
	doi = {http://dx.doi.org/10.1109/DATE.2004.1269207},
	author = {Dadda, Luigi and Macchetti, Marco and Owen, Jeff}
}
@conference {1.371690,
	title = {Development cost and size estimation starting from high-level specifications},
	booktitle = {CODES {\textquoteright}01: Proceedings of the ninth international symposium on Hardware/software codesign},
	year = {2001},
	pages = {86-91},
	publisher = {ACM Press, New York, USA},
	organization = {ACM Press, New York, USA},
	address = {Copenhagen, Denmark},
	abstract = {This paper addresses the problem of estimating cost and development effort of a system, starting from its complete or partial high-level description. In addition, some modifications to evaluate the cost-effectiveness of reusing VHDL-based designs, are presented. The proposed approach has been formalized using an approach similar to the COCOMO analysis strategy, enhanced by a project size prediction methodology based on a VHDL function point metric. The proposed design size estimation methodology has been validated through a significant benchmark. The LEON-I microprocessor, whose VHDL description is of public domain.},
	keywords = {concurrent engineering, design reuse, process management, project size estimation, VHDL},
	isbn = {1-58113-364-2},
	doi = {http://dx.doi.org/10.1109/HSC.2001.924656},
	author = {Fornaciari, William and Salice, Fabio and Bondi, Umberto and Magini, Edi}
}
