@article {18569,
	title = {Compact Circuits for Combined AES},
	journal = {Journal of Cryptographic Engineering},
	year = {In Press},
	author = {Banik, Subhadeep and Bogdanov, Andrey and Regazzoni, Francesco}
}
@article {18567,
	title = {Customized Instructions for Protection Against Memory Integrity Attacks},
	journal = {IEEE Embedded Systems Letters},
	year = {In Press},
	author = {Roy, Debapriya Basu and Alam, Manaar and Bhattacharya, Sarani and Govindan, Vidya and Regazzoni, Francesco and Chakraborty, Rajat Subhra and Mukhopadhyay, Debdeep}
}
@conference {18573,
	title = {Compact, Scalable, and Efficient Gaussian Samplers for Lattice-Based Cryptography},
	booktitle = {Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) 2018},
	year = {2018},
	author = {Khalid, Ayesha and Howe, James and Rafferty, Ciara and Regazzoni, Francesco and O{\textquoteright}Neil, Maire}
}
@conference {18581,
	title = {Cross-layer Design of Reconfigurable Cyber-Physical Systems},
	booktitle = {Proceedings of Design, Automation and Test in Europe (DATE) 2017},
	year = {2017},
	author = {Masin, Michael and Palumbo, Francesca and Myrhaug, Hans and Filho, Julio A. de Oliv and Pastena, Max and Pelcat, Maxime and Raffo, Luigi and Regazzoni, Francesco and Sanchez, Angel A. and Toffetti, Antonella and de la Torre, Eduardo and Zedda, Katiuscia}
}
@conference {18477,
	title = {Challenges in designing trustworthy cryptographic co-processors},
	booktitle = {IEEE International Symposium on Circuits and Systems (ISCAS) 2015},
	year = {2015},
	month = {09/2015},
	pages = {2009-2012},
	publisher = {IEEE},
	organization = {IEEE},
	address = {Lisbon, Portugal},
	abstract = {Security is becoming ubiquitous in our society. However, the vulnerability of electronic devices that implement the needed cryptographic primitives has become a major issue. This paper starts by presenting a comprehensive overview of the existing attacks to cryptography implementations. Thereafter, the state-of-the-art on some of the most critical aspects of designing cryptographic co-processors are presented. This analysis starts by considering the design of asymmetrical and symmetrical cryptographic primitives, followed by the discussion on the design and online testing of True Random Number Generation. To conclude, techniques for the detection of Hardware Trojans are also discussed},
	keywords = {asymmetrical cryptographic primitives, cryptography, hardware Trojan detection techniques},
	issn = {0271-4302 },
	doi = {10.1109/ISCAS.2015.7169070},
	url = {http://dx.doi.org/10.1109/ISCAS.2015.7169070},
	author = {Regazzoni, Francesco and Graves, Ricardo and Di Natale, Giorgio and Batina, Lejla and Bhasin, Shivam and Ege, Baris and Fournaris, Apostolos P. and Mentens, Nele and Picek, Stjepan and Rozic, Vladimir and Sklavos, Nicolas and Yang, Bohan}
}
@article {18058,
	title = {A Combined Design-Time/Test-Time Study of the Vulnerability of Sub-Threshold Devices to Low Voltage Fault Attacks},
	journal = {IEEE Transactions on Emerging Topics in Computing},
	volume = {PP},
	issue = {99},
	year = {2014},
	month = {04/2014},
	abstract = {The continuous scaling of VLSI technology and the possibility to run circuits in subthreshold voltage range make it possible to implement standard cryptographic primitives within the very limited circuit and power budget of RFID devices. However, such cryptographic implementations raise concerns regarding their vulnerability to both active and passive side-channel attacks. In particular, when focusing on RFID targeted designs, it is important to evaluate their resistance against low cost physical attacks. A low cost fault injection attack can be mounted, for example, by lowering the supply voltage of the chip with the goal of causing setup time violations. In this paper, we provide an in-depth characterization of a chip implementation of the AES cipher. The chip has been designed using a 65nm low power standard cell library and operates in a subthreshold voltage range. We first show that it is possible to inject faults (through lowering the supply voltage) compliant with the fault models required to perform attacks against the AES cipher. We then investigate the possibility of predicting, at design time, which parts of the chip are more likely to be sensitive to such fault injection attacks and produce the desirable (from the point of view of the attacker) faulty behavior. Identifying such sensitive logic signals allows us to suggest to the designer a tailored countermeasure strategy for thwarting these attacks, with a minimal impact on the circuit{\textquoteright}s performance.},
	issn = {2168-6750},
	doi = {10.1109/TETC.2014.2316509},
	author = {Barenghi, Alessandro and Hocquet, C{\'e}dric and Bol, David and Standaert, Fran{\c c}ois-Xavier and Regazzoni, Francesco and Koren, Israel}
}
@conference {18069,
	title = {Comparison of Two Cameras based on Single Photon Avalanche Diodes (SPADS) for Fluorescence Lifetime Imaging Application with Picosecond Resolution},
	booktitle = {International Image Sensor Workshop (IISW)},
	year = {2013},
	month = {June},
	address = {Snowbird Resort, Utah, USA},
	author = {Powolny, Fran{\c c}ois and Burri, Samuel and Bruschini, Claudio and Michalet, Xavier and Regazzoni, Francesco and Charbon, Edoardo}
}
@conference {18075,
	title = {Compact Implementation and Performance Evaluation of Block Ciphers in ATtiny Devices},
	booktitle = {Progress in Cryptology - Africacrypt},
	year = {2012},
	month = {July},
	address = {Ifrance, Morocco},
	author = {Eisenbarth, Thomas and Gong, Zheng and Gneysu, Tim and Heyse, Stefan and Indesteege, Sebastiaan and Kerckhof, St{\'e}phanie and Koeune, Francois and Nad, Tomislav and Plos, Thomas and Regazzoni, Francesco and Standaert, Fran{\c c}ois-Xavier and Oldenzeel, Loic Van Oldene}
}
@conference {18073,
	title = {Compact Implementation and Performance Evaluation of Hash Functions in ATtiny Devices},
	booktitle = {11th Smart Card Research and Advanced Application Conference (CARDIS)},
	year = {2012},
	month = {November},
	address = {Graz, Austria},
	author = {Balasch, Josep and Ege, Baris and Eisenbarth, Thomas and Grard, Benot and Gong, Zheng and Gneysu, Tim and Heyse, Stefan and Kerckhof, St{\'e}phanie and Koeune, Francois and Plos, Thomas and Poppelmann, Thomas and Regazzoni, Francesco and Standaert, Fran{\c c}ois-Xavier and Van Assche, Gilles and Van Keer, Ronny and Oldenzeel, Loic Van Oldene and von Maurich, Ingo}
}
@conference {18084,
	title = {The Certicom Challenges ECC2-X},
	booktitle = {Workshop on Special Purpose Hardware for Attacking Cryptographic Systems (SHARCS)},
	year = {2009},
	month = {September},
	address = {Lausanne, Switzerland},
	author = {Bailey, Daniel V. and Baldwin, Brian and Batina, Lejla and Bernstein, Daniel J. and Birkner, Peter and Bos, Joppe W. and van Damme, Gauthier and de Meulenaer, Giacomo and Fan, Junfeng and Gurkaynak, Frank and G{\"u}neys, Tim and Kleinjung, Thorsten and Lange, Tanja and Mentens, Nele and Paar, Christof and Regazzoni, Francesco and Schwabe, Peter and Uhsadel, Leif}
}
@conference {89.ReEiBrIeKo,
	title = {Can knowledge regarding the presence of countermeasures against fault attacks simplify power attacks on cryptographic devices?},
	booktitle = {Proceedings of 23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS 08)},
	year = {2008},
	month = {October 1-3},
	abstract = {Side-channel attacks are nowadays a serious concern when implementing cryptographic algorithms. Powerful ways for gaining information about the secret key as well as various countermeasures against such attacks have been recently developed. Although it is well known that such attacks can exploit information leaked from different sources, most prior works have only addressed the problem of protecting a cryptographic device against a single type of attack. Consequently, there is very little knowledge on how a scheme for protecting a device against one type of side-channel attack may affect its vulnerability to other types of side-channel attacks. In this paper we focus on devices that include protection against fault injection attacks (using different error detection schemes) and explore whether the presence of such fault detection circuits affects the resistance against attacks based on power analysis. Using the AES S-Box as an example, we performed attacks on the unprotected implementation as well as modified implementations with parity check circuits or residue check circuits (mod3 and mod7). In particular, we focus on the question whether the knowledge of the presence of error detection circuitry in the cryptographic device can help an attacker who attempts to mount a power attack on the device. Our results show that the presence of error detection circuitry helps the attacker even if he is unaware of this circuitry, and that the benefit to the attacker increases with the number of check bits used for the purpose of error detection.},
	author = {Regazzoni, Francesco and Eisenbarth, Thomas and Breveglieri, Luca and Ienne, Paolo and Koren, Israel}
}
