@Patent {18589,
	title = {Reconfigurable Logic Circuit},
	number = {GB1719355.8},
	year = {Submitted},
	month = {11/2017},
	type = {UK},
	author = {Mentens, Nele and Charbon, Edoardo and Regazzoni, Francesco}
}
@conference {18575,
	title = {Rethinking Secure FPGAs: TowardsCryptography-friendly Configurable Cell Architecture and its Automated Design Flow},
	booktitle = {Proceedings of FCCM},
	year = {2018},
	month = {05/2018},
	author = {Mentens, Nele and Charbon, Edoardo and Regazzoni, Francesco}
}
@inbook {18521,
	title = {Runtime Classification of Mobile Malware for Resource-constrained Devices},
	booktitle = {Lecture Notes in Communications in Computer and Information Science},
	volume = {764},
	year = {2017},
	pages = {195-215},
	publisher = { Springer International Publishing AG},
	organization = { Springer International Publishing AG},
	doi = {https://doi.org/10.1007/978-3-319-67876-4_10},
	author = {Milosevic, Jelena and Malek, Miroslaw and Ferrante, Alberto}
}
@conference {18484,
	title = {Round gating for low energy block ciphers},
	booktitle = {2016 IEEE International Symposium on Hardware Oriented Security and Trust, HOST},
	year = {2016},
	month = {05/2016},
	pages = {55-60},
	publisher = {IEEE Computer Society},
	organization = {IEEE Computer Society},
	address = {McLean, VA, USA},
	abstract = {Pushed by the pervasive diffusion of devices operated by battery or by the energy harvested, energy has become one of the most important parameter to be optimized for embedded systems. Particularly relevant would be to optimize the energy consumption of security primitives. In this paper we explore design techniques for implementing block ciphers in a low energy fashion. We concentrate on round based implementation and we discuss how gating, applied at round level can affect and improve the energy consumption of the most common lightweight block cipher currently used in the internet of things. Additionally, we discuss how to needed gating wave can be generated. Experimental results show that our technique is able to reduce the energy consumption in most block ciphers by over 60\% while incurring only a minimal overhead in hardware},
	keywords = {algorithm design and analysis, ciphers, clocks, computer architecture, energy consumption},
	isbn = {978-1-4673-8826-9},
	doi = {10.1109/HST.2016.7495556},
	url = {http://dx.doi.org/10.1109/HST.2016.7495556},
	author = {Banik, Subhadeep and Bogdanov, Andrey and Regazzoni, Francesco and Isobe, Takanori and Hiwatari, Harunaga and Akishita, Toru}
}
@conference {18206,
	title = {A Resource-optimized Approach to Efficient Early Detection of Mobile Malware},
	booktitle = {3rd International Workshop on Security of Mobile Applications - IWSMA 2014},
	year = {2014},
	month = {09/2014},
	address = {Fribourg, Switzerland},
	author = {Milosevic, Jelena and Dittrich, Andreas and Ferrante, Alberto and Malek, Miroslaw}
}
@conference {18232,
	title = {Responsiveness of Service Discovery in Wireless Mesh Networks},
	booktitle = {20th Pacific Rim International Symposium on Dependable Computing (PRDC)},
	year = {2014},
	month = {11/2014},
	publisher = {IEEE Computer Society},
	organization = {IEEE Computer Society},
	address = {Singapore},
	abstract = {Service Discovery (SD) is an integral part of service networks. Before a service can be used, it needs to be discovered successfully. Comprehensive service dependability analysis thus needs to include the SD process. As a time-critical operation, an important property of SD is responsiveness: The probability of successful discovery within a deadline, even in the presence of faults. This is especially true for dynamic networks with complex fault behavior such as wireless networks. This work evaluates the responsiveness of decentralized SD in wireless mesh networks. For this reason, the experiment framework ExCovery has been employed, which provides a unified description, execution, measurement and storage of experiments. ExCovery runs on the Distributed Embedded System (DES) wireless testbed at Freie Universit{\"a}t Berlin. We present and discuss the results of the experiments and show how responsiveness is affected by the position and number of requester and providers as well as the load in the network. The results clearly demonstrate that in all but the most favorable conditions, the configurations of current SD protocols struggle to achieve a high responsiveness.},
	keywords = {Experiments, Responsiveness, Service Discovery, Wireless mesh networks, Zeroconf},
	doi = {10.1109/PRDC.2014.38},
	url = {http://andreas-dittrich.eu/2014/06/prdc2014},
	author = {Dittrich, Andreas and Herrera, Daniel Solis and Coto, Pablo and Malek, Miroslaw}
}
@conference {18227,
	title = {Risk Assessment of Atrial Fibrillation: a Failure Prediction Approach},
	booktitle = {41st Computing in Cardiology Conference (CinC)},
	year = {2014},
	month = {09/2014},
	publisher = {IEEE Computer Society},
	organization = {IEEE Computer Society},
	address = {Cambridge, MA, USA},
	abstract = {We present a methodology for identifying patients who have experienced Paroxysmal Atrial Fibrillation (PAF) among a given subjects population. Our work is intended as an initial step towards the design of an unobtrusive system for concurrent detection and monitoring of chronic cardiac conditions.

Our methodology comprises two stages: off-line training and on-line analysis. During training the most significant features are selected using machine-learning methods, without relying on a manual selection based on previous knowledge. Analysis is based on two phases: feature extraction and detection of PAF patients. Light-weight algorithms are employed in the feature extraction phase, allowing the on-line implementation of this step on wearable and resource-constrained sensor nodes. The detection phase employs techniques borrowed from the field of failure prediction. While these algorithms have found extensive applications in diverse scenarios, their application to automated cardiac analysis has not been sufficiently investigated.

Obtained results, in terms of performance, are comparable to similar efforts in the field. Nonetheless, the proposed method employs computationally simpler and more efficient algorithms, which are compatible with the computational constraints of state-of-the-art body sensor nodes.},
	url = {http://andreas-dittrich.eu/2014/06/risk-assessment-of-atrial-fibrillation-a-failure-prediction-approach},
	author = {Milosevic, Jelena and Dittrich, Andreas and Ferrante, Alberto and Malek, Miroslaw and Rojas Quiros, Camilo and Braojos, Rub{\'e}n and Ansaloni, Giovanni and Atienza, David}
}
@conference {18090,
	title = {Run-time Optimization of a Dynamically Reconfigurable Embedded System Through Performance Prediction},
	booktitle = {23rd International Conference on Field Programmable Logic and Applications (FPL)},
	year = {2013},
	month = {09/2013},
	publisher = {IEEE},
	organization = {IEEE},
	address = {Porto, Portugal},
	doi = {10.1109/FPL.2013.6645523},
	author = {Mariani, Giovanni and Sima, Vlad-Mihai and Palermo, Gianluca and Zaccaria, Vittorio and Marchiori, Giacomo and Silvano, Cristina and Bertels, Koen}
}
@inbook {142.PaSiZaRiKaTuMa.2011,
	title = {Response Surface Modeling for Embedded System Design Space Exploration},
	booktitle = {Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach},
	year = {2011},
	publisher = {Springer},
	organization = {Springer},
	address = {New York, USA},
	abstract = {A typical design space exploration flow involves an event-based simulator in the loop, often leading to an actual evaluation time that can exceed practical limits for realistic applications. Chip multi-processor architectures further exacerbate this problem given that the actual simulation speed decreases by increasing the number of cores of the chip. Traditional design space exploration lacks of efficient techniques that reduce the number of architectural alternatives to be analyzed. In this chapter, we introduce a set of statistical and machine learning techniques that can be used to predict system level metrics by using closed-form analytical expressions instead of lengthy simulations; the latter are called Response Surface Models (RSM). The principle of RSM is to exploit a set of simulations generated by one or more Design of Experiments strategies to build a surrogate model to predict the system-level metrics. The response model has the same input and output features of the original simulation based model but offers significant speed-up by leveraging analytical, closed-form functions which are tuned during model training. The techniques presented in this chapter can be used to improve the performance of traditional design space exploration algorithms such as those presented in Chap. 3.},
	author = {Palermo, Gianluca and Silvano, Cristina and Zaccaria, Vittorio and Rigoni, Enrico and Kavka, Carlos and Turco, Alessandro and Mariani, Giovanni}
}
@conference {116.TuRePaFeSc10,
	title = {A Reconfigurable Multiprocessor Architecture for a Reliable Face Recognition Implementation},
	booktitle = {Proceedings of Design, Automation and Test in Europe (DATE) Conference},
	year = {2010},
	month = {March},
	address = {Dresden, Germany},
	abstract = {Face Recognition techniques are solutions used to quickly screen a huge number of persons without being intrusive in open environments or to substitute id cards in companies or research institutes. There are several reasons that require to systems implementing these techniques to be reliable. This paper presents the design of a reliable face recognition system implemented on Field Programmable Gate Array (FPGA). The proposed implementation uses the concepts of multiprocessor architecture, parallel software and dynamic reconfiguration to satisfy the requirement of a reliable system. The target multiprocessor architecture is extended to support the dynamic reconfiguration of the processing unit to provide reliability to processors fault. The experimental results show that, due to the multiprocessor architecture, the parallel face recognition algorithm can achieve a speed up of 63\% with respect to the sequential version. Results regarding the overhead in maintaining a reliable architecture are also shown},
	author = {Tumeo, Antonino and Regazzoni, Francesco and Palermo, Gianluca and Ferrandi, Fabrizio and Sciuto, Donatella}
}
@conference {104.UpCaMaMaPo09,
	title = {Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering},
	booktitle = {Proceedings of the 19th international workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2009)},
	year = {2009},
	month = {September 9-11},
	address = {Delft, The Netherlands},
	abstract = {Clock-gating and power-gating have proven to be two of the most effective techniques for reducing dynamic and leakage power, respectively, in VLSI CMOS circuits. Most commercial synthesis tools do support such techniques individually, but their combined implementation is not available, since some open issues in terms of power/timing overhead associated to the control logic required for the integration are not yet solved. Moving from some recent work targeting clock-gating/power-gating integration, in this paper we present a solution for reducing the timing overhead that may occur when the integration is performed. In particular, we introduce a new, multilevel partitioning heuristic that increases the efficiency of the clustering phase, one of the key steps of our methodology. The results demonstrate the effectiveness of our solution; in fact, power-delay product and timing overhead of the circuits synthesized using the new clustering algorithm improve by 33\% and 24\%, respectively.},
	author = {Upasani, Gaurang and Calimera, Andrea and Macii, Alberto and Macii, Enrico and Poncino, Massimo}
}
@conference {107.TaFe209,
	title = {Run-time Selection of Security Algorithms For Networked Devices},
	booktitle = {5th ACM International Symposium on QoS and Security for Wireless and Mobile Networks},
	year = {2009},
	address = {Tenerife, Canary Islands, Spain},
	abstract = {One of the most important challenges that need to be currently faced in securing resource-constrained embedded systems is optimizing the trade-off between resources used (energy consumption and computational capabilities required) and security requirements for cryptographic algorithms: any adopted security solutions should guarantee an adequate level of protection, yet respecting constraints on computational resources and consumed power. These constraints are given by the kind of system considered and by the foreseen applications. In this paper, a generic, efficient, and energy-aware mechanism is proposed to face the problem of determining a correct trade off between security requirements and resources consumed. The solution proposed relies on Analytic Hierarchy Process (AHP) to define priorities among different requirements and to compare different security solutions. A knapsack problem is formulated to select the most relevant algorithms based on their utility and on available resources.},
	keywords = {adaptive systems, algorithm selection, protocol, quality of service (QoS), security},
	doi = {http://dx.doi.org/10.1145/1641944.1641963},
	author = {Taddeo, Antonio Vincenzo and Ferrante, Alberto}
}
@conference {73.OtReLa07,
	title = {Rapid Creation of Application Models from Bandwidth Aware Core Graphs},
	booktitle = {Proceedings of: IP Based SoC Design 2007},
	year = {2007},
	month = {December 5-6},
	address = {Grenoble, France},
	abstract = {We present a methodology that allows rapid creation of application models from bandwidth aware core graphs that are available in the literature for a wide range of applications and we discuss their applicability to the rapid exploration of multiple Networks on Chip (NoCs) layout organizations. In a bandwidth aware core graph, each node represents a core and the numbers on the edges represent the bandwidth requirements between cores. We describe core graphs in a UML object model diagram and we then have an automatic code generation tool which produces a SystemC description whose behaviour results in a packet generation on every output connection that respects the bandwidth requirements specified in the core graph. We can then rapidly derive a NoC mapping in which a specific floorplan of the cores can be evaluated and compared with alternate floorplan options for rapid design space exploration.},
	keywords = {network-on-chip (NoC), rapid prototyping},
	author = {Otero, Jo{\~a}o and Regazzoni, Francesco and Lajolo, Marcello}
}
@conference {70.PaBoSa07,
	title = {ReCPU: a Parallel and Pipelined Architecture for Regular Expression Matching},
	booktitle = {Proceedings of 15th Annual IFIP International Conference on Very Large Scale Integration {(IFIP-VLSI 07)},(best paper award)},
	year = {2007},
	month = {October 15-17},
	address = {Atlanta, Georgia, USA},
	abstract = {Text pattern matching is one of the main and most computation intensive parts of systems such as Network Intrusion Detection Systems and DNA Sequencing Matching. Soft- ware solutions to this are available but often they do not satisfy the requirements in terms of performance. This pa- per presents a new hardware approach for regular expression matching: ReCPU. The proposed solution is a parallel and pipelined architecture able to deal with the common regular expression semantics. This implementation based on several parallel units achieves a throughput of more than one char- acter per clock cycle (maximum performance of state of the art solutions) requiring just O(n) memory locations (where n is the length of the regular expression). Performance has been evaluated synthesizing the VHDL description. Area and time constraints have been analyzed. Experimental re- sults are obtained simulating the architecture.},
	doi = {http://dx.doi.org/10.1109/VLSISOC.2007.4402466},
	author = {Paolieri, Marco and Bonesana, Ivano and Santambrogio, Marco Domenico}
}
@conference {62.SaTa07,
	title = {Remote Cooperation on Project-centred Learning: a Working Implemented Solution in Academia},
	booktitle = {COOPER Workshop in conjunction with EC-TEL07 Conference},
	year = {2007},
	month = {September 17},
	abstract = {The paper aims at illustrating the original technical solution provided within an academic institute in order to manage teaching activities, encompassing the coordination of project-centred learning processes that run in parallel with the formal theoretical courses. Unlike the planning of the academic teaching that can be scheduled year by year, the development of a project cannot be defined over a long period, but it requires frequent report reviews and updating by the different actors involved in the project. From this consideration, and due to the peculiar context of the ALaRI institute, it was clear the necessity to manage asynchronous and synchronous communications occurring during the ongoing project, facilitating the team members{\textquoteright} remote interactions and cooperation. The provided solution within the EU COOPER project is the answer to more and more common scenarios of use, reflecting not only university requirements, but also industrial needs based on the cooperative teamwork among persons geographically dispersed and with heterogeneous competences.},
	keywords = {case study, project-centred learning, remote cooperation},
	author = {Salvioni, Carola and Taddeo, Antonio Vincenzo}
}
@conference {69.BoIoNeTaTo07,
	title = {Role Based Access Control for the interaction with Search Engines},
	booktitle = {COOPER Workshop in conjunction with EC-TEL07 Conference},
	year = {2007},
	month = {September 17},
	abstract = {Search engine-based features are a basic interaction mean for users to find information inside a Web-based Learning Management Systems (LMS); nonetheless, traditional solutions lack in mechanisms for access rights management for data contained in search engines{\textquoteright} indexes. This paper explores the integration of a Role Based Access Control (RBAC) mechanism for the interaction with a search engine in a Web-based LMS. We first outline a reference conceptual model for the design of Web-based LMSs exploiting RBAC by means of WebML, a visual modeling language for the high-level specification of data-intensive Web applications. Then, we propose a model-driven approach for the definition of a RBAC-driven interaction between users and search engines, extending WebML with new modeling primitives and outlining significative modeling patterns for the specification of the visibility and action access control levels.},
	keywords = {access control modeling, index modeling, search engine design, web engineering},
	author = {Bozzon, Alessandro and Iofciu, Tereza and Nejdl, Wolfgang and Taddeo, Antonio Vincenzo and Tonnies, Sascha}
}
