@article {18566,
	title = {Impact of Failure Prediction on Availability: Modeling and Comparative Analysis of Predictive and Reactive Methods},
	journal = {IEEE Transactions on Dependable and Secure Computing},
	year = {2018},
	pages = {1-1},
	abstract = {Predicting failures and acting proactively have a potential to improve availability as a correct prediction and a successful mitigation may bring a reward resulting in decrease of downtime and availability improvement. But, conversely, each incorrect prediction may introduce additional downtime (penalty). Therefore, depending on the quality of prediction and the system parameters, predictive fault-tolerance methods may improve or may degrade availability in comparison to the reactive ones. We first derive taxonomies of fault-tolerant techniques and policies to differentiate between reactive and proactive policies that are further classified as systematic and predictive. To evaluate whether a predictive policy improves availability or not, we derive an analytical model for availability quantification. We use Markov chains to extend steady-state availability equation to include: precision and recall, penalty and reward, mitigation success probability and potential failure rate increase due to the prediction load. We also derive A-measure to optimize failure prediction for increasing availability. In our conclusion, precision and recall have comparable impact on availability as changing MTTF and MTTR. To validate the model we also simulate and analyze availability of a virtualized server with exponential distribution of failure and repair rates.},
	keywords = {Analytical models, availability, Computational modeling, failure, fault tolerance, Fault tolerant systems, Mathematical model, modeling, Optimization, prediction, predictive, Predictive models, proactive, Servers},
	issn = {1545-5971},
	doi = {10.1109/TDSC.2018.2806448},
	author = {Kaitovi{\'c}, Igor and Malek, Miroslaw}
}
@conference {18574,
	title = {Inverse Gating for Low Energy Block Ciphers},
	booktitle = {Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust (HOST)},
	year = {2018},
	author = {Banik, Subhadeep and Bogdanov, Andrey and Isobe, Takanori and Hiwatari, Harunaga and Akishita, Toru and Regazzoni, Francesco}
}
@article {18508,
	title = {Investigating echo state networks dynamics by means of recurrence analysis},
	journal = {IEEE Transactions on Neural Networks and Learning Systems},
	volume = {29},
	year = {2018},
	month = {02/2018},
	pages = { 427 - 439},
	abstract = {In this paper, we elaborate over the well-known
interpretability issue in echo state networks. The idea is to investigate
the dynamics of reservoir neurons with time-series analysis
techniques taken from research on complex systems. Notably, we
analyze time-series of neuron activations with Recurrence Plots
(RPs) and Recurrence Quantification Analysis (RQA), which
permit to visualize and characterize high-dimensional dynamical
systems. We show that this approach is useful in a number of
ways. First, the two-dimensional representation offered by RPs
provides a way for visualizing the high-dimensional dynamics of
a reservoir. Our results suggest that, if the network is stable,
reservoir and input denote similar line patterns in the respective
RPs. Conversely, the more unstable the ESN, the more the RP
of the reservoir presents instability patterns. As a second result,
we show that the Lmax measure is highly correlated with the
well-established maximal local Lyapunov exponent. This suggests
that complexity measures based on RP diagonal lines distribution
provide a valuable tool to quantify the degree of network stability.
Finally, our analysis shows that all RQA measures fluctuate on
the proximity of the so-called edge of stability, where an ESN
typically achieves maximum computational capability. We verify
that the determination of the edge of stability provided by such
RQA measures is more accurate than two well-known criteria
based on the Jacobian matrix of the reservoir. Therefore, we
claim that RPs and RQA-based analyses can be used as valuable
tools to design an effective network given a specific problem.},
	doi = {10.1109/TNNLS.2016.2630802},
	author = {Bianchi, Filippo Maria and Livi, Lorenzo and Alippi, Cesare}
}
@article {18535,
	title = {An Incremental Change Detection Test Based on Density Difference Estimation},
	journal = {IEEE Transactions on Systems, Man, and Cybernetics: Systems},
	volume = {47},
	year = {2017},
	month = {Oct},
	pages = {2714-2726},
	keywords = {Big data framework, Change detection, change detection method, density difference estimation, Estimation, false positive rates, Feature extraction, Histograms, incremental change detection test, incremental computing, incremental least squares density difference change detection method (LSDD-Inc), Internet of Things, Kernel, least squares approximations, least squares density difference, linear combination, LSDD, LSDD values, nonoverlapping data windows, probability, Probability density function, probability density function (pdf)-free, probability density functions, process continuous data streams, Training},
	issn = {2168-2216},
	doi = {10.1109/TSMC.2017.2682502},
	author = {Bu, Li and Zhao, Dongbin and Alippi, Cesare}
}
@article {18561,
	title = {An Investigation of Sources of Randomness Within Discrete Gaussian Sampling},
	journal = {IACR Cryptology ePrint Archive},
	volume = {2017},
	year = {2017},
	pages = {298},
	author = {Brannigan, S{\'e}amus and Smyth, Neil and Oder, Tobias and Valencia, Felipe and O{\textquoteright}Sullivan, Elizabeth and G{\"u}neysu, Tim and Regazzoni, Francesco}
}
@conference {18513,
	title = {An improved Hilbert-Huang Transform for non-linear and time-variant signals},
	booktitle = {26th Italian Workshop on Neural Networks (WIRN 2016)},
	year = {2016},
	month = {05/2016},
	pages = {1-8},
	address = {Vietri sul Mare, Salerno, Italy},
	abstract = {Learning in non-stationary/evolving environments requires methods able to process and deal with non-stationary streams. In this paper we propose a novel algorithm providing a time-frequency decomposition
of time-variant signals. Outcoming signals can be used to identify anomalous events/patterns or extract features associated with the time variance of the signal, precious information for any consequent learning
action. The paper extends the Hilbert-Huang Transform notoriously used to deal with time-variant signals by introducing (i) a new Empirical Mode Decomposition that identies the number of frequency modes of
the signal and (ii) an extension of the Hilbert Transform that eliminates negative frequency-values in the time-frequency spectrum. The effectiveness of the proposed Transform has been tested on both synthetic and real time-variant signals acquired by a real-world intelligent system for landslide monitoring.
},
	author = {Alippi, Cesare and Wen, Qi and Roveri, Manuel}
}
@conference {18486,
	title = {Instruction Set Extensions for secure applications},
	booktitle = {Design, Automation Test in Europe Conference DATE 2016},
	year = {2016},
	month = {03/2016},
	pages = {1529-1534},
	publisher = {IEEE},
	organization = {IEEE},
	address = {Dresden, Germany},
	abstract = {The main goal of this paper is to expose the community to past achievements and future possible uses of Instruction Set Extension (ISE) in security applications. Processor customization has proven to be an effective way for achieving high performance with limited area and energy overhead for several applications, ranging from signal processing to graphical computation. Concerning cryptographic algorithms, a large body of work exists on speeding up block ciphers and asymmetric cryptography with specific ISEs. These algorithms often mix non-standard operations with regular ones, thus representing an ideal target for being accelerated with dedicated instructions. Tools supporting automatic generations of ISEs demonstrated to be useful for algorithm exploration, while secure instructions can increase the robustness against side channels attacks of software routines. In this paper, we discuss how processor customization and the relative tool chains can be used by designers to address security problems and we highlight possible research directions},
	keywords = {asymmetric cryptography, block ciphers, cryptographic algorithms protection, instruction set, security applications},
	isbn = {978-3-9815-3707-9},
	url = {http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=7459556},
	author = {Regazzoni, Francesco and Ienne, Paolo}
}
@inbook {18062,
	title = {Interaction between Fault Attack Countermeasures and the Resistance against Power Analysis Attacks},
	booktitle = {Fault Analysis in Cryptography},
	series = {Information Security and Cryptography Series, Springer},
	year = {2012},
	pages = {257-272},
	publisher = {Springer Berlin Heidelberg},
	organization = {Springer Berlin Heidelberg},
	abstract = {Most of the countermeasures against fault attacks on cryptographic systems that have been developed so far are based on the addition of information redundancy. While these countermeasures have been evaluated with respect to their cost (implementation overhead) and efficiency (fault coverage), little attention has been devoted to the question of the impact their use has on the effectiveness of other types of side-channel attacks, in particular, power analysis attacks. This chapter presents an experimental study whose goal is to determine whether the added information redundancy can increase the vulnerability of a cryptographic circuit to power analysis attacks.},
	isbn = {978-3-642-29656-7},
	doi = {10.1007/978-3-642-29656-7_15},
	author = {Regazzoni, Francesco and Breveglieri, Luca and Ienne, Paolo and Koren, Israel},
	editor = {Joye, Marc and Tunstall, Michael}
}
@conference {117.MaAvVaYkPaSiZa10,
	title = {An industrial design space exploration framework for supporting run-time resource management on multi-core systems},
	booktitle = {Proceedings of Design, Automation and Test in Europe (DATE) Conference},
	year = {2010},
	month = {March},
	address = {Dresden, Germany},
	abstract = {Current multi-core design methodologies are facing increasing unpredictability in terms of quality due to the actual diversity of the workloads that characterize the deployment scenario. To this end, these systems expose a set of dynamic parameters which can be tuned at run-time to achieve a specified Quality of Service (QoS) in terms of performance. A run-time manager operating system module is in charge of matching the specified QoS with the available platform resources by manipulating the overall degree of task-level parallelism of each application as well as the frequency of operation of each of the system cores. In this paper, we introduce a design space exploration framework for enabling and supporting enhanced resource management through software re-configuration on an industrial multicore platform. From one side, the framework operates at design time to identify a set of promising operating points which represent the optimal trade-off in terms of the target power consumption and performance. The operating points are used after the system has been deployed to support an enhanced resource management policy. This is done by a light-weight resource management layer which filters and selects the optimal parallelism of each application and operating frequency of each core to achieve the QoS constraints imposed by the external world and/or the user. We show how the proposed design-time and run-time techniques can be used to optimally manage the resources of a multiple-stream MPEG4 encoding chip dedicated to automotive cognitive safety tasks.},
	author = {Mariani, Giovanni and Avasare, Prabhat and Vanmeerbeeck, Geert and Ykman-Couvreur, Chantal and Palermo, Gianluca and Silvano, Cristina and Zaccaria, Vittorio}
}
@inbook {17765,
	title = {IPSec Database Query Acceleration},
	booktitle = {E-business and Telecommunications},
	series = {Communications in Computer and Information Science},
	volume = {23},
	year = {2009},
	pages = {188-200},
	publisher = {Springer Berlin Heidelberg},
	organization = {Springer Berlin Heidelberg},
	isbn = {978-3-540-88652-5},
	doi = {10.1007/978-3-540-88653-2_14},
	url = {http://dx.doi.org/10.1007/978-3-540-88653-2_14},
	author = {Ferrante, Alberto and Chandra, Satish and Piuri, Vincenzo},
	editor = {Filipe, Joaquim and Obaidat, Mohammad}
}
@conference {76.FiLuPa08,
	title = {Implementation of a Reconfigurable Data Protection Module for NoC-based MPSoCs},
	booktitle = {Proceedings of the 21st IPDPS 2007 Reconfigurable Architecture Workshop (RAW), 21th IEEE International Parallel and Distributed Processing Symposium},
	year = {2008},
	month = {April},
	address = {Miami, USA/FL},
	abstract = {Security issues are emerging to be a basic concern in modern SoC development. Since in the field of on-chip interconnections the security problem continues to remain mostly an unexplored topic, this paper proposes a novel technique for data protection that uses the communication subsystem as basis. The proposed architecture works as a firewall managing the memory accesses on the basis of a lookup table containing the access rights. This module, called Data Protection Unit (DPU), has been designed for MPSoC architectures and integrated in the Network Interfaces near the shared memory. We implement the DPU inside an MPSoC architecture on FPGA and we add features to the module to be aware of dynamic reconfiguration of the system software. Starting from a general overview of our design down to components structure, we introduce the place and the role of the DPU module inside the system for a reconfigurable secure implementation of a MPSoC on FPGA. The description of the DPU concept, its implementation, and integration into the system are described in detail. Finally, the architecture is fully implemented on FPGA and tested on a Xilinx Virtex-II Pro board.},
	keywords = {data protection, FPGA, multiprocessor system-on-chip (MPSoC), network-on-chip (NoC), reconfigurable systems, security},
	doi = {http://dx.doi.org/10.1109/IPDPS.2008.4536514},
	author = {Fiorin, Leandro and Lukovi{\'c}, Slobodan and Palermo, Gianluca}
}
@misc {52.Prevo2007MISC,
	title = {Introduction to SysML},
	year = {2007},
	month = {April 20},
	abstract = {The Systems Modeling Language (SysML) is a general-purpose graphical modeling language for specifying, analyzing, designing, and verifying complex systems that may include hardware, software, information, personnel, procedures, and facilities. It is a response to the UML for Systems Engineering RFP developed by OMG, INCOSE, and the ISO AP233 workgroup. In this presentation I will provide an overview of SysML in particular by showing the diagrams that describe the four pillars of SysML: Requirements, Behavior, Structure, and Parametrics. The diagrams will be shown by means of a simple case study in the field of Wireless Sensor Network.},
	keywords = {embedded systems, systems modeling language (SysML), wireless sensor networks},
	author = {Prevostini, Mauro}
}
@conference {27.RegLaj2004,
	title = {Interface Synthesis in Multiprocessing Systems-on-Chips},
	booktitle = {IP Based SoC Design 2004},
	year = {2004},
	month = {December},
	address = {Grenoble},
	abstract = {Although Moore{\textquoteright}s Law, in principle, enables a huge number of components to be integrated into a single chip, design methods that will allow system architects to put the components together to achieve cost, power and time-to-market targets are severely lacking. System-level design and optimization techniques can significantly reduce the design gap by providing solutions that achieve correct-by-construction approach rather than the correct-by-iteration approach. This paper presents a programmatic interface generation tool for automating the generation of the hardware/software interfaces in the context of multi-processor Systems-On-Chips. The solutions that we present are of crucial importance in a platform based design environment for building a flexible system with reusable IPs and CPU cores.},
	keywords = {HW/SW co-design, system-on-chip (SoC)},
	author = {Regazzoni, Francesco and Lajolo, Marcello}
}
@conference {12.MiMaMaPreKoBa2003,
	title = {Intelligent, low-power and low-cost measurement system for energy consumption},
	booktitle = {VECIMS 2003},
	year = {2003},
	month = {July 27-29},
	pages = {125-130},
	address = {Lugano},
	abstract = {In the area of utility measurement systems, there is increasing awareness to the importance of using intelligent and secure meter readers. The aim is not simply that of reducing operational costs; aspects such as availability of real-time determination of consumption (mainly in the case of energy meters, but potentially also for water consumption etc.) are relevant not only for actions such as real-time billing but also in view of an increasing environmental awareness leading to {\textquoteright}preferential{\textquoteright} billing in particular times of the day or of the week and requiring availability of fine-grained statistics. All these actions in turn involve the requirement of data integrity; when utilities other than power providers are considered, the device should be battery-powered (and very long battery life must be granted), so that low-power design becomes a further requirement while being permanently either in active or in standby mode; moreover, not being connected to the power network means that wireless connections for transmitting and receiving information must be taken into account. Finally, these devices should be made available to the general public and thus be low-cost ones. This paper describes how all the above constraints have been analyzed in the design of a wireless meter reading system.},
	keywords = {measurement systems, meter reading systems, power consumption},
	author = {Minosi, Antonio and Martinola, Aris and Mankan, Srinivas and Prevostini, Mauro and Kostadinov, Atanas Nikolov and Balzarini, Francesco}
}
@conference {4.BonaSaSciSiZaZa2002,
	title = {An Instruction-Level Methodology for Power Estimation and Optimization of Embedded VLIW cores},
	booktitle = {DATE 2002},
	year = {2002},
	month = {March 4-8},
	pages = {1128},
	address = {Paris},
	abstract = {The overall goal of this work is to define an instruction-level power macro-modeling and characterization methodology for VLIW embedded processor cores. The approach presented in this paper is a major extension of the work previously proposed in [1-3], targeting an instruction-level energy model to evaluate the energy consumption associated with a program execution on a pipelined VLIW core. Our first goal is the reduction of the complexity of the processor{\textquoteright}s energy model, without reducing the accuracy of the results. The second goal is to show how the energy model can be further simplified by introducing a methodology to automatically cluster the whole Instruction Set with respect to their average energy cost, in order to con verge to an highly effective design of experiments for the actual characterization task. The paper describes also the application of the proposed model to a real industrial VLIW core (the Lx Architecture developed by HP Labs and STMicroelectronics), to validate the effectiveness and accuracy of the proposed methodology.},
	doi = {http://dx.doi.org/10.1109/DATE.2002.998484},
	author = {Bona, Andrea and Sami, Mariagiovanna and Sciuto, Donatella and Silvano, Cristina and Zaccaria, Vittorio and Zafalon, Roberto}
}
