@conference {38.1110115,
	title = {Power/Performance Tradeoffs in Bluetooth Sensor Networks},
	booktitle = {HICSS {\textquoteright}06: Proceedings of the 39th Annual Hawaii International Conference on System Sciences},
	year = {2006},
	pages = {236.2},
	publisher = {IEEE Computer Society},
	organization = {IEEE Computer Society},
	address = {Washington, DC, USA},
	abstract = {Low power consumption is a critical issue in wireless sensor networks. Over the past few years, a considerable number of ad-hoc architectures and communication protocols have been proposed for sensor network nodes. If on one hand custom solutions carry the greatest power optimization potential, widespread communication standards guarantee interoperability and ease of connection with existing devices. In this paper we present a variable-granularity power model of Bluetooth, and apply it to variable-complexity optimization scenarios, to devise optimal power management policies. These policies, if backed by hardware implementations that are more power-aggressive than those available, could make the protocol fit for a wider range of sensor networks than it is today.},
	isbn = {0-7695-2507-5},
	doi = {http://dx.doi.org/10.1109/HICSS.2006.383},
	author = {Negri, Luca and Zanetti, Davide}
}
@conference {31.1070384,
	title = {Flexible Power Modeling for Wireless Systems: Power Modeling and Optimization of two Bluetooth Implementations},
	booktitle = {WOWMOM {\textquoteright}05: Proceedings of the Sixth IEEE International Symposium on a World of Wireless Mobile and Multimedia Networks (WoWMoM{\textquoteright}05)},
	year = {2005},
	pages = {408{\textendash}416},
	publisher = {IEEE Computer Society},
	organization = {IEEE Computer Society},
	address = {Washington, DC, USA},
	abstract = {A large number of embedded multimedia applications are characterized by high instruction-level parallelism (ILP) expecially in the most critical internal loop bodies. Very Large Instruction Word (VLIW) architectures Application Specific Instruction Set Processors (ASIP) are best suited to exploit such parallelism. Fast design space exploration and optimization of VLIW architecture to a specific application target is increasingly becoming the crucial factor to achieve higher efficiency designs in a relatively small amount of time. In this paper we propose an example of VLIW architecture application driven optimization using the VEX (VLIW Example) system. A typical image processing application, the Imaging Pipeline, has been chosen as an example.},
	isbn = {0-7695-2342-0-01},
	doi = {http://dx.doi.org/10.1109/WOWMOM.2005.46},
	author = {Negri, Luca and Sami, Mariagiovanna and Tran, Que Dung and Zanetti, Davide}
}
