@article {18058,
	title = {A Combined Design-Time/Test-Time Study of the Vulnerability of Sub-Threshold Devices to Low Voltage Fault Attacks},
	journal = {IEEE Transactions on Emerging Topics in Computing},
	volume = {PP},
	issue = {99},
	year = {2014},
	month = {04/2014},
	abstract = {The continuous scaling of VLSI technology and the possibility to run circuits in subthreshold voltage range make it possible to implement standard cryptographic primitives within the very limited circuit and power budget of RFID devices. However, such cryptographic implementations raise concerns regarding their vulnerability to both active and passive side-channel attacks. In particular, when focusing on RFID targeted designs, it is important to evaluate their resistance against low cost physical attacks. A low cost fault injection attack can be mounted, for example, by lowering the supply voltage of the chip with the goal of causing setup time violations. In this paper, we provide an in-depth characterization of a chip implementation of the AES cipher. The chip has been designed using a 65nm low power standard cell library and operates in a subthreshold voltage range. We first show that it is possible to inject faults (through lowering the supply voltage) compliant with the fault models required to perform attacks against the AES cipher. We then investigate the possibility of predicting, at design time, which parts of the chip are more likely to be sensitive to such fault injection attacks and produce the desirable (from the point of view of the attacker) faulty behavior. Identifying such sensitive logic signals allows us to suggest to the designer a tailored countermeasure strategy for thwarting these attacks, with a minimal impact on the circuit{\textquoteright}s performance.},
	issn = {2168-6750},
	doi = {10.1109/TETC.2014.2316509},
	author = {Barenghi, Alessandro and Hocquet, C{\'e}dric and Bol, David and Standaert, Fran{\c c}ois-Xavier and Regazzoni, Francesco and Koren, Israel}
}
@article {18061,
	title = {A Fast ULV Logic Synthesis Flow in Many-Vt CMOS Processes for Minimum Energy under Timing Constraints},
	journal = {IEEE Transactions on Circuits and Systems II},
	volume = {59},
	issue = {12},
	year = {2013},
	pages = {947-951},
	abstract = {Ultra-low-voltage (ULV) logic offers the opportunity to operate at the minimum-energy point (MEP) for applications with low-to-medium speed requirements. Unfortunately, the critical design constraint of achieving a reliable timing closure at the target frequency of the application becomes very complex in the wide design space of ULV including supply (Vdd) and threshold (Vt) voltage selection as well as netlist optimizations from the synthesis. In this paper, we propose a fast synthesis flow to accurately predict the Vdd/Vt MEP under strict timing constraints. Compared to an exhaustive search for the MEP under timing constraints based on numerous library recharacterizations and synthesis steps for all Vdd/Vt pairs, the proposed ULV flow dramatically speeds up the design process. Indeed, it requires a single library recharacterization and only three synthesis steps. Results obtained for several ITC{\textquoteright}99 benchmarks under a wide range of timing constraints from 0.1 to 30 MHz in 65-nm LP/GP CMOS demonstrate that the proposed flow has a less than 10\% energy penalty with respect to the absolute MEP computed with an exhaustive search and energy savings enhanced up to 2.4{\texttimes} compared to a conventional flow with Vdd scaling only.},
	issn = {1549-7747},
	doi = {10.1109/TCSII.2012.2231034},
	author = {Bol, David and Hocquet, C{\'e}dric and Regazzoni, Francesco}
}
@article {18491,
	title = {A Fast ULV Logic Synthesis Flow in Many-Vt CMOS Processes for Minimum Energy Under Timing Constraints},
	journal = {IEEE Transactions on Circuits and Systems II: Express Briefs  },
	volume = {59-II},
	issue = {12},
	year = {2012},
	month = {02/2012},
	pages = {947-951},
	type = {journal},
	chapter = {947},
	abstract = {Ultra-low-voltage (ULV) logic offers the opportunity to operate at the minimum-energy point (MEP) for applications with low-to-medium speed requirements. Unfortunately, the critical design constraint of achieving a reliable timing closure at the target frequency of the application becomes very complex in the wide design space of ULV including supply (Vdd) and threshold (Vt) voltage selection as well as netlist optimizations from the synthesis. In this paper, we propose a fast synthesis flow to accurately predict the Vdd/Vt MEP under strict timing constraints. Compared to an exhaustive search for the MEP under timing constraints based on numerous library recharacterizations and synthesis steps for all Vdd/Vt pairs, the proposed ULV flow dramatically speeds up the design process. Indeed, it requires a single library recharacterization and only three synthesis steps. Results obtained for several ITC{\textquoteright}99 benchmarks under a wide range of timing constraints from 0.1 to 30 MHz in 65-nm LP/GP CMOS demonstrate that the proposed flow has a less than 10\% energy penalty with respect to the absolute MEP computed with an exhaustive search and energy savings enhanced up to 2.4{\texttimes} compared to a conventional flow with Vdd scaling only},
	keywords = {circuit optimisation, CMOS logic circuits, fast ULV logic synthesis flow, Low power electronics},
	issn = {1549-7747},
	doi = {10.1109/TCSII.2012.2231034},
	url = {http://dx.doi.org/10.1109/TCSII.2012.2231034},
	author = {Bol, David and Hocquet, C{\'e}dric and Regazzoni, Francesco}
}
@conference {18079,
	title = {Exploring the Feasibility of Low Cost Fault Injection Attacks on Sub-Threshold Devices through an Example of a 65nm AES Implementation},
	booktitle = {7th Workshop on RFID Security and Privacy (RFIDSec)},
	year = {2011},
	month = {June},
	address = {Amherst, Massachussets, USA},
	author = {Barenghi, Alessandro and Hocquet, C{\'e}dric and Bol, David and Standaert, Fran{\c c}ois-Xavier and Regazzoni, Francesco and Koren, Israel}
}
@article {18063,
	title = {Harvesting the potential of nano-CMOS for lightweight cryptography: An ultra-low-voltage 65 nm AES coprocessor for passive RFID tags},
	journal = {Springer Journal of Cryptographic Engineering},
	volume = {1},
	issue = {1},
	year = {2011},
	author = {Hocquet, C{\'e}dric and Kamel, Dina and Regazzoni, Francesco and Legat, Jean-Didier and Flandre, Denis and Bol, David and Standaert, Fran{\c c}ois-Xavier}
}
