@Patent {18589,
	title = {Reconfigurable Logic Circuit},
	number = {GB1719355.8},
	year = {Submitted},
	month = {11/2017},
	type = {UK},
	author = {Mentens, Nele and Charbon, Edoardo and Regazzoni, Francesco}
}
@article {18567,
	title = {Customized Instructions for Protection Against Memory Integrity Attacks},
	journal = {IEEE Embedded Systems Letters},
	year = {In Press},
	author = {Roy, Debapriya Basu and Alam, Manaar and Bhattacharya, Sarani and Govindan, Vidya and Regazzoni, Francesco and Chakraborty, Rajat Subhra and Mukhopadhyay, Debdeep}
}
@book {18544,
	title = {Artificial Intelligence in the Age of Neural Networks and Brain Computing},
	series = {Academic Press },
	year = {2018},
	pages = {420},
	edition = {1},
	abstract = {Artificial Intelligence in the Age of Neural Networks and Brain Computing demonstrates that existing disruptive implications and applications of AI is a development of the unique attributes of neural networks, mainly machine learning, distributed architectures, massive parallel processing, black-box inference, intrinsic nonlinearity and smart autonomous search engines. The book covers the major basic ideas of brain-like computing behind AI, provides a framework to deep learning, and launches novel and intriguing paradigms as future alternatives. The success of AI-based commercial products proposed by top industry leaders, such as Google, IBM, Microsoft, Intel and Amazon can be interpreted using this book. },
	author = {Kozma, Robert and Alippi, Cesare and Choe, Yoonsuck and Morabito, Francesco}
}
@article {18549,
	title = {The Case for Polymorphic Registers in Dataflow Computing},
	journal = {International Journal of Parallel Programming},
	volume = {54},
	issue = {5},
	year = {2018},
	month = {10/2018},
	pages = {54-62},
	chapter = {54},
	doi = {10.1007/s10766-017-0494-1},
	author = {Ciobanu, Catalin B. and Gaydadjiev, Georgi and Pilato, Christian and Sciuto, Donatella}
}
@article {18536,
	title = {Credit Card Fraud Detection: A Realistic Modeling and a Novel Learning Strategy},
	journal = {IEEE Transactions on Neural Networks and Learning Systems},
	year = {2018},
	pages = {1-14},
	keywords = {Amplitude modulation, Area measurement, Companies, Concept drift, Credit card fraud detection, Credit cards, learning in nonstationary environments, Learning systems, Tools, Training, unbalanced classification.},
	issn = {2162-237X},
	doi = {10.1109/TNNLS.2017.2736643},
	author = {Dal Pozzolo, Andrea and Boracchi, Giacomo and Caelen, Olivier and Alippi, Cesare and Bontempi, Gianluca}
}
@conference {18551,
	title = {Dark{M}em: Fine-Grained Power Management of Local Memories for Accelerators in Embedded Systems},
	booktitle = {Proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC)},
	year = {2018},
	doi = {10.1109/ASPDAC.2018.8297403},
	author = {Pilato, Christian and Carloni, Luca P.}
}
@conference {18575,
	title = {Rethinking Secure FPGAs: TowardsCryptography-friendly Configurable Cell Architecture and its Automated Design Flow},
	booktitle = {Proceedings of FCCM},
	year = {2018},
	month = {05/2018},
	author = {Mentens, Nele and Charbon, Edoardo and Regazzoni, Francesco}
}
@conference {18588,
	title = {SCA-Resistance for AES: How Cheap Can We Go?},
	booktitle = {Progress in Cryptology {\textendash} AFRICACRYPT 2018},
	year = {2018},
	publisher = {Springer International Publishing},
	organization = {Springer International Publishing},
	address = {Cham},
	abstract = {This paper introduces a novel AES structure capable of improving the robustness against power analysis attacks while allowing for a very compact structure with a potentially negligible area and performance impact. The proposed design is based on a low entropy masking scheme, where half of the time the true value and half of the time the complemented value are used to mask the power consumption variation. The obtained experimental results suggest that the area overhead for the protection against power analysis is as low as 5{\%} LUT increase with a performance degradation of about 10{\%}. When compared with the state of the art supported on FPGAs, efficiency improvements above 6 times and a throughput improvement of at least two times higher are achieved.},
	isbn = {978-3-319-89339-6},
	author = {Chaves, Ricardo and Chmielewski, {\L}ukasz and Regazzoni, Francesco and Batina, Lejla},
	editor = {Joux, Antoine and Nitaj, Abderrahmane and Rachidi, Tajjeeddine}
}
@inbook {18572,
	title = {Hardware Security and Trust: Design and Deployment of Integrated Circuits in a Threatened Environment},
	year = {2017},
	publisher = {Springer},
	organization = {Springer},
	edition = {First edition; 2016},
	author = {Sklavos, Nicolas and Chaves, Ricardo and Di Natale, Giorgio and Regazzoni, Francesco}
}
@conference {18537,
	title = {A lightweight and energy-efficient Internet-of-birds tracking system},
	booktitle = {2017 IEEE International Conference on Pervasive Computing and Communications (PerCom)},
	year = {2017},
	month = {March},
	keywords = {animal movement tracking, application server, Birds, cellular radio, cloud computing, energy assessment, energy conservation, energy consumption, energy efficient Internet-of-birds tracking system, GSM, GSM-based tracking device energy consumption reduction, Internet of Things, Internet-of-things vision, joint localization-transmission phase, Northern Italy, quality of service, Radar tracking, Receivers, Satellites, telecommunication power management, Tracking, Transmitters},
	doi = {10.1109/PERCOM.2017.7917862},
	author = {Alippi, Cesare and Ambrosini, Roberto and Longoni, Violetta and Cogliati, Dario and Roveri, Manuel}
}
@article {18550,
	title = {System-Level Optimization of Accelerator Local Memory for Heterogeneous Systems-on-Chip},
	journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
	volume = {36},
	year = {2017},
	pages = {435-448},
	keywords = {algorithm design and analysis, Data structures, hardware, hardware accelerator, High-Level Synthesis, IP networks, Memory Design, Memory management, Multi-bank Architecture, Random access memory},
	doi = {10.1109/TCAD.2016.2611506},
	author = {Pilato, Christian and Mantovani, Paolo and Di Guglielmo, Giuseppe and Carloni, Luca P.}
}
@proceedings {18514,
	title = {CCM: Controlling the Change Magnitude in High Dimensional Data},
	journal = {In Proceedings of the 2nd INNS Conference on Big Data 2016 (INNS Big Data 2016)},
	year = {2016},
	month = {10/2016},
	pages = {1-10},
	address = {Thessaloniki, Greece},
	abstract = {Change-detection algorithms are often tested on real-world datasets where changes are synthetically introduced. While this common practice allows generating multiple datasets to obtain stable performance measures, it is often quite arbitrary since the change magnitude is seldom controlled. Thus, experiments { in particular those on multivariate and high-dimensional data. We here present a rigorous framework for introducing changes having a controlled magnitude in multivariate datasets. In particular, we introduce changes by directly roto-translating the data, and we measure the change magnitude by the symmetric
Kullback-Leibler divergence between pre- ad post-change distributions. We present an iterative algorithm that identities the roto-translation parameters yielding the desired change magnitude, and we prove its convergence analytically. We also illustrate our MATLAB framework that introduces changes having a controlled magnitude in real-world datasets, which is made publicly available for download.
},
	author = {Alippi, Cesare and Boracchi, Giacomo and Carrera, Diego}
}
@conference {18447,
	title = {Change Detection in Multivariate Datastreams: Likelihood and  Detectability Loss},
	booktitle = {25th International Joint Conference on Artificial Intelligence (IJCAI-16)},
	year = {2016},
	month = {07/2016},
	address = { New York, USA},
	abstract = {We address the problem of detecting changes in multivariate datastreams, and we investigate the intrinsic difficulty that change-detection methods have to face when the data-dimension scales. In particular, we consider the general approach that detects changes by comparing the distribution of the log-likelihood of the datastream over different time windows. Despite the fact that this approach constitutes the frame for several change-detection methods, its effectiveness when the dimension of data scales has never been investigated, which is indeed the goal of our paper. We show that the magnitude of the change can be naturally measured by the symmetric Kullback-Leibler divergence between the pre- and post-change distributions, and that the detectability of a change of a given magnitude worsens when the data-dimension increases. This structural problem, which we refer to as detectability loss, is due to the linear relationship existing between the variance of the log-likelihood and the data dimension, and reveals to be harmful even at low data-dimensions (say, 10). We analytically derive the detectability loss on Gaussian-distributed datastreams, and empirically demonstrate that this problem holds also on real-world datasets.},
	author = {Alippi, Cesare and Boracchi, Giacomo and Carrera, Diego and Roveri, Manuel}
}
@conference {18478,
	title = {200 MS/s ADC implemented in a FPGA employing TDCs},
	booktitle = {FPGA International Symposium on Field-Programmable Gate Arrays ACM/SIGDA 2015},
	series = {Proceedings of the 2015 ACM/SIGDA},
	year = {2015},
	month = {02/2015},
	pages = {228-235},
	publisher = {ACM},
	organization = {ACM},
	address = {Monterey, CA, USA},
	abstract = {Analog signals are used in many applications and systems, such as cyber physical systems, sensor networks and automotive applications. These are also applications where the use of FPGAs is continuously growing. To date, however there is no direct integration between FPGAs, which are digital, and the analog world (except for the newest generation of FPGAs). Currently, an external analog-to-digital converter (ADC) has to be added to the system, thus limiting its overall compactness and flexibility.

To address this issue we propose a novel architecture implementing a high speed ADC in reconfigurable devices. The system exploits picosecond resolution time-to-digital converters (TDCs) to reach a conversion as fast as its clock speed. The resulting analog-through-time-to-digital converter (ATDC) can achieve a sampling rate of 200 MS/s with a 7 bit resolution for signals ranging from 0 to 2.5 V. Except for the external resistor needed for the analog reference ramp, the system is fully integrated inside the target FPGA. Moreover, our design can be easily scaled for multichannel ADCs, proving the suitability of reconfigurable devices for applications requiring a deep integration between analog and digital world.
},
	keywords = {analog-through time to digital convertor, FPGA-based design, reference voltage},
	isbn = {978-1-4503-3315-3},
	doi = {10.1145/2684746.2689070},
	url = {http://doi.acm.org/10.1145/2684746.2689070},
	author = {Homulle, Harald and Regazzoni, Francesco and Charbon, Edoardo}
}
@conference {18469,
	title = {Accelerating differential power analysis on heterogeneous systems},
	booktitle = {The 9th Workshop on Embedded Systems Security (WESS) 2014},
	year = {2014},
	month = {10/2014},
	publisher = {ACM},
	organization = {ACM},
	address = {New Delhi, India},
	abstract = {Differential Power Analysis (DPA) attacks allows discovering the secret key stored into secure embedded systems by exploiting the correlation between the power consumed by a device and the data being processed. The computation involved is generally relatively simple, however, if the used power traces are composed by a large number of points, the processing time can be long. In this paper we aim at speeding up the so called correlation power analysis (CPA). To do so, we used the OpenCL framework to distribute the workload of the attack over an heterogeneous platform composed by a CPU and multiple accelerators. We concentrate in the computation of the Pearson{\textquoteright}s correlation coefficients, as they cover approximately 80\% of the overall execution time, and we further optimize the attack by minimizing the data transfers between the host processor and the GPUs. Our results show performance improvements of up to 9x when compared with the reference parallel implementation},
	keywords = {heterogeneous systems, power analysis},
	isbn = {978-1-4503-2932-3},
	doi = {10.1145/2668322.2668326},
	url = {http://doi.acm.org/10.1145/2668322.2668326},
	author = {Amaral, Joao and Regazzoni, Francesco and Tomas, Pedro and Chaves, Ricardo}
}
@conference {18232,
	title = {Responsiveness of Service Discovery in Wireless Mesh Networks},
	booktitle = {20th Pacific Rim International Symposium on Dependable Computing (PRDC)},
	year = {2014},
	month = {11/2014},
	publisher = {IEEE Computer Society},
	organization = {IEEE Computer Society},
	address = {Singapore},
	abstract = {Service Discovery (SD) is an integral part of service networks. Before a service can be used, it needs to be discovered successfully. Comprehensive service dependability analysis thus needs to include the SD process. As a time-critical operation, an important property of SD is responsiveness: The probability of successful discovery within a deadline, even in the presence of faults. This is especially true for dynamic networks with complex fault behavior such as wireless networks. This work evaluates the responsiveness of decentralized SD in wireless mesh networks. For this reason, the experiment framework ExCovery has been employed, which provides a unified description, execution, measurement and storage of experiments. ExCovery runs on the Distributed Embedded System (DES) wireless testbed at Freie Universit{\"a}t Berlin. We present and discuss the results of the experiments and show how responsiveness is affected by the position and number of requester and providers as well as the load in the network. The results clearly demonstrate that in all but the most favorable conditions, the configurations of current SD protocols struggle to achieve a high responsiveness.},
	keywords = {Experiments, Responsiveness, Service Discovery, Wireless mesh networks, Zeroconf},
	doi = {10.1109/PRDC.2014.38},
	url = {http://andreas-dittrich.eu/2014/06/prdc2014},
	author = {Dittrich, Andreas and Herrera, Daniel Solis and Coto, Pablo and Malek, Miroslaw}
}
@conference {18470,
	title = {Single-Photon Avalanche Diodes (SPADs) for quantum random number generators and beyond},
	booktitle = {19th Asia and South Pacific Design Automation Conference (ASP-DAC) 2014},
	year = {2014},
	month = {01/2014},
	publisher = {IEEE},
	organization = {IEEE},
	address = {Singapore},
	abstract = {Single-Photon Avalanche Diodes (SPADs) are solid-state photo-detectors capable of detecting single photons by exploiting the avalanche effect that occurs in the breakdown of a p-n junction biased above breakdown voltage. By this effect, a SPAD translates an incoming photon to a macroscopic current pulse. These devices are currently used for building medical devices characterized by a very high time resolution. An appealing application of SPAD is to use them as a basic block for building the entropy source of true random number generators. In this paper we focus on such application, and we explore the design challenges behind the realization of a quantum random number generator based on a massively parallel array of SPADs. The matrix under investigation comprises 512{\texttimes}128 independent cells that convert photons onto a raw bit-stream, which, as ensured by the properties of quantum physics, is characterized by a very high level of randomness. The sequences are read out in a 128-bit parallel bus, concatenated, and pipelined onto a de-biasing filter. Subsequently, we fabricated the proposed chip using a standard CMOS process. Our results, achieved on the manufactured device and coupling two matrices, show that our architecture can reach up to 5 Gbit/s while consuming 25pJ/bit, thus demonstrating scalability and performance for any random number generators based on SPADs},
	keywords = {quantum physics, random number generators, SPAD},
	isbn = {978-1-4799-2816-3},
	url = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6736726},
	author = {Regazzoni, Francesco and Burri, Samuel and Stucki, Damien and Maruyama, Yuki and Bruschini, Claudio and Charbon, Edoardo}
}
@conference {17578,
	title = {An Algorithm for Extended Dynamic Range Video in Embedded Systems},
	booktitle = {SENSORNETS 2013 - 2nd International Conference on Sensor Networks},
	year = {2013},
	month = {02/2013},
	publisher = {INSTICC},
	organization = {INSTICC},
	address = {Barcelona, Spain},
	keywords = {embedded systems, extended dynamic range, HDR, image processing, sensor, videocamera},
	author = {Ferrante, Alberto and Chelodi, Massimo and Bruschi, Francesco and Mozzetti, Valeria}
}
@conference {18069,
	title = {Comparison of Two Cameras based on Single Photon Avalanche Diodes (SPADS) for Fluorescence Lifetime Imaging Application with Picosecond Resolution},
	booktitle = {International Image Sensor Workshop (IISW)},
	year = {2013},
	month = {June},
	address = {Snowbird Resort, Utah, USA},
	author = {Powolny, Fran{\c c}ois and Burri, Samuel and Bruschini, Claudio and Michalet, Xavier and Regazzoni, Francesco and Charbon, Edoardo}
}
@conference {18068,
	title = {Jailbreak Imagers: Transforming a Single-Photon Image Sensor into a True Random Number Generator},
	booktitle = {International Image Sensor Workshop (IISW)},
	year = {2013},
	month = {June},
	address = {Snowbird Resort, Utah, USA},
	author = {Burri, Samuel and Stucki, Damien and Maruyama, Yuki and Bruschini, Claudio and Charbon, Edoardo and Regazzoni, Francesco}
}
@inbook {17731,
	title = {Model-Driven Evaluation of User-Perceived Service Availability},
	booktitle = {Dependable Computing},
	series = {Lecture Notes in Computer Science},
	volume = {7869},
	year = {2013},
	month = {May},
	pages = {39-53},
	publisher = {Springer Berlin Heidelberg},
	organization = {Springer Berlin Heidelberg},
	abstract = {Service-oriented architecture (SOA), which proposes services as basic building elements of system design, has emerged as an approach to master growing system complexity. However, it remains difficult to evaluate dependability of such distributed and heterogeneous functionality as it depends highly on the properties of the enabling information and communications technology (ICT) infrastructure. Moreover, every specific pair service client and provider can utilize different ICT components, constituting for the user-perceived view of a service. We provide a model-driven methodology to automatically create reliability block diagrams of such views. Given a service description, a network topology model and a pair service client and provider, it identifies relevant ICT components and generates a user-perceived service availability model (UPSAM). We then use this UPSAM to calculate the steady-state availability of different views on an examplary mail service deployed in the network infrastructure of University of Lugano.},
	keywords = {availability, design engineering, modeling, object oriented modeling, quality of service (QoS), service dependability, service network management, service networks},
	issn = {978-3-642-38788-3},
	doi = {10.1007/978-3-642-38789-0_4},
	url = {http://andreas-dittrich.eu/2013/04/model-driven-evaluation-of-user-perceived-service-availability},
	author = {Dittrich, Andreas and Rezende, Rafael},
	editor = {Vieira, Marco and Cunha, Jo{\~a}o Carlos}
}
@conference {18070,
	title = {Single-Photon Image Sensors},
	booktitle = {Special Session, 50th Design Automation Conference (DAC)},
	year = {2013},
	month = {June},
	address = {Austin, Texas, USA},
	author = {Charbon, Edoardo and Regazzoni, Francesco}
}
@conference {18039,
	title = {Smart Building Integration in Smart Grids},
	booktitle = {The 44th Heating Ventilation Air Condition and Refrigeration Congress and Exhibition - KGH 2013},
	year = {2013},
	abstract = {Modern power distribution systems gradually evolve into Smart Grids. Intelligence is getting inserted in all segments of the grid, monitoring and controlling entire power flow from generation and distribution down to consumption of home appliances. On the other hand renewable generation systems are getting widely deployed in public and residential buildings turning them into prosumers. Such scenario requires novel solutions for smart coupling of generation and consumption. Different kinds of prosumers clustering have been proposed by scientific community as a response. In the present work we propose an ICT structure capable of tackling this challenge. The conceptual solution represents an architecture which enables seamless integration of Smart Buildings into Smart Grids.},
	keywords = {Clustering, smart grid, smart home, System Level Model},
	author = {Lukovi{\'c}, Slobodan and {\v C}ongradac, Velimir and Kuli{\'c}, Filip}
}
@article {18050,
	title = {A system-level approach to adaptivity and fault-tolerance in NoC-based MPSoCs: The MADNESS project.},
	journal = {Microprocessors and Microsystems - Embedded Hardware Design},
	volume = {37},
	issue = {6-7},
	year = {2013},
	pages = {515{\textendash}529},
	doi = {10.1016/j.micpro.2013.07.007},
	author = {Derin, Onur and Cannella, Emanuele and Tuveri, Giuseppe and Meloni, Paolo and Stefanov, Todor and Fiorin, Leandro and Raffo, Luigi and Sami, Mariagiovanna}
}
@article {155.CaDeMeTuSt12.VLSI,
	title = {Adaptivity Support for MPSoCs based on Process Migration in Polyhedral Process Networks},
	journal = {VLSI Design},
	volume = {2012},
	number = {Article ID 987209},
	year = {2012},
	note = {Special issue on Application-Driven Design of Processor, Memory, and Communication Architectures for MPSoCs},
	month = {February},
	pages = {15 pages},
	publisher = {Hindawi},
	abstract = {System adaptivity is becoming an important feature of modern embedded multiprocessor systems. To achieve the goal of system adaptivity when executing Polyhedral Process Networks (PPNs) on a generic tiled Network-on-Chip (NoC) MPSoC platform, we propose an approach to enable the run-time migration of processes among the available platform resources. In our approach, process migration is allowed by a middleware layer which comprises two main components. The first component concerns the inter-tile data communication between processes. We develop and evaluate a number of different communication approaches which implement the semantics of the PPN model of computation on a generic NoC platform. The presented communication approaches do not depend on the mapping of processes, and have been implemented on a Network-on-Chip multiprocessor platform prototyped on an FPGA. Their comparison in terms of the introduced overhead is presented in two case studies with different communication characteristics. The second middleware component allows the actual run-time migration of PPN processes. To this end, we propose and evaluate a process migration mechanism which leverages the PPN model of computation to guarantee a predictable and efficient migration procedure. The efficiency and applicability of the proposed migration mechanism is shown in a real-life case study.},
	keywords = {middleware, network-on-chip (NoC), polyhedral process networks (PPN), process migration, system adaptivity},
	author = {Cannella, Emanuele and Derin, Onur and Meloni, Paolo and Tuveri, Giuseppe and Stefanov, Todor}
}
@conference {17737,
	title = {System Adaptivity and Fault-tolerance in NoC-based MPSoCs: the MADNESS Project Approach},
	booktitle = {Proceedings of the 15th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD{\textquoteright}12)},
	year = {2012},
	month = {September 5-8},
	address = {Izmir, Turkey},
	abstract = {Modern embedded systems increasingly require adaptive run-time management. The system may adapt the mapping of the applications in order to accommodate the current workload conditions, to balance load for efficient resource utilization, to meet quality of service agreements, to avoid thermal hot-spots and to reduce power consumption. As the possibility of experiencing run-time faults becomes increasingly relevant with deep-sub-micron technology nodes, in the scope of the MADNESS project, we focus particularly on the problem of graceful degradation by dynamic remapping in presence of run-time faults. In this paper, we summarize the major results achieved in the MADNESS project until now regarding the system adaptivity and fault tolerant processing. We report the first results of the integration between platform level and middleware level support for adaptivity and fault tolerance. A case study demonstrates the survival ability of the platform via a low-overhead process migration mechanism and a near-optimal online remapping heuristic.},
	keywords = {fault tolerance, kahn process networks (KPN), middleware, network-on-chip (NoC), process migration, system adaptivity},
	doi = {http://dx.doi.org/10.1109/DSD.2012.122},
	author = {Meloni, Paolo and Tuveri, Giuseppe and Raffo, Luigi and Cannella, Emanuele and Stefanov, Todor and Derin, Onur and Fiorin, Leandro and Sami, Mariagiovanna}
}
@article {17738,
	title = {Towards Self-adaptive KPN Applications on NoC-based MPSoCs},
	journal = {Advances in Software Engineering},
	volume = {2012},
	year = {2012},
	month = {September},
	pages = {16 pages},
	abstract = {Self-adaptivity is the ability of a system to adapt itself dynamically to internal and external changes. Such a capability helps systems to meet the performance and quality goals, while judiciously using available resources. In this paper, we propose a framework to implement application level self-adaptation capabilities in KPN applications running on NoC-based MPSoCs. The monitor-controller-adapter mechanism is used at the application level. The monitor measures various parameters to check whether the system meets the assigned goals. The controller takes decisions to steer the system towards the goal, which are applied by the adapters. The proposed framework requires minimal modifications to the application code and offers ease of integration. It incorporates a generic adaptation controller based on fuzzy logic. We present the MJPEG encoder as a case study to demonstrate the effectiveness of the approach. Our results show that even if the parameters of the fuzzy controller are not tuned optimally, the adaptation convergence is achieved within reasonable time and error limits. Moreover, the incurred steady-state overhead due to the framework is 4\% for average frame-rate, 3.5\% for average bit-rate, and 0.5\% for additional control data introduced in the network.},
	keywords = {kahn process networks (KPN), network-on-chip (NoC), quality of service (QoS), self-adaptivity},
	doi = {http://dx.doi.org/10.1155/2012/172674},
	author = {Derin, Onur and Ramankutty, Prasanth Kuncheerat and Meloni, Paolo and Cannella, Emanuele}
}
@conference {18493,
	title = {ADSC: Application-Driven Storage Control for Energy Efficiency},
	booktitle = {Information and Communication on Technology for the Fight against Global Warming - First International Conference ICT-GLOW},
	series = {Lecture Notes in Computer Science },
	volume = {6868},
	year = {2011},
	month = {08/2011},
	pages = {165-179},
	publisher = {Springer},
	organization = {Springer},
	address = {Toulouse, France},
	abstract = {While performance and quality of service are the main criteria for application data management on storage units, energy efficiency is increasingly being stated as an additional criterion for evaluation. Due to the increasing energy consumption of storage subsystems, improving their energy efficiency is an important issue. In this paper we present a novel approach to storage management whereby both mid-level (file placement) and low level (disk mode) aspects are controlled, in a tiered storage architecture. The proposed mechanism is based on policies, and it is implemented via fuzzy logic rules, in contrast to attempting to build a model of the storage subsystem. The inputs to the storage management system are high level (application), mid level (file system) and low level (disk access patterns) information. The effectiveness of our approach has been validated by means of a case study using a TPC-C benchmark modified to access file level data. Results from this simulation are presented.},
	isbn = {978-3-642-23446-0},
	doi = {10.1007/978-3-642-23447-7_15},
	url = {http://dx.doi.org/10.1007/978-3-642-23447-7_15},
	author = {Cappiello, Cinzia and Hinostroza, Alicia and Pernici, Barbara and Sami, Mariagiovanna and Henis, Ealan and Kat, Ronen I. and Meth, Kalman Z. and Mura, Marcello}
}
@inbook {141.aetherinbook.2011,
	title = {AETHER: Self-Adaptive Networked Entities: Autonomous Computing Elements for Future Pervasive Applications and Technologies},
	booktitle = {Reconfigurable Computing: From FPGAs to Hardware/Software Codesign},
	year = {2011},
	pages = {149{\textendash}184},
	publisher = {Springer},
	organization = {Springer},
	address = {New York, USA},
	abstract = {The AETHER project has laid the foundation of a complete new framework for designing and programming computing resources that live in changing environments and need to re-configure their objectives in a dynamic way. This chapter contributes to a strategic research agenda in the field of self-adaptive computing systems. It brings inputs to the reconfigurable hardware community and proposes directions to go for reconfigurable hardware and research on self-adaptive computing; it tries to identify some of the most promising future technologies for reconfiguration, while pointing out the main foreseen Challenges for reconfigurable hardware. This chapter presents the main solutions the AETHER project proposed for some of the major concerns in trying to engineer a self-adaptive computing system. The text exposes the AETHER vision of self-adaptation and its requirements. It describes and discusses the proposed solutions for tackling self-adaptivity at the various levels of abstractions. It exposes how the developed technologies could be put together in a real methodology and how self-adaptation could then be used in potential applications. Finally and based on lessons learned from AETHER, we discuss open issues and research opportunities and put those in perspective along other investigations and roadmaps.},
	isbn = {978-1-4614-0061-5},
	author = {Gamrat, Christian and Philippe, Jean-Marc and Jesshope, Chris and Shafarenko, Alex and Bisdounis, Labros and Bondi, Umberto and Ferrante, Alberto and Cabestany, Joan and Huebner, Michael and Parsinnen, Juha and Kadlec, Jiri and Danek, Martin and Tain, Benoit and Eisenbach, Susan and Auguin, Michel and Diguet, Jean-Philippe and Lenormand, Eric and Roux, Jean-Luc},
	editor = {Cardoso, Joao Manuel Pai and Huebner, Michael}
}
@conference {154.BaChDe11.ISWCS,
	title = {Energy-Throughput Simulation Approach for Heterogeneous LTE scenarios},
	booktitle = {ISWCS{\textquoteright}11: Proceedings of The Eighth International Symposium on Wireless Communication Systems},
	year = {2011},
	month = {November 6-9},
	pages = {1{\textendash}5},
	address = {Aachen, Germany},
	abstract = {In order to increase overall LTE system performance femtocells have been proposed as a user-based solution promising to give much better service to the user specially indoor. Their deployment should improve the total system capacity noticeably and decrease drastically the power consumption. On the other hand these small indoor cells make the network planning strategies much more complex given the uncertainty of their position and their load; femtocells are after all managed by the users. Goal of this work is to provide a simulation approach to determine the effects of heterogeneous cell deployment on the performance of an LTE network. The simulation framework allows to realistically compare the power consumption and throughput of the overall system. The key components are the combination of indoor and outdoor propagation modeling, and the diversification of femto, micro and macro-cell energy consumption models. The model further contains complex city-like building structures, multiple communication layers (eNodeBs and femtocells) distributed over a three-dimensional map and numerous users moving across different areas while adapting their service requirements. The simulation approach results in relatively computationally inexpensive simulations and allows to model the expected throughput and energy consumption for various heterogeneous LTE scenarios.},
	keywords = {long term evolution (LTE)},
	doi = {http://dx.doi.org/10.1109/ISWCS.2011.6125377},
	author = {Baddour, Rami and Chiumento, Alessandro and Desset, Claude}
}
@conference {153.CaDeSt11.DASIP,
	title = {Middleware Approaches for Adaptivity of Kahn Process Networks on Networks-on-Chip},
	booktitle = {DASIP{\textquoteright}11: Proceedings of the Conference on Design and Architectures for Signal and Image Processing},
	year = {2011},
	month = {November 2-4},
	pages = {1{\textendash}8},
	address = {Tampere, Finland},
	abstract = {We investigate and propose a number of different middleware approaches, namely virtual connector, virtual connector with variable rate, and request-based, which implement the semantics of Kahn Process Networks on Network-on-Chip architectures. All of the presented solutions allow for run-time system adaptivity. We implement the approaches on a Network-on-Chip multiprocessor platform prototyped on an FPGA. Their comparison in terms of the introduced overhead is presented on two case studies with different communication characteristics. We found out that the virtual connector mechanism outperforms other approaches in the communication-intensive application. In the other case study, which has a higher computation/communication ratio, the middleware approaches show similar performance.},
	keywords = {kahn process networks (KPN), middleware, network-on-chip (NoC), self-adaptivity},
	doi = {http://dx.doi.org/10.1109/DASIP.2011.6136862},
	author = {Cannella, Emanuele and Derin, Onur and Stefanov, Todor}
}
@inbook {17734,
	title = {The MULTICUBE Design Flow},
	booktitle = {Multi-objective Design Space Exploration of Multiprocessor SoC Architectures},
	year = {2011},
	pages = {3-17},
	publisher = {Springer New York},
	organization = {Springer New York},
	isbn = {978-1-4419-8836-2},
	doi = {10.1007/978-1-4419-8837-9_1},
	url = {http://dx.doi.org/10.1007/978-1-4419-8837-9_1},
	author = {Silvano, Cristina and Fornaciari, William and Palermo, Gianluca and Zaccaria, Vittorio and Castro, Fabrizio and Martinez, Marcos and Bocchio, Sara and Zafalon, Roberto and Avasare, Prabhat and Vanmeerbeeck, Geert and Ykman-Couvreur, Chantal and Wouters, Maryse and Kavka, Carlos and Onesti, Luka and Turco, Alessandro and Bondi, Umberto and Mariani, Giovanni and Posadas, Hector and Villar, Eugenio and Wu, Chris and Dongrui, Fan and Hao, Zhang},
	editor = {Silvano, Cristina and Fornaciari, William and Villar, Eugenio}
}
@inbook {139.Sietal2.2011,
	title = {MULTICUBE: Multi-Objective Design Space Exploration of Multi-Core Architectures},
	booktitle = {VLSI 2010 Annual Symposium},
	volume = {105},
	year = {2011},
	pages = {47-63},
	publisher = {Springer},
	organization = {Springer},
	address = {Netherlands},
	abstract = {Given the increasing complexity of Chip Multi-Processors (CMPs), a wide range of architecture parameters must be explored at design time to find the best trade-off in terms of multiple competing objectives (such as energy, delay, bandwidth, area, etc.) The design space of the target architectures is huge because it should consider all possible combinations of each hardware parameter (e.g., number of processors, processor issue width, L1 and L2 cache sizes, etc.). In this complex scenario, intuition and past experience of design architects is no more a sufficient condition to converge to an optimal design of the system. Indeed, Automatic Design Space Exploration (DSE) is needed to systematically support the analysis and quantitative comparison of a large amount of design alternatives in terms of multiple competing objectives (by means of Pareto analysis). The main goal of the MULTICUBE project consists of the definition of an automatic Design Space Exploration framework to support the design of next generation many-core architectures.},
	isbn = {978-94-007-1487-8},
	url = {http://dx.doi.org/10.1007/978-94-007-1488-5_4},
	author = {Silvano, Cristina and Fornaciari, William and Palermo, Gianluca and Zaccaria, Vittorio and Castro, Fabrizio and Martinez, Marcos and Bocchio, Sara and Zafalon, Roberto and Avasare, Prabhat and Vanmeerbeeck, Geert and Ykman-Couvreur, Chantal and Wouters, Maryse and Kavka, Carlos and Onesti, Luka and Turco, Alessandro and Bondi, Umberto and Mariani, Giovanni and Posadas, Hector and Villar, Eugenio and Wu, Chris and Dongrui, Fan and Hao, Zhang and Shibin, Tang}
}
@conference {18081,
	title = {Power-Gated MOS Current Mode Logic (PG-MCML): A Power-Aware DPA-Resistant Standard Cell Library},
	booktitle = {48th Design Automation Conference (DAC)},
	year = {2011},
	month = {June},
	address = {San Diego, Califorina},
	author = {Cevrero, Alessandro and Regazzoni, Francesco and Schwander, Michael and Badel, St{\'e}phane and Ienne, Paolo and Leblebici, Yusuf}
}
@conference {17740,
	title = {Towards an ESL design framework for adaptive and fault-tolerant MPSoCs: MADNESS or not?},
	booktitle = {Embedded Systems for Real-Time Multimedia (ESTIMedia), 2011 9th IEEE Symposium on},
	year = {2011},
	abstract = {The MADNESS project aims at the definition of innovative system-level design methodologies for embedded MP-SoCs, extending the classic concept of design space exploration in multi-application domains to cope with high heterogeneity, technology scaling and system reliability. The main goal of the project is to provide a framework able to guide designers and researchers to the optimal composition of embedded MPSoC architectures, according to the requirements and the features of a given target application field. The proposed approach will tackle the new challenges, related to both architecture and design methodologies, arising with the technology scaling, the system reliability and the ever-growing computational needs of modern applications. The methodologies proposed with this project act at different levels of the design flow, enhancing the state-of-the art with novel features in system-level synthesis, architectural evaluation and prototyping. Support for fault resilience and efficient adaptive runtime management is introduced at hardware and middleware level, and considered by the system-level synthesis as one of the optimization factors to be taken into account. This paper presents the first stable results obtained in the MADNESS project, already demonstrating the effectiveness of the proposed methods.},
	keywords = {adaptive MPSoC, adaptive runtime management, computer architecture, embedded MPSoC architectures, emulation, ESL design framework, fault resilience, fault tolerance, fault tolerant MPSoC, field programmable gate arrays, hardware, integrated circuit reliability, libraries, MADNESS project, middleware, multiprocessing systems, network synthesis, program processors, system level design methodologies, system level synthesis, system reliability, system-on-chip (SoC)},
	doi = {10.1109/ESTIMedia.2011.6088518},
	author = {Cannella, Emanuele and Di Gregorio, Lorenzo and Fiorin, Leandro and Lindwer, Menno and Meloni, Paolo and Neugebauer, Olaf and Pimentel, Andy}
}
@conference {133.LuNi10.2,
	title = {Enhancing Network-on-Chip Components to Support Security of Processing Elements},
	booktitle = {Proceedings of the 5th Workshop on Embedded Systems Security (WESS{\textquoteright}2010) A Workshop of the Embedded Systems Week (ESWEEK {\textquoteright}10)},
	year = {2010},
	month = {October 24},
	address = {Scottsdale, AZ, USA},
	abstract = {Network-on-Chip (NoC) has emerged as a promising solution for scalable communication among steadily growing number of cores integrated in MultiProcessor System-on-Chips (MPSoCs). The increasing system heterogeneity together with the possibility of recon guration makes the overall system security one of the major concerns in MPSoC design. On the other hand, modular and scalable design of NoCs enables their enhancements in various directions for supporting services other than simple data routing. In this work we propose and implement a solution to secure attached processing units from a bu er over ow type of the attacks that comes in a form of a protection module that is embedded into the Network Interface of the NoC. At the same time, our solution prevents potential propagation of the attack through the NoC towards other processors. We prove feasibility via prototype realization in FPGA technology for a MicroBlaze processor on Xilinx Virtex-II Pro board.},
	doi = {http://dx.doi.org/10.1145/1873548.1873560},
	author = {Lukovi{\'c}, Slobodan and Christianos, Nikolaos}
}
@conference {134.FiFePaCa10,
	title = {Hardware-assisted Security Enhanced Linux in Embedded Systems: a Proposal},
	booktitle = {Proceedings of the 5th Workshop on Embedded Systems Security (WESS{\textquoteright}2010)},
	year = {2010},
	month = {October 24},
	address = {Scottsdale, Arizona, USA},
	abstract = {As computing and communications increasingly pervade our lives, security and protection of sensitive data and systems are emerging as extremely important issues. This is especially true for embedded systems, often operating in non-secure environments, and with limited amount of computational, storage, and communication resources available. In servers and desktop systems, Security Enhanced Linux (SELinux) is currently used as a method to enhance security by enforcing a security control based on policies that confine user programs, or processes, to the minimum amount of privileges that they require for their execution. While providing a powerful mean for enhancing security in UNIX-like systems, SELinux still remains a feature that is too heavy to be fully supported by constrained devices. In this paper, we propose a hardware architecture for enhancing security and accelerating retrieval and applications of SELinux policies in embedded processors. We describe the general ideas be hind our work, discussing motivations, advantages, and limits of the solution proposed, while suggesting the main steps needed to implement the described architecture on common embedded processors.},
	keywords = {access controls, embedded systems, SELinux},
	author = {Fiorin, Leandro and Ferrante, Alberto and Padarnitsas, Konstantinos and Carucci, Stefano}
}
@conference {132.LuNi10,
	title = {Hierarchical Multi-Agent Protection System for NoC based MPSoCs},
	booktitle = {Proceedings of the International Workshop on Security and Dependability for Resource Constrained Embedded Systems (SD4RCES 2010)},
	year = {2010},
	month = {September 14},
	address = {Vienna, Austria},
	abstract = {Network-on-Chip (NoC) has emerged as a promising solution for scalable communication among steadily growing number of cores integrated in MultiProcessor System-on-Chips (MPSoCs). The increasing system heterogeneity together with the possibility of reconfiguration makes the overall system security one of the major concerns in MPSoC design. On the other hand, modular and scalable design of NoCs enables their enhancements in various directions for supporting services other than simple data routing. In this work we propose a conceptual solution to secure NoC based MPSoCs at different levels of design. The basic idea is to integrate various kinds of security approaches from attack specific protection strategies up to system level security. The concept aims at securing single cores but also, at the same time, prevents potential propagation of the attack through the NoC towards. We prove feasibility via prototype realization in FPGA technology.},
	keywords = {multiprocessor system-on-chip (MPSoC), network-on-chip (NoC), security},
	doi = {http://dx.doi.org/10.1145/1868433.1868441},
	author = {Lukovi{\'c}, Slobodan and Christianos, Nikolaos}
}
@conference {115.ZaPaCaSiMa10,
	title = {Multicube Explorer: An Open Source Framework for Design Space Exploration of Chip Multi-Processors},
	booktitle = {2PARMA: Proceedings of the Workshop on Parallel Programming and Run-time Management Techniques for Many-core Architectures},
	year = {2010},
	month = {February},
	address = {Hannover, Germany},
	abstract = {Given the increasing complexity of Chip Multi-Processors (CMPs), a wide range of architecture parameters must be explored at design time to find the best trade-off in terms of multiple competing objectives (such as energy, delay, bandwidth, area, etc.) The design space of the target architecture is huge because of it should consider all possible combinations of each parameter (number of processors, processor issue width, L1 and L2 cache sizes, etc.). In this complex scenario, the multi-objective exploration of the huge design space of next generation CMPs cannot be anymore based on intuition and past experience of the design architects. An Automatic Design Space Exploration methodology is needed to support systematically the exploration and the quantitative comparison of the design alternatives in terms of multiple competing objectives (Pareto analysis). An overall design space exploration framework is needed to combine all optimizations into a global search space with a common interface to the simulation and evaluation tools. Our work1 focuses on the definition of an automatic multi-objective Design Space Exploration (DSE) framework for tuning Chip Multi-Processor architectures by evaluating a set of metrics (such as energy and delay) for the next generation embedded computing platforms. Multicube Explorer is an interactive open-source framework to enable the designer to automatically explore a design space of configurations for a parameterized architecture for which an executable model (use case simulator) exists. Multicube Explorer is an advanced multi-objective optimization framework which is entirely command-line/script driven and can be re-targeted to any configurable platform by writing a suitable XML design space definition file and providing a configurable simulator},
	author = {Zaccaria, Vittorio and Palermo, Gianluca and Castro, Fabrizio and Silvano, Cristina and Mariani, Giovanni}
}
@conference {129.Sietal.ISVLSI11,
	title = {Multicube: Multi-objective design space exploration of multi-core architectures},
	booktitle = {ISVLSI 2010: IEEE Annual Symposium on VLSI},
	year = {2010},
	month = {July},
	pages = {488{\textendash}493},
	address = {Lixouri, Kefalonia - Greece},
	abstract = {Technology trends enable the integration of many processor cores in a System-on-Chip (SoC). In these complex architectures, several architectural parameters can be tuned to find the best trade-off in terms of multiple metrics such as energy and delay. The main goal of the MULTICUBE project consists of the definition of an automatic Design Space Exploration framework to support the design of next generation many-core architectures.},
	doi = {http://dx.doi.org/10.1109/ISVLSI.2010.67},
	author = {Silvano, Cristina and Fornaciari, William and Palermo, Gianluca and Zaccaria, Vittorio and Castro, Fabrizio and Martinez, Marcos and Bocchio, Sara and Zafalon, Roberto and Avasare, Prabhat and Vanmeerbeeck, Geert and Ykman-Couvreur, Chantal and Wouters, Maryse and Kavka, Carlos and Onesti, Luka and Turco, Alessandro and Bondi, Umberto and Mariani, Giovanni and Posadas, Hector and Villar, Eugenio and Wu, Chris and Dongrui, Fan and Hao, Zhang and Shibin, Tang}
}
@conference {113.LuCoKu10,
	title = {A system level model of possible integration of Building Management System in SmartGrid},
	booktitle = {Complexity in Engineering (COMPENG 2010)},
	year = {2010},
	month = {February 22-24},
	address = {Rome, Italy},
	abstract = {SmartGrids are conceived as modular, end-to-end interoperable systems. It is envisaged that power systems components (modules) will be hierarchically coordinated and integrated in order to form certain autonomous clusters which would perform as much as possible local data storing and processing in order to decrease overall communicational and computational overhead. Building Management Systems (BMS) could be seen as one of such modules inside wider SmartGrid system. The incorporation of BMS must consider both technical as well as commercial issues. Hence, the efficient integration will require standards{\textquoteright} harmonization and closer interaction among key elements of these systems. Moreover, another important issue will be adopting of new market models to BMS. In order to represent the system and relations among its components in a clear and understandable fashion, we introduce system level modeling concept as an instrument to bridge functional requirements and implementation constraints.},
	doi = {http://dx.doi.org/10.1109/COMPENG.2010.43},
	author = {Lukovi{\'c}, Slobodan and {\v C}ongradac, Velimir and Kuli{\'c}, Filip}
}
@conference {118.CaVeStShCeLeAsMe10,
	title = {Trace-based KPN Composability Analysis for Mapping Simultaneous Applications to MPSoC Platforms},
	booktitle = {Proceedings of Design, Automation and Test in Europe(DATE) Conference},
	year = {2010},
	month = {March},
	address = {Dresden, Germany},
	abstract = {Nowadays, most embedded devices need to support multiple applications running concurrently. In contrast to desktop computing, very often the set of applications is known at design time and the designer needs to assure that critical applications meet their constraints in every possible use-case. In order to do this, all possible use-cases, i.e. subset of applications running simultaneously, have to be verified thoroughly. An approach to reduce the verification effort, is to perform composability analysis which has been studied for sets of applications modeled as Synchronous Dataflow Graphs. In this paper we introduce a framework that supports a more general parallel programming model based on the Kahn Process Networks Model of Computation and integrates a complete MPSoC programming environment that includes: compilercentric analysis, performance estimation, simulation as well as mapping and scheduling of multiple applications. In our solution, composability analysis is performed on parallel traces obtained by instrumenting the application code. A case study performed on three typical embedded applications, JPEG, GSM and MPEG-2, proved the applicability of our approach.},
	author = {Castrill{\'o}n, Jer{\'o}nimo and Vel{\'a}squez, Ricardo and Stulova, Anastasia and Sheng, Weihua and Ceng, Jianjiang and Leupers, Rainer and Ascheid, Gerd and Meyr, Heinrich}
}
@article {18492,
	title = {Breaking ECC2K-130},
	journal = {IACR Cryptology ePrint Archive},
	volume = {2009},
	year = {2009},
	month = {11/2009},
	pages = {541},
	abstract = {Elliptic-curve cryptography is becoming the standard public-key primitive not only for mobile devices but also for high-security applications. Advantages are the higher cryptographic strength per bit in comparison with RSA and the higher speed in implementations. To improve understanding of the exact strength of the elliptic-curve discrete-logarithm problem, Certicom has published a series of challenges. This paper describes breaking the ECC2K-130 challenge using a parallelized version of Pollard{\textquoteright}s rho method. This is a major computation bringing together the contributions of several clusters of conventional computers, PlayStation~3 clusters, computers with powerful graphics cards and FPGAs. We also give /preseestimates for an ASIC design. In particular we present * our choice and analysis of the iteration function for the rho method; * our choice of finite field arithmetic and representation; * detailed descriptions of the implementations on a multitude of platforms: CPUs, Cells, GPUs, FPGAs, and ASICs; * details about running the attack. },
	keywords = {Attacks, automorphisms, binary fields, Certicom challenges, DLP, ECC, implementation, Koblitz curves, parallelized Pollard rho},
	url = {http://eprint.iacr.org/2009/541},
	author = {Bailey, Daniel V. and Batina, Lejla and Bernstein, Daniel J. and Birkner, Peter and Bos, Joppe W. and Chen, Hsieh - Chung and Cheng, Chen - Mou and van Damme, Gauthier and G{\"u}neysu, Tim and Gurkaynak, Frank and Kleinjung, Thorsten and Paar, Christof and Regazzoni, Francesco and Niederhagen, Ruben and Schwabe, Peter and Uhsadel, Leif and Van Herrewege, Anthony}
}
@inbook {18085,
	title = {A Design Flow and Evaluation Framework for DPA-resistant Instruction Set Extensions},
	booktitle = {Cryptographic Hardware and Embedded Systems (CHES)},
	series = {Lecture Notes in Computer Science},
	volume = {5747},
	year = {2009},
	month = {September},
	pages = {205-219},
	publisher = {Springer Berlin Heidelberg},
	organization = {Springer Berlin Heidelberg},
	address = {Lausanne, Switzerland},
	abstract = {Power-based side channel attacks are a significant security risk, especially for embedded applications. To improve the security of such devices, protected logic styles have been proposed as an alternative to CMOS. However, they should only be used sparingly, since their area and power consumption are both significantly larger than for CMOS. We propose to augment a processor, realized in CMOS, with custom instruction set extensions, designed with security and performance as the primary objectives, that are realized in a protected logic. We have developed a design flow based on standard CAD tools that can automatically synthesize and place-and-route such hybrid designs. The flow is integrated into a simulation and evaluation environment to quantify the security achieved on a sound basis. Using MCML logic as a case study, we have explored different partitions of the PRESENT block cipher between protected and unprotected logic. This experiment illustrates the tradeoff between the type and amount of application-level functionality implemented in protected logic and the level of security achieved by the design. Our design approach and evaluation tools are generic and could be used to partition any algorithm using any protected logic style.},
	isbn = {978-3-642-04137-2},
	doi = {10.1007/978-3-642-04138-9_15},
	author = {Regazzoni, Francesco and Cevrero, Alessandro and Standaert, Fran{\c c}ois-Xavier and Badel, St{\'e}phane and Kluter, Theo and Brisk, Philip and Leblebici, Yusuf and Ienne, Paolo}
}
@inbook {17765,
	title = {IPSec Database Query Acceleration},
	booktitle = {E-business and Telecommunications},
	series = {Communications in Computer and Information Science},
	volume = {23},
	year = {2009},
	pages = {188-200},
	publisher = {Springer Berlin Heidelberg},
	organization = {Springer Berlin Heidelberg},
	isbn = {978-3-540-88652-5},
	doi = {10.1007/978-3-540-88653-2_14},
	url = {http://dx.doi.org/10.1007/978-3-540-88653-2_14},
	author = {Ferrante, Alberto and Chandra, Satish and Piuri, Vincenzo},
	editor = {Filipe, Joaquim and Obaidat, Mohammad}
}
@conference {110.CoKuLu09,
	title = {Prediction of the type of heating with EnergyPlus program and fuzzy logic},
	booktitle = {40th International Congress on Heating, Refrigerating and Air-conditioning (KGH Congress)},
	year = {2009},
	month = {12/2009},
	address = {Belgrade, Serbia},
	abstract = {The purpose of this work is prediction of the type of heating for the next few days in an office building using EnergyPlus program for simulation and fuzzy logic for determination. In this matter a program that binds weather forecast, created simulation model in EnergyPlus of a five story building in Belgrade, simulation in EnergyPlus and fuzzy logic, and as a result program gives the type of heating which is the most economic to use for the particular day, was built. Everything is done in the way of most efficient and rational use of energy.},
	author = {{\v C}ongradac, Velimir and Kuli{\'c}, Filip and Lukovi{\'c}, Slobodan}
}
@Patent {87.pat07301411.0-2413PATENT,
	title = {Programmable data protection device, secure programming manager system and process for controlling access to an interconnect network for an integrated circuit},
	number = {EP 20070301411},
	year = {2009},
	month = {04/2009},
	type = {Application},
	chapter = {EP 2043324 A1},
	abstract = {A data protection device for an interconnect network on chip (NoC) includes a header encoder that receives input requests for generating network packets. The encoder routes the input requests to a destination address. An access control unit controls and allows access to the destination address. The access control unit uses a memory to store access rules for controlling access to the network as a function of the destination address and of a source of the input request.},
	issn = {EP 2043324 A1},
	author = {Fiorin, Leandro and Palermo, Gianluca and Silvano, Cristina and Catalano, Valerio and Locatelli, Riccardo and Coppola, Marcello}
}
@conference {104.UpCaMaMaPo09,
	title = {Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering},
	booktitle = {Proceedings of the 19th international workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2009)},
	year = {2009},
	month = {September 9-11},
	address = {Delft, The Netherlands},
	abstract = {Clock-gating and power-gating have proven to be two of the most effective techniques for reducing dynamic and leakage power, respectively, in VLSI CMOS circuits. Most commercial synthesis tools do support such techniques individually, but their combined implementation is not available, since some open issues in terms of power/timing overhead associated to the control logic required for the integration are not yet solved. Moving from some recent work targeting clock-gating/power-gating integration, in this paper we present a solution for reducing the timing overhead that may occur when the integration is performed. In particular, we introduce a new, multilevel partitioning heuristic that increases the efficiency of the clustering phase, one of the key steps of our methodology. The results demonstrate the effectiveness of our solution; in fact, power-delay product and timing overhead of the circuits synthesized using the new clustering algorithm improve by 33\% and 24\%, respectively.},
	author = {Upasani, Gaurang and Calimera, Andrea and Macii, Alberto and Macii, Enrico and Poncino, Massimo}
}
@conference {111.ChPaSiZa10,
	title = {Yield Enhancement by Robust Application-specific Mapping on Network-on-Chips},
	booktitle = {NoCArc{\textquoteright}09: Proceedings of the Second International Workshop on Network on-Chip Architectures},
	year = {2009},
	month = {December},
	pages = {37{\textendash}42},
	address = {New York City, USA},
	abstract = {The current technological defect densities and production yields are a motivating factor supporting the introduction of design-for-manufacturability techniques during the highlevel design of complex, embedded systems based on networkon- chips (NoCs). In this context, we tackle the problem of mapping the IPs of a multi-processing system to the NoC nodes, by taking into account the effective robustness of the system with respect to permanent faults in the interconnection network due to manufacturing defects. In particular, we introduce an application specific methodology for identifying optimal NoCs mappings which minimize the variance of the system power and latency and maximizes the probability that the actual system will work when deployed, even in presence of faulty NoC links. We provide experimental results by comparing the proposed methodology with conventional mapping approaches, by highlighting benefits and drawbacks of both techniques},
	author = {Choudhury, Anirban Dutta and Palermo, Gianluca and Silvano, Cristina and Zaccaria, Vittorio}
}
@article {84.AlGaSte2008,
	title = {Secure Memory Accesses on Networks-on-Chip},
	journal = {IEEE Transactions on Computers},
	volume = {57},
	number = {9},
	year = {2008},
	month = {September},
	pages = {1216-1229},
	abstract = {Security is gaining relevance in the development of embedded devices. Towards a secure system at each level of design, this paper addresses security aspects related to Network on Chip (NoC) architectures, foreseen as the communication infrastructure of next-generation embedded devices. In the context of NoC-based multiprocessor systems, we focus on the topic, not yet thoroughly faced, of data protection. In this paper, we present a secure NoC architecture composed of a set of Data Protection Units (DPUs) implemented within the Network Interfaces (NIs)1. The run-time configuration of the programmable part of the DPUs is managed by a central unit, the Network Security Manager (NSM). The DPU, similar to a firewall, can check and limit the access rights (none, read, write, or both) of processors accessing data and instructions in a shared memory. In particular, the DPU can distinguish between the operating roles (supervisor/user and secure/non secure) of the processing elements.We explore alternative implementations of the DPU and demonstrate how this unit does not affect the network latency if the memory request has the appropriate rights. We also focus on the dynamic updating of the DPUs to support their utilization in dynamic environments, and on the utilization of authentication techniques to increase the level of security.},
	keywords = {data protection, embedded systems, multiprocessor system-on-chip (MPSoC), network-on-chip (NoC), security},
	doi = {http://dx.doi.org/10.1109/TC.2008.69},
	author = {Fiorin, Leandro and Palermo, Gianluca and Lukovi{\'c}, Slobodan and Catalano, Valerio and Silvano, Cristina}
}
@conference {61.PaMaSiLo07,
	title = {Application-Specific Topology Design Customization for STNoC},
	booktitle = {DSD07, in proceedings of 10th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD 07)},
	year = {2007},
	month = {August 29-31},
	address = {L{\"u}beck, Germany},
	abstract = {Customized network-oriented communication architectures have recently become a must to support high bandwidth SoCs. To this end, a corresponding communication design flow is necessary to support the design space exploration of complex SoCs with tight design constraints. In order to exploit the benefits introduced by the NoC approach for the on-chip communication, the paper presents a Pareto Simulated Annealing (PSA) approach for the customization of the network topology. The proposed PSA approach has been applied to STNoC, the Network on Chip developed by STMicroelectronics. Starting from the ring topology, the proposed application-specific design flow tries to find a set of customized topologies (optimized in terms of performance and area/energy overhead) by adding custom links up to the spidergon topology.},
	keywords = {application specific design, mapping, network-on-chip (NoC), STNoC, topology customization},
	doi = {http://dx.doi.org/10.1109/DSD.2007.4341522},
	author = {Palermo, Gianluca and Mariani, Giovanni and Silvano, Cristina and Locatelli, Riccardo and Coppola, Marcello}
}
@conference {63.Der2007,
	title = {Learning Java by a Card Game: A Case Study},
	booktitle = {LG2007: Proceedings of Learning with Games Conference},
	year = {2007},
	month = {September 24-27},
	pages = {221{\textendash}228},
	address = {Sophia Antipolis, France},
	abstract = {To teach Java programming language better and in a more enjoyable way, we developed a framework for card games that allows students to write and test their own intelligent players. This paper briefly describes the design of the framework, the advantages of using it to assign homework and reports our experience with a class carried out in our institute.},
	keywords = {assignment, card games, case study, java, pedagogy},
	isbn = {978-88-901168-0-3},
	author = {Derin, Onur},
	editor = {Taisch, Marco and Cassina, Jacopo}
}
@conference {57.PaMaSiLoCo07,
	title = {Mapping and Topology Customization Approaches for Application-Specific STNoC Designs},
	booktitle = {IEEE Proceedings of ASAP{\textquoteright}07 - 18th International Conference on Application-specific Systems, Architectures and Processors},
	year = {2007},
	month = {July},
	address = {Montr{\'e}al, Qu{\'e}bec, Canada},
	abstract = {Application-specific network-oriented communication architectures have recently become an effective solution to support high bandwidth Systems on-Chip. The Network on-Chip architectures considered so far range from regular to fully customized topologies for application specific designs requiring high-level bandwidth. To this end, a networkcentric design flow is necessary to support the design space exploration of complex SoCs with tight design constraints. This paper introduces four different approaches based on the orthogonalization of core mapping and topology customization applied to STNoC, the Network on-Chip developed by STMicroelecronics. The four methods are derived from the combination of the initial mappings to two standard topologies (ring and spidergon) with two types of topology customization based on the insertion of cross-links to reduce the network distance of standard topologies},
	keywords = {application specific design, mapping, network-on-chip (NoC), STNoC, topology customization},
	doi = {http://dx.doi.org/10.1109/ASAP.2007.4429959},
	author = {Palermo, Gianluca and Mariani, Giovanni and Silvano, Cristina and Locatelli, Riccardo and Coppola, Marcello}
}
@conference {58.FeChPi07,
	title = {A Query Unit for the IPSec Databases},
	booktitle = {SECRYPT 2007},
	year = {2007},
	month = {07/2007},
	address = {Barcelona, Spain},
	abstract = {IPSec is a suite of protocols that adds security to communications at the IP level. Protocols within IPSec make extensive use of two databases, namely the Security Policy Database (SPD) and the Security Association Database (SAD). The ability to query the SPD quickly is fundamental as this operation needs to be done for each incoming or outgoing IP packet, even if no IPSec processing needs to be applied on it. This may easily result in millions of query per second in gigabit networks. Since the databases may be of several thousands of records on large secure gateways, a dedicated hardware solution is needed to support high throughput. In this paper we discuss an architecture for these query units, we propose different query methods for the two databases, and we compare them through simulation. Two different versions of the architecture are presented: the basic version is modified to support multithreading. As shown by the simulations, this technique is very effective in this case. The architecture that supports multithreading allows for 11 million queries per second in the best case.},
	keywords = {accelerator, database, IPSec, security, security association database (SAD), security policy database (SPD), system-on-chip (SoC), SystemC},
	author = {Ferrante, Alberto and Chandra, Satish and Piuri, Vincenzo}
}
@conference {66.PaMaSi07,
	title = {A Topology Design Customization Approach for (STNoC)},
	booktitle = {Nano-Nets 07, in proceedings of 2nd International Conference on Nano-Networks (Nano-Nets 2007).},
	year = {2007},
	month = {September 24-26},
	address = {Catania, Italy},
	abstract = {To support high bandwidth SoCs, a communication design flow is necessary for the design space exploration respecting tight design requirements. In order to exploit the benefits introduced by the NoC approach for the on-chip communication, the paper presents a design flow for the core mapping and customization of the network topology applied to STNoC, the Network on-Chip developed by STMicroelectronics. Starting from ring topology, the proposed application-specific flow tries to find a set of customized topologies, optimized in terms of performance and area/energy overhead, by adding links. The generated STNoC custom topologies provide a reduced cost with respect to the spidergon topology.},
	keywords = {application specific design, mapping, network-on-chip (NoC), STNoC, topology customization},
	doi = {http://dx.doi.org/10.1109/ASAP.2007.4429959},
	author = {Palermo, Gianluca and Mariani, Giovanni and Silvano, Cristina and Locatelli, Riccardo and Coppola, Marcello}
}
@conference {42.MaChen2006,
	title = {ASIC Hardware Implementation of the IDEA NXT Encryption Algorithm},
	booktitle = {IEEE International Symposium on Circuits and Systems},
	year = {2006},
	month = {May 21-24},
	address = {Kos, Greece},
	abstract = {Symmetric-key block ciphers are often used to provide data confidentiality with low complexity, especially in the case of dedicated hardware implementations. IDEA NXT is a novel block cipher family, which has many interesting features and is targeted to multimedia streaming encryption. Different values can be assigned to the hardware architecture parameters in order to scale the security and the performance of the cipher. In this paper, we implement the IDEA NXT algorithm in custom silicon, using a commercial technology library; different optimizations are applied in order to satisfy different constraints in terms of latency and area occupation, maintaining a high level of security. After giving an overview of the IDEA NXT design, a discussion of the implementation choices and trade offs is given, highlighting the similarities and the main differences with regards to other block ciphers. To the authors{\textquoteright} knowledge this is the first paper describing such work.},
	doi = {http://dx.doi.org/10.1109/ISCAS.2006.1693715},
	author = {Macchetti, Marco and Chen, Wenyu}
}
@conference {45.BoTa2006,
	title = {COOPER: Towards A Collaborative Open Environment of Project-centred Learning},
	booktitle = {proceedings to EC-TEL{\textquoteright}06 conference},
	year = {2006},
	month = {October 1-4},
	address = {Crete, Greece},
	abstract = {Nowadays, engineering studies are characterized by high mobility of students, lecturers and workforce and by the dynamics of multi-national companies where classes or students{\textquoteright} teams composed of persons with different competencies and backgrounds, working together in projects to solve complex problems. Such an environment will become increasingly relevant in multinational universities and companies, and it has brought a number of challenges to existing e-learning technologies. COOPER is an ongoing project that focuses on developing and testing such a collaborative and project-centred leaning environment. This paper proposes a COOPER framework and shows its approaches to address the various research challenges.},
	keywords = {project-centred learning, remote cooperation},
	author = {Bongio, Aldo and Bruggen, Jan and Ceri, Stefano and Cristea, Valentin and Dolog, Peter and Hoffmann, Andreas and Matera, Maristella and Mura, Marzia and Taddeo, Antonio Vincenzo and Zhou, Xuan and Zoni, Larissa}
}
@conference {40.1127983,
	title = {Hardware/software partitioning of operating systems: a behavioral synthesis approach},
	booktitle = {GLSVLSI {\textquoteright}06: Proceedings of the 16th ACM Great Lakes symposium on VLSI},
	year = {2006},
	pages = {324{\textendash}329},
	publisher = {ACM Press, New York, USA},
	organization = {ACM Press, New York, USA},
	address = {Philadelphia, PA, USA},
	abstract = {In this paper we propose a hardware real time operating system(HW-RTOS) solution that makes use of a dedicated hardware in order to replace the standard support provided by the POSIX layer of a general purpose RTOS for implementing task synchronization and scheduling. By redefining only the I/O APIs of the tasks, the HW-RTOS then takes care of the communication requirements of the original application and also implements the task scheduling algorithm. The new software application can then be compiled without any need for POSIX support. The main advantages are smaller and faster executables. We present results that show how a small hardware area, less than 10K gates, can result in a 15X performance improvement when the original software scheduler is replaced by a dedicated HW-RTOS.},
	keywords = {HW/SW co-design, real time operating systems, system-on-chip (SoC)},
	isbn = {1-59593-347-6},
	doi = {http://doi.acm.org/10.1145/1127908.1127983},
	author = {Chandra, Satish and Regazzoni, Francesco and Lajolo, Marcello}
}
@conference {3.CaPoMaMaBeBreFra2001,
	title = {Efficient C implementation of the ECC and AES cryptographic systems},
	booktitle = {Technology Leadership Day - organized by the MicroSwiss Network},
	year = {2001},
	month = {October 10},
	address = {Fribourg},
	author = {Cassoli, Federico and Polloni, Flavio and Marchesin, Stefano and Macchetti, Marco and Bertoni, Guido Marco and Breveglieri, Luca and Fragneto, Pasqualina}
}
