@conference {18.969266, title = {The Design of a High Speed ASIC Unit for the Hash Function SHA-256 (384,512)}, booktitle = {DATE {\textquoteright}04: Proceedings of the conference on Design, automation and test in Europe}, year = {2004}, pages = {30070}, publisher = {IEEE Computer Society}, organization = {IEEE Computer Society}, address = {Washington, DC, USA}, abstract = {After recalling the basic algorithms published by NIST for implementing the hash functions SHA-256 (384, 512), a basic circuit characterized by a cascade of full adder arrays is given. Implementation options are discussed and two methods for improving speed are exposed: the delay balancing and the pipelining. An application of the former is first given, obtaining a circuit that reduces the length of the critical path by a full adder array. A pipelined version is then given, obtaining a reduction of two full adder arrays in the critical path. The two methods are afterwards combined and the results obtained through hardware synthesis are exposed, where a comparison between the new circuits is also given.}, isbn = {0-7695-2085-5-3}, doi = {http://dx.doi.org/10.1109/DATE.2004.1269207}, author = {Dadda, Luigi and Macchetti, Marco and Owen, Jeff} }