@Patent {18589,
	title = {Reconfigurable Logic Circuit},
	number = {GB1719355.8},
	year = {Submitted},
	month = {11/2017},
	type = {UK},
	author = {Mentens, Nele and Charbon, Edoardo and Regazzoni, Francesco}
}
@article {18591,
	title = {Black-Hat High-Level Synthesis: Myth or Reality?},
	journal = {IEEE Transactions on Very Large Scale Integration Systems},
	year = {In Press},
	doi = {10.1109/TVLSI.2018.2884742},
	author = {Pilato, Christian and Basu, Kanad and Regazzoni, Francesco and Karri, Ramesh}
}
@article {18569,
	title = {Compact Circuits for Combined AES},
	journal = {Journal of Cryptographic Engineering},
	year = {In Press},
	author = {Banik, Subhadeep and Bogdanov, Andrey and Regazzoni, Francesco}
}
@article {18567,
	title = {Customized Instructions for Protection Against Memory Integrity Attacks},
	journal = {IEEE Embedded Systems Letters},
	year = {In Press},
	author = {Roy, Debapriya Basu and Alam, Manaar and Bhattacharya, Sarani and Govindan, Vidya and Regazzoni, Francesco and Chakraborty, Rajat Subhra and Mukhopadhyay, Debdeep}
}
@article {18553,
	title = {Enabling Automated Bug Detection for IP-based Designs using High-Level Synthesis},
	journal = {IEEE Design \& Test},
	year = {In Press},
	month = {2018},
	doi = {10.1109/MDAT.2018.2824121},
	author = {Fezzardi, Pietro and Pilato, Christian and Ferrandi, Fabrizio}
}
@article {18570,
	title = {On Practical Discrete Gaussian Samplers For Lattice-Based Cryptography},
	journal = {IEEE Transaction on Computers},
	year = {In Press},
	author = {Howe, James and Khalid, Ayesha and Rafferty, Ciara and Regazzoni, Francesco and O{\textquoteright}Neill, Maire}
}
@article {18552,
	title = {TaintHLS: High-Level Synthesis For Dynamic Information Flow Tracking},
	journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
	year = {In Press},
	doi = {10.1109/TCAD.2018.2834421},
	author = {Pilato, Christian and Garg, Siddharth and Wu, Kaijie and Karri, Ramesh and Regazzoni, Francesco}
}
@article {18568,
	title = {Towards Low Energy Stream Ciphers},
	journal = {IACR Transactions on Symmetric Cryptology},
	year = {In Press},
	author = {Banik, Subhadeep and Mikhalev, Vasily and Armknecht, Frederik and Isobe, Takanori and Meier, Willi and Bogdanov, Andrey and Watanabe, Yuhei and Regazzoni, Francesco}
}
@conference {18590,
	title = {High-Level Synthesis of Benevolent Trojans},
	booktitle = {Proceedings of the IEEE Design, Automation and Test in Europe Conference (DATE)},
	year = {2019},
	author = {Pilato, Christian and Basu, Kanad and Shayan, Mohammed and Regazzoni, Francesco and Karri, Ramesh}
}
@conference {18595,
	title = {Power and Performance Optimized Hardware Classifiers for Eefficient On-device Malware Detection},
	booktitle = {Cryptography and Security in Computing Systems},
	year = {2019},
	month = {01/2019},
	publisher = {ACM},
	organization = {ACM},
	address = {Valencia, Spain},
	author = {Wahab, Muhammad Abdul and Milosevic, Jelena and Regazzoni, Francesco and Ferrante, Alberto}
}
@article {18594,
	title = {Time, Accuracy and Power Consumption Tradeoff in Mobile Malware Detection Systems},
	journal = {Computers \& Security},
	volume = {82},
	year = {2019},
	month = {05/2019},
	pages = {314-328},
	chapter = {314},
	issn = {01674048},
	doi = {https://doi.org/10.1016/j.cose.2019.01.001},
	author = {Milosevic, Jelena and Malek, Miroslaw and Ferrante, Alberto}
}
@article {18547,
	title = {Anomaly and Change Detection in Graph Streams through Constant-Curvature Manifold Embeddings},
	journal = {IJCNN 2018 : International Joint Conference on Neural Networks},
	year = {2018},
	month = {07/2018},
	author = {Zambon, Daniele and Livi, Lorenzo and Alippi, Cesare}
}
@conference {18592,
	title = {Arbon Demonstrator Eye-on-the-Grid, from Concept to Results},
	booktitle = {SCCER-FURIES Annual Conference},
	year = {2018},
	month = {12/2018},
	url = {https://sccer-furies.epfl.ch/wp-content/uploads/2019/01/Arbon-demo-FURIES-Annual-meeting.pdf},
	author = {Lukovi{\'c}, Slobodan and Gasparin, Alberto and Witzig, Jens and Herbst, Ingo}
}
@book {18544,
	title = {Artificial Intelligence in the Age of Neural Networks and Brain Computing},
	series = {Academic Press },
	year = {2018},
	pages = {420},
	edition = {1},
	abstract = {Artificial Intelligence in the Age of Neural Networks and Brain Computing demonstrates that existing disruptive implications and applications of AI is a development of the unique attributes of neural networks, mainly machine learning, distributed architectures, massive parallel processing, black-box inference, intrinsic nonlinearity and smart autonomous search engines. The book covers the major basic ideas of brain-like computing behind AI, provides a framework to deep learning, and launches novel and intriguing paradigms as future alternatives. The success of AI-based commercial products proposed by top industry leaders, such as Google, IBM, Microsoft, Intel and Amazon can be interpreted using this book. },
	author = {Kozma, Robert and Alippi, Cesare and Choe, Yoonsuck and Morabito, Francesco}
}
@conference {18556,
	title = {Bridging the Gap between Software and Hardware Designers Using High-Level Synthesis},
	booktitle = {Advances in Parallel Computing},
	year = {2018},
	doi = {10.3233/978-1-61499-843-3-622},
	author = {Pilato, Christian}
}
@article {18549,
	title = {The Case for Polymorphic Registers in Dataflow Computing},
	journal = {International Journal of Parallel Programming},
	volume = {54},
	issue = {5},
	year = {2018},
	month = {10/2018},
	pages = {54-62},
	chapter = {54},
	doi = {10.1007/s10766-017-0494-1},
	author = {Ciobanu, Catalin B. and Gaydadjiev, Georgi and Pilato, Christian and Sciuto, Donatella}
}
@conference {18593,
	title = {A characterization of the Edge of Criticality in Binary Echo State Networks},
	booktitle = {2018 IEEE 28th International Workshop on Machine Learning for Signal Processing (MLSP)},
	year = {2018},
	month = {09/2018},
	address = {Aalborg, Denmark},
	author = {Verzelli, Pietro and Livi, Lorenzo and Alippi, Cesare}
}
@conference {18573,
	title = {Compact, Scalable, and Efficient Gaussian Samplers for Lattice-Based Cryptography},
	booktitle = {Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) 2018},
	year = {2018},
	author = {Khalid, Ayesha and Howe, James and Rafferty, Ciara and Regazzoni, Francesco and O{\textquoteright}Neil, Maire}
}
@article {18545,
	title = {Concept Drift and Anomaly Detection in Graph Streams},
	journal = {IEEE Transactions on Neural Networks and Learning Systems},
	volume = {29},
	issue = {11},
	year = {2018},
	month = {11/2018},
	pages = {5592-5605},
	chapter = {5592},
	author = {Zambon, Daniele and Alippi, Cesare and Livi, Lorenzo}
}
@article {18536,
	title = {Credit Card Fraud Detection: A Realistic Modeling and a Novel Learning Strategy},
	journal = {IEEE Transactions on Neural Networks and Learning Systems},
	year = {2018},
	pages = {1-14},
	keywords = {Amplitude modulation, Area measurement, Companies, Concept drift, Credit card fraud detection, Credit cards, learning in nonstationary environments, Learning systems, Tools, Training, unbalanced classification.},
	issn = {2162-237X},
	doi = {10.1109/TNNLS.2017.2736643},
	author = {Dal Pozzolo, Andrea and Boracchi, Giacomo and Caelen, Olivier and Alippi, Cesare and Bontempi, Gianluca}
}
@conference {18551,
	title = {Dark{M}em: Fine-Grained Power Management of Local Memories for Accelerators in Embedded Systems},
	booktitle = {Proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC)},
	year = {2018},
	doi = {10.1109/ASPDAC.2018.8297403},
	author = {Pilato, Christian and Carloni, Luca P.}
}
@article {18533,
	title = {Determination of the Edge of Criticality in Echo State Networks Through Fisher Information Maximization},
	journal = {IEEE Transactions on Neural Networks and Learning Systems},
	volume = {29},
	year = {2018},
	month = {March},
	pages = {706-717},
	keywords = {Echo state network (ESN), echo state networks, edge of criticality, ESN, Fisher information, Fisher information matrix, Fisher information maximization, Jacobian matrices, Learning systems, Neurons, nonparametric estimation, nonparametric estimator, nonparametric statistics, prediction error, Probability density function, recurrent neural nets, recurrent neural networks, Reservoirs, RNN, short-term memory capacity, Training},
	issn = {2162-237X},
	doi = {10.1109/TNNLS.2016.2644268},
	author = {Livi, Lorenzo and Bianchi, Filippo Maria and Alippi, Cesare}
}
@conference {18577,
	title = {Efficient Configurations for Block Ciphers with Unified ENC/DEC Paths},
	booktitle = {Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust (HOST) 2017},
	year = {2018},
	author = {Banik, Subhadeep and Bogdanov, Andrey and Regazzoni, Francesco}
}
@conference {18559,
	title = {Exploring the Vulnerability of R-LWE Encryption to Fault Attacks},
	booktitle = {Workshop on Cryptography and Security in Computing Systems of the HiPEAC2018 Conference, CS2 {\textquoteright}18},
	year = {2018},
	publisher = {ACM},
	organization = {ACM},
	address = {New York, NY, USA},
	author = {Valencia, Felipe and Oder, Tobias and G{\"u}neysu, Tim and Regazzoni, Francesco}
}
@inbook {18529,
	title = {Extinguishing Ransomware - A Hybrid Approach to Android Ransomware Detection},
	booktitle = {Foundations and Practice of Security},
	volume = {10723},
	year = {2018},
	month = {02/2018},
	pages = {242-258},
	publisher = {Springer International Publishing},
	organization = {Springer International Publishing},
	address = {Cham},
	abstract = {Mobile ransomware is on the rise and effective defense from it is of utmost importance to guarantee security of mobile users{\textquoteright} data. Current solutions provided by antimalware vendors are signature-based and thus ineffective in removing ransomware and restoring the infected devices and files. Also, current state-of-the art literature offers very few solutions to effectively detecting and blocking mobile ransomware. Starting from these considerations, we propose a hybrid method able to effectively counter ransomware. The proposed method first examines applications to be used on a device prior to their installation (static approach) and then observes their behavior at runtime and identifies if the system is under attack (dynamic approach). To detect ransomware, the static detection method uses the frequency of opcodes while the dynamic detection method considers CPU usage, memory usage, network usage and system call statistics. We evaluate the performance of our hybrid detection method on a dataset that contains both ransomware and legitimate applications. Additionally, we evaluate the performance of the static and dynamic stand-alone methods for comparison. Our results show that although both static and dynamic detection methods perform well in detecting ransomware, their combination in a form of a hybrid method performs best, being able to detect ransomware with 100{\%} precision and having a false positive rate of less than 4{\%}.},
	isbn = {978-3-319-75650-9},
	doi = {https://doi.org/10.1007/978-3-319-75650-9_16},
	author = {Ferrante, Alberto and Malek, Miroslaw and Martinelli, Fabio and Mercaldo, Francesco and Milosevic, Jelena},
	editor = {Imine, Abdessamad and Fernandez, Jos{\'e} M. and Marion, Jean-Yves and Logrippo, Luigi and Garcia-Alfaro, Joaquin}
}
@article {18566,
	title = {Impact of Failure Prediction on Availability: Modeling and Comparative Analysis of Predictive and Reactive Methods},
	journal = {IEEE Transactions on Dependable and Secure Computing},
	year = {2018},
	pages = {1-1},
	abstract = {Predicting failures and acting proactively have a potential to improve availability as a correct prediction and a successful mitigation may bring a reward resulting in decrease of downtime and availability improvement. But, conversely, each incorrect prediction may introduce additional downtime (penalty). Therefore, depending on the quality of prediction and the system parameters, predictive fault-tolerance methods may improve or may degrade availability in comparison to the reactive ones. We first derive taxonomies of fault-tolerant techniques and policies to differentiate between reactive and proactive policies that are further classified as systematic and predictive. To evaluate whether a predictive policy improves availability or not, we derive an analytical model for availability quantification. We use Markov chains to extend steady-state availability equation to include: precision and recall, penalty and reward, mitigation success probability and potential failure rate increase due to the prediction load. We also derive A-measure to optimize failure prediction for increasing availability. In our conclusion, precision and recall have comparable impact on availability as changing MTTF and MTTR. To validate the model we also simulate and analyze availability of a virtualized server with exponential distribution of failure and repair rates.},
	keywords = {Analytical models, availability, Computational modeling, failure, fault tolerance, Fault tolerant systems, Mathematical model, modeling, Optimization, prediction, predictive, Predictive models, proactive, Servers},
	issn = {1545-5971},
	doi = {10.1109/TDSC.2018.2806448},
	author = {Kaitovi{\'c}, Igor and Malek, Miroslaw}
}
@conference {18574,
	title = {Inverse Gating for Low Energy Block Ciphers},
	booktitle = {Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust (HOST)},
	year = {2018},
	author = {Banik, Subhadeep and Bogdanov, Andrey and Isobe, Takanori and Hiwatari, Harunaga and Akishita, Toru and Regazzoni, Francesco}
}
@article {18508,
	title = {Investigating echo state networks dynamics by means of recurrence analysis},
	journal = {IEEE Transactions on Neural Networks and Learning Systems},
	volume = {29},
	year = {2018},
	month = {02/2018},
	pages = { 427 - 439},
	abstract = {In this paper, we elaborate over the well-known
interpretability issue in echo state networks. The idea is to investigate
the dynamics of reservoir neurons with time-series analysis
techniques taken from research on complex systems. Notably, we
analyze time-series of neuron activations with Recurrence Plots
(RPs) and Recurrence Quantification Analysis (RQA), which
permit to visualize and characterize high-dimensional dynamical
systems. We show that this approach is useful in a number of
ways. First, the two-dimensional representation offered by RPs
provides a way for visualizing the high-dimensional dynamics of
a reservoir. Our results suggest that, if the network is stable,
reservoir and input denote similar line patterns in the respective
RPs. Conversely, the more unstable the ESN, the more the RP
of the reservoir presents instability patterns. As a second result,
we show that the Lmax measure is highly correlated with the
well-established maximal local Lyapunov exponent. This suggests
that complexity measures based on RP diagonal lines distribution
provide a valuable tool to quantify the degree of network stability.
Finally, our analysis shows that all RQA measures fluctuate on
the proximity of the so-called edge of stability, where an ESN
typically achieves maximum computational capability. We verify
that the determination of the edge of stability provided by such
RQA measures is more accurate than two well-known criteria
based on the Jacobian matrix of the reservoir. Therefore, we
claim that RPs and RQA-based analyses can be used as valuable
tools to design an effective network given a specific problem.},
	doi = {10.1109/TNNLS.2016.2630802},
	author = {Bianchi, Filippo Maria and Livi, Lorenzo and Alippi, Cesare}
}
@conference {18546,
	title = {Moving Convolutional Neural Networks to Embedded Systems: The Alexnet and VGG-16 Case},
	booktitle = {Proceedings of the 17th ACM/IEEE International Conference on Information Processing in Sensor Networks},
	year = {2018},
	publisher = {IEEE Press},
	organization = {IEEE Press},
	address = {Piscataway, NJ, USA},
	keywords = {approximate computing, convolutional neural networks, deep learning, embedded systems},
	isbn = {978-1-5386-5298-5},
	doi = {10.1109/IPSN.2018.00049},
	url = {https://doi.org/10.1109/IPSN.2018.00049},
	author = {Alippi, Cesare and Disabato, Simone and Roveri, Manuel}
}
@conference {18548,
	title = {Panel IoT and pervasive computing: are new definitions of security and privacy needed?},
	booktitle = {Malicious Software and Hardware in Internet of Things Co-located with ACM International Conference on Computing Frontiers 2018},
	year = {2018},
	month = {05/2018},
	address = {Ischia, Naples, Italy},
	author = {Ferrante, Alberto},
	editor = {Palmieri, Paolo}
}
@article {18512,
	title = {A Pdf-free Change Detection Test Based on Density Difference Estimation},
	journal = {IEEE Transactions on Neural Networks and Learning Systems},
	volume = {29},
	issue = {2},
	year = {2018},
	month = {11/2016},
	pages = { 324 - 334},
	chapter = {324},
	abstract = {The ability to detect 1 online changes in stationarity or time variance in a data stream is a hot research topic with striking implications. In this paper, we propose a novel probability density function-free change detection test, which is based on the least squares density-difference estimation method and operates online on multidimensional inputs. The test does not require any assumption about the underlying data distribution, and is able to operate immediately after having been configured by adopting a reservoir sampling mechanism. Thresholds requested to detect a change are automatically derived once a false positive rate is set by the application designer. Comprehensive experiments validate the effectiveness in detection of the proposed method both in terms of detection promptness and accuracy.},
	doi = {10.1109/TNNLS.2016.2619909},
	author = {Bo, Li and Alippi, Cesare and Zhao, Dongbin}
}
@conference {18585,
	title = {Quantum Era Challenges for Classical Computers},
	booktitle = {Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation},
	year = {2018},
	publisher = {ACM},
	organization = {ACM},
	address = {New York, NY, USA},
	isbn = {978-1-4503-6494-2},
	doi = {10.1145/3229631.3264737},
	url = {http://doi.acm.org/10.1145/3229631.3264737},
	author = {Regazzoni, Francesco and Fowler, Austin and Polian, Ilia}
}
@conference {18575,
	title = {Rethinking Secure FPGAs: TowardsCryptography-friendly Configurable Cell Architecture and its Automated Design Flow},
	booktitle = {Proceedings of FCCM},
	year = {2018},
	month = {05/2018},
	author = {Mentens, Nele and Charbon, Edoardo and Regazzoni, Francesco}
}
@conference {18588,
	title = {SCA-Resistance for AES: How Cheap Can We Go?},
	booktitle = {Progress in Cryptology {\textendash} AFRICACRYPT 2018},
	year = {2018},
	publisher = {Springer International Publishing},
	organization = {Springer International Publishing},
	address = {Cham},
	abstract = {This paper introduces a novel AES structure capable of improving the robustness against power analysis attacks while allowing for a very compact structure with a potentially negligible area and performance impact. The proposed design is based on a low entropy masking scheme, where half of the time the true value and half of the time the complemented value are used to mask the power consumption variation. The obtained experimental results suggest that the area overhead for the protection against power analysis is as low as 5{\%} LUT increase with a performance degradation of about 10{\%}. When compared with the state of the art supported on FPGAs, efficiency improvements above 6 times and a throughput improvement of at least two times higher are achieved.},
	isbn = {978-3-319-89339-6},
	author = {Chaves, Ricardo and Chmielewski, {\L}ukasz and Regazzoni, Francesco and Batina, Lejla},
	editor = {Joux, Antoine and Nitaj, Abderrahmane and Rachidi, Tajjeeddine}
}
@article {18554,
	title = {Securing Hardware Accelerators: a New Challenge for High-Level Synthesis},
	journal = {IEEE Embedded Systems Letters},
	volume = {3},
	issue = {10},
	year = {2018},
	month = {11/2017},
	pages = {77-80},
	chapter = {77},
	doi = {10.1109/LES.2017.2774800},
	author = {Pilato, Christian and Garg, Siddharth and Karri, Ramesh and Regazzoni, Francesco}
}
@conference {18584,
	title = {Security: The Dark Side of Approximate Computing?},
	booktitle = {Proceedings of the International Conference on Computer-Aided Design},
	year = {2018},
	month = {11/2018},
	publisher = {ACM},
	organization = {ACM},
	address = {New York, NY, USA},
	isbn = {978-1-4503-5950-4},
	doi = {10.1145/3240765.3243497},
	url = {http://doi.acm.org/10.1145/3240765.3243497},
	author = {Regazzoni, Francesco and Alippi, Cesare and Polian, Ilia}
}
@conference {18555,
	title = {TAO: Techniques for Algorithmic Obscuration during High-Level Synthesis},
	booktitle = {Proceedings of the ACM/IEEE Design Automation Conference (DAC)},
	year = {2018},
	doi = {10.1145/3195970.3196126},
	author = {Pilato, Christian and Regazzoni, Francesco and Karri, Ramesh and Garg, Siddharth}
}
@conference {18530,
	title = {Time series kernel similarities for predicting Paroxysmal Atrial Fibrillation from ECGs},
	booktitle = { IJCNN 2018 : International Joint Conference on Neural Networks},
	year = {2018},
	month = {07/2018},
	publisher = {IEEE},
	organization = {IEEE},
	address = {Rio, Brazil},
	author = {Bianchi, Filippo Maria and Livi, Lorenzo and Ferrante, Alberto and Milosevic, Jelena and Malek, Miroslaw}
}
@conference {18538,
	title = {Critical echo state network dynamics by means of Fisher information maximization},
	booktitle = {2017 International Joint Conference on Neural Networks (IJCNN)},
	year = {2017},
	month = {May},
	keywords = {Asymptotic stability, critical phase transitions, echo state network, edge of criticality, Electronic mail, ESN, Estimation, estimation theory, FIM, Fisher information matrix, Fisher information maximization, hidden neurons activations, high short term memory capacity, input signal, low prediction error, network dynamics, network theory (graphs), Neurons, optimisation, Probability density function, recurrent neural nets, Reservoirs, signal processing, statistics, Tuning, unsupervised approach, unsupervised learning},
	doi = {10.1109/IJCNN.2017.7965941},
	author = {Bianchi, Filippo Maria and Livi, Lorenzo and Jenssen, Robert and Alippi, Cesare}
}
@conference {18581,
	title = {Cross-layer Design of Reconfigurable Cyber-Physical Systems},
	booktitle = {Proceedings of Design, Automation and Test in Europe (DATE) 2017},
	year = {2017},
	author = {Masin, Michael and Palumbo, Francesca and Myrhaug, Hans and Filho, Julio A. de Oliv and Pastena, Max and Pelcat, Maxime and Raffo, Luigi and Regazzoni, Francesco and Sanchez, Angel A. and Toffetti, Antonella and de la Torre, Eduardo and Zedda, Katiuscia}
}
@conference {18560,
	title = {The design space of the number theoretic transform: {A} survey},
	booktitle = {2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, {SAMOS} 2017, Pythagorion, Greece, July 17-20, 2017 (Invited)},
	year = {2017},
	doi = {10.1109/SAMOS.2017.8344640},
	url = {https://doi.org/10.1109/SAMOS.2017.8344640},
	author = {Valencia, Felipe and Khalid, Ayesha and O{\textquoteright}Sullivan, Elizabeth and Regazzoni, Francesco}
}
@conference {18539,
	title = {Detecting changes at the sensor level in cyber-physical systems: Methodology and technological implementation},
	booktitle = {2017 International Joint Conference on Neural Networks (IJCNN)},
	year = {2017},
	month = {May},
	keywords = {actuators, adaptation mechanisms, adaptive systems, Change detection, change-point method, Computational modeling, cyber-physical systems, datastreams, fault detection and diagnosis, fault tolerant computing, ICI-based change detection test, Intelligence for Embedded and Cyber-physical Systems, Mann-Whitney change-point method, Mathematical model, model-free change detection test, Predictive models, Random variables, self-adaptive CPS, self-adaptive cyber-physical systems, self-configuration, self-healing skills, self-management, sensor acquisitions, sensor level, sensors, signal detection, Smart Sensor Networks, ST STM32 Nucleo platform, time-variant environments, Training},
	doi = {10.1109/IJCNN.2017.7966066},
	author = {Alippi, Cesare and D{\textquoteright}Alto, Viviana and Falchetto, Mirko and Pau, Danilo and Roveri, Manuel}
}
@conference {18542,
	title = {Detecting changes in sequences of attributed graphs},
	booktitle = {2017 IEEE Symposium Series on Computational Intelligence (SSCI)},
	year = {2017},
	month = {Nov},
	keywords = {Aerospace electronics, Anomaly detection, application domains, Attributed graph, attributed graphs, Change detection, Concept drift, Dynamic/Evolving graph, Electronic mail, Embedding, geometric graphs, Graph matching, graph theory, graph-based representations, Markov chains, Markov processes, Microsoft Windows, pair-wise relations, Prototypes, real-world systems, Stationarity, topology, Training, variable order},
	doi = {10.1109/SSCI.2017.8285273},
	author = {Zambon, Daniele and Livi, Lorenzo and Alippi, Cesare}
}
@inbook {18571,
	title = {Fault Attacks, Injection Techniques and Tools for Simulation},
	booktitle = {Hardware Security and Trust: Design and Deployment of Integrated Circuits in a Threatened Environment},
	year = {2017},
	pages = {149-167},
	publisher = {Springer},
	organization = {Springer},
	edition = {First edition; 2016},
	author = {Piscitelli, Roberta and Bhasin, Shivam and Regazzoni, Francesco}
}
@inbook {18572,
	title = {Hardware Security and Trust: Design and Deployment of Integrated Circuits in a Threatened Environment},
	year = {2017},
	publisher = {Springer},
	organization = {Springer},
	edition = {First edition; 2016},
	author = {Sklavos, Nicolas and Chaves, Ricardo and Di Natale, Giorgio and Regazzoni, Francesco}
}
@article {18535,
	title = {An Incremental Change Detection Test Based on Density Difference Estimation},
	journal = {IEEE Transactions on Systems, Man, and Cybernetics: Systems},
	volume = {47},
	year = {2017},
	month = {Oct},
	pages = {2714-2726},
	keywords = {Big data framework, Change detection, change detection method, density difference estimation, Estimation, false positive rates, Feature extraction, Histograms, incremental change detection test, incremental computing, incremental least squares density difference change detection method (LSDD-Inc), Internet of Things, Kernel, least squares approximations, least squares density difference, linear combination, LSDD, LSDD values, nonoverlapping data windows, probability, Probability density function, probability density function (pdf)-free, probability density functions, process continuous data streams, Training},
	issn = {2168-2216},
	doi = {10.1109/TSMC.2017.2682502},
	author = {Bu, Li and Zhao, Dongbin and Alippi, Cesare}
}
@article {18561,
	title = {An Investigation of Sources of Randomness Within Discrete Gaussian Sampling},
	journal = {IACR Cryptology ePrint Archive},
	volume = {2017},
	year = {2017},
	pages = {298},
	author = {Brannigan, S{\'e}amus and Smyth, Neil and Oder, Tobias and Valencia, Felipe and O{\textquoteright}Sullivan, Elizabeth and G{\"u}neysu, Tim and Regazzoni, Francesco}
}
@article {18540,
	title = {A Kolmogorov-Smirnov Test to Detect Changes in Stationarity in Big Data},
	journal = {IFAC-PapersOnLine},
	volume = {50},
	year = {2017},
	pages = {14260 - 14265},
	abstract = {The paper proposes an effective change detection test for online monitoring data streams by inspecting the least squares density difference (LSDD) features extracted from two non-overlapped windows. The first window contains samples associated with the pre-change probability distribution function (pdf) and the second one with the post-change one (that differs from the former if a change in stationarity occurs). This method can detect changes by also controlling the false positive rate. However, since the window sizes is fixed after the test has been configured (it has to be small to reduce the execution time), the method may fail to detect changes with small magnitude which need more samples to reach the requested level of confidence. In this paper, we extend our work to the Big Data framework by applying the Kolmogorov-Smirnov test (KS test) to infer changes. Experiments show that the proposed method is effective in detecting changes.},
	keywords = {change detection test, KS test, LSDD},
	issn = {2405-8963},
	doi = {https://doi.org/10.1016/j.ifacol.2017.08.1821},
	url = {http://www.sciencedirect.com/science/article/pii/S2405896317324436},
	author = {Zhao, Dongbin and Bu, Li and Alippi, Cesare and Wei, Qinglai}
}
@conference {18541,
	title = {Learning in Nonstationary Environments: A Hybrid Approach},
	booktitle = {Artificial Intelligence and Soft Computing},
	year = {2017},
	publisher = {Springer International Publishing},
	organization = {Springer International Publishing},
	address = {Cham},
	abstract = {Solutions present in the literature to learn in nonstationary environments can be grouped into two main families: passive and active. Passive solutions rely on a continuous adaptation of the envisaged learning system, while the active ones trigger the adaptation only when needed. Passive and active solutions are somehow complementary and one should be preferred than the other depending on the nonstationarity rate and the tolerable computational complexity. The aim of this paper is to introduce a novel hybrid approach that jointly uses an adaptation mechanism (as in passive solutions) and a change detection triggering the need to retrain the learning system (as in active solutions).},
	isbn = {978-3-319-59060-8},
	author = {Alippi, Cesare and Qi, Wen and Roveri, Manuel},
	editor = {Rutkowski, Leszek and Korytkowski, Marcin and Scherer, Rafa{\l} and Tadeusiewicz, Ryszard and Zadeh, Lotfi A. and Zurada, Jacek M.}
}
@conference {18537,
	title = {A lightweight and energy-efficient Internet-of-birds tracking system},
	booktitle = {2017 IEEE International Conference on Pervasive Computing and Communications (PerCom)},
	year = {2017},
	month = {March},
	keywords = {animal movement tracking, application server, Birds, cellular radio, cloud computing, energy assessment, energy conservation, energy consumption, energy efficient Internet-of-birds tracking system, GSM, GSM-based tracking device energy consumption reduction, Internet of Things, Internet-of-things vision, joint localization-transmission phase, Northern Italy, quality of service, Radar tracking, Receivers, Satellites, telecommunication power management, Tracking, Transmitters},
	doi = {10.1109/PERCOM.2017.7917862},
	author = {Alippi, Cesare and Ambrosini, Roberto and Longoni, Violetta and Cogliati, Dario and Roveri, Manuel}
}
@inbook {18466,
	title = {Malware Threats and Solutions for Trustworthy Mobile Systems Design},
	booktitle = {Hardware Security and Trust: Design and Deployment of Integrated Circuits in a Threatened Environment},
	year = {2017},
	pages = {149-167},
	publisher = {Springer},
	organization = {Springer},
	edition = {First edition; 2016},
	keywords = {malware, mobile systems, security metric, trusting},
	doi = {https://doi.org/10.1007/978-3-319-44318-8_8},
	author = {Milosevic, Jelena and Regazzoni, Francesco and Malek, Miroslaw}
}
@article {18531,
	title = {Model-Free Fault Detection and Isolation in Large-Scale Cyber-Physical Systems},
	journal = {IEEE Transactions on Emerging Topics in Computational Intelligence},
	volume = {1},
	year = {2017},
	month = {Feb},
	pages = {61-71},
	keywords = {Change detection algorithms, clustering methods, Computational modeling, cyber-physical systems, Fault detection, Hidden Markov models, monitoring, Sensor phenomena and characterization, Sensor systems},
	doi = {10.1109/TETCI.2016.2641452},
	author = {Alippi, Cesare and Ntalampiras, Stavros and Roveri, Manuel}
}
@article {18532,
	title = {Multiplex visibility graphs to investigate recurrent neural network dynamics},
	journal = {Nature-Scientific reports},
	volume = {7},
	year = {2017},
	month = {03/2017},
	pages = {44037-44049},
	chapter = {44037},
	doi = {doi:10.1038/srep44037},
	author = {Bianchi, Filippo Maria and Livi, Lorenzo and Alippi, Cesare and Jenssen, Robert}
}
@article {18534,
	title = {The (Not) Far-Away Path to Smart Cyber-Physical Systems: An Information-Centric Framework},
	journal = {Computer},
	volume = {50},
	year = {2017},
	month = {April},
	pages = {38-47},
	keywords = {adaptive systems, autonomic computing, communication technologies, CPSs, cyber-physical systems, cybersecurity, embedded systems, Energy management, fault detection and diagnosis, Fault diagnosis, Green computing, homogeneous integrated framework, information-centric framework, intelligent functionalities, Intelligent sensors, Intelligent systems, Internet of Things, IoT, learning (artificial intelligence), low-cost sensors, security, smart cyber-physical systems, smart technology},
	issn = {0018-9162},
	doi = {10.1109/MC.2017.111},
	author = {Alippi, Cesare and Roveri, Manuel}
}
@article {18510,
	title = {One-class classifiers based on entropic spanning graphs},
	journal = {IEEE Transactions on Neural Networks and Learning Systems},
	volume = {28},
	issue = {12},
	year = {2017},
	month = {11/2016},
	pages = { 2846 - 2858},
	chapter = {2846},
	abstract = {One-class classifiers offer valuable tools to assess the presence of outliers in data. In this paper, we propose a design methodology for one-class classifiers based on entropic spanning graphs. The spanning graph is learned on the embedded input data, with the aim to generate a partition of the vertices.
The final partition is derived by exploiting a criterion based on mutual information minimization. Here, we compute the mutual information by using a convenient formulation provided in terms of the alfa-Jensen difference. Once training is completed, in order to associate a confidence level with the classifier decision, a graph-based fuzzy model is constructed. The fuzzification process is based only on topological information of the vertices of the entropic spanning graph. As such, the proposed one-class classifier is suitable also for datasets with complex geometric structures. We provide experiments on well-known benchmarking datasets containing both feature vectors and labeled graphs. In addition, we apply the method on the problem of protein solubility recognition by considering several data representations for the samples. Experimental results demonstrate the effectiveness and versatility of the proposed method with respect to other state-of the-art approaches.
},
	doi = { 10.1109/TNNLS.2016.2608983},
	author = {Livi, Lorenzo and Alippi, Cesare}
}
@conference {18582,
	title = {Predictive Analytics: A Shortcut to Dependable Computing},
	booktitle = {Software Engineering for Resilient Systems},
	year = {2017},
	publisher = {Springer International Publishing},
	organization = {Springer International Publishing},
	address = {Cham},
	abstract = {The paper lists three major issues: complexity, time and uncertainty, and identifies dependability as the permanent challenge. In order to enhance dependability, the paradigm shift is proposed where focus is on failure prediction and early malware detection. Failure prediction methodology, including modeling and failure mitigation, is presented and two case studies (failure prediction for computer servers and early malware detection) are described in detail. The proposed approach, using predictive analytics, may increase system availability by an order of magnitude or so.},
	isbn = {978-3-319-65948-0},
	author = {Malek, Miroslaw},
	editor = {Romanovsky, Alexander and Troubitsyna, Elena A.}
}
@inbook {18521,
	title = {Runtime Classification of Mobile Malware for Resource-constrained Devices},
	booktitle = {Lecture Notes in Communications in Computer and Information Science},
	volume = {764},
	year = {2017},
	pages = {195-215},
	publisher = { Springer International Publishing AG},
	organization = { Springer International Publishing AG},
	doi = {https://doi.org/10.1007/978-3-319-67876-4_10},
	author = {Milosevic, Jelena and Malek, Miroslaw and Ferrante, Alberto}
}
@article {18509,
	title = {Solving Multiobjective Optimization Problems in Unknown Dynamic Environments: An Inverse Modeling Approach},
	journal = {IEEE Transactions on Cybernetics},
	volume = {47},
	issue = {12},
	year = {2017},
	month = {11/2016},
	pages = {4223 - 4234},
	chapter = {4223},
	abstract = {Evolutionary multiobjective optimization in dynamic environments is a challenging task, as it requires the optimization algorithm converging to a time-variant Pareto optimal front. This paper proposes a dynamic multiobjective optimization algorithm which utilizes an inverse model set to guide the search towards promising decision regions. In order to reduce the number of fitness evaluations for change detection purpose, a two stage change detection test is proposed which uses the inverse model set to check potential changes in the objective function landscape. Both static and dynamic multiobjective benchmark optimization problems have been considered to evaluate the performance of the proposed algorithm. Experimental results show that the improvement in optimization performance is achievable when the proposed inverse model set is adopted.},
	doi = {10.1109/TCYB.2016.2602561},
	author = {Gee, Sen Bong and Tan, Kay Chen and Alippi, Cesare}
}
@conference {18576,
	title = {Special Session Paper: Efficient Arithmetic for lattice-based Cryptography},
	booktitle = {Proceedings of the CODES+ISSS 2017},
	year = {2017},
	author = {O{\textquoteright}Sullivan, Elizabeth and Regazzoni, Francesco}
}
@article {18550,
	title = {System-Level Optimization of Accelerator Local Memory for Heterogeneous Systems-on-Chip},
	journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
	volume = {36},
	year = {2017},
	pages = {435-448},
	keywords = {algorithm design and analysis, Data structures, hardware, hardware accelerator, High-Level Synthesis, IP networks, Memory Design, Memory management, Multi-bank Architecture, Random access memory},
	doi = {10.1109/TCAD.2016.2611506},
	author = {Pilato, Christian and Mantovani, Paolo and Di Guglielmo, Giuseppe and Carloni, Luca P.}
}
@conference {18488,
	title = {Adaptable AES implementation with power-gating support},
	booktitle = {International Conference on Computing Frontiers CF{\textquoteright}16},
	series = {Proceedings of the ACM International Conference on Computing Frontiers},
	year = {2016},
	month = {05/2016},
	pages = {331-334},
	publisher = {ACM Ney York, NY, USA},
	organization = {ACM Ney York, NY, USA},
	address = {Como, Italy},
	abstract = {In this paper, we propose a reconfigurable design of the Advanced Encryption Standard capable of adapting at runtime to the requirements of the target application. Reconfiguration is achieved by activating only a specific subset of all the instantiated processing elements. Further, we explore the effectiveness of power gating and clock gating methodologies to minimize the energy consumption of the processing elements not involved in computation.},
	keywords = {AES implementation, power analysis attacks, power modeling},
	isbn = {978-1-4503-4128-8},
	doi = {10.1145/2903150.2903488},
	url = {http://doi.acm.org/10.1145/2903150.2903488},
	author = {Banik, Subhadeep and Bogdanov, Andrey and Fanni, Tiziana and Sau, Carlo and Raffo, Luigi and Palumbo, Francesca and Regazzoni, Francesco}
}
@conference {18578,
	title = {Atomic-AES: A Compact Implementation of the AES Encryption/Decryption Core},
	booktitle = {Proceedings of 17th International Conference on Cryptology in India (INDOCRYPT) 2016},
	year = {2016},
	author = {Banik, Subhadeep and Bogdanov, Andrey and Regazzoni, Francesco}
}
@proceedings {18514,
	title = {CCM: Controlling the Change Magnitude in High Dimensional Data},
	journal = {In Proceedings of the 2nd INNS Conference on Big Data 2016 (INNS Big Data 2016)},
	year = {2016},
	month = {10/2016},
	pages = {1-10},
	address = {Thessaloniki, Greece},
	abstract = {Change-detection algorithms are often tested on real-world datasets where changes are synthetically introduced. While this common practice allows generating multiple datasets to obtain stable performance measures, it is often quite arbitrary since the change magnitude is seldom controlled. Thus, experiments { in particular those on multivariate and high-dimensional data. We here present a rigorous framework for introducing changes having a controlled magnitude in multivariate datasets. In particular, we introduce changes by directly roto-translating the data, and we measure the change magnitude by the symmetric
Kullback-Leibler divergence between pre- ad post-change distributions. We present an iterative algorithm that identities the roto-translation parameters yielding the desired change magnitude, and we prove its convergence analytically. We also illustrate our MATLAB framework that introduces changes having a controlled magnitude in real-world datasets, which is made publicly available for download.
},
	author = {Alippi, Cesare and Boracchi, Giacomo and Carrera, Diego}
}
@conference {18447,
	title = {Change Detection in Multivariate Datastreams: Likelihood and  Detectability Loss},
	booktitle = {25th International Joint Conference on Artificial Intelligence (IJCAI-16)},
	year = {2016},
	month = {07/2016},
	address = { New York, USA},
	abstract = {We address the problem of detecting changes in multivariate datastreams, and we investigate the intrinsic difficulty that change-detection methods have to face when the data-dimension scales. In particular, we consider the general approach that detects changes by comparing the distribution of the log-likelihood of the datastream over different time windows. Despite the fact that this approach constitutes the frame for several change-detection methods, its effectiveness when the dimension of data scales has never been investigated, which is indeed the goal of our paper. We show that the magnitude of the change can be naturally measured by the symmetric Kullback-Leibler divergence between the pre- and post-change distributions, and that the detectability of a change of a given magnitude worsens when the data-dimension increases. This structural problem, which we refer to as detectability loss, is due to the linear relationship existing between the variance of the log-likelihood and the data dimension, and reveals to be harmful even at low data-dimensions (say, 10). We analytically derive the detectability loss on Gaussian-distributed datastreams, and empirically demonstrate that this problem holds also on real-world datasets.},
	author = {Alippi, Cesare and Boracchi, Giacomo and Carrera, Diego and Roveri, Manuel}
}
@article {18511,
	title = {A Cloud to the Ground: The New Frontier of Intelligent and Autonomous Networks of Things},
	journal = {IEEE Communication Magazine},
	volume = {54},
	issue = {12},
	year = {2016},
	month = {11/2016},
	pages = {14 - 20},
	chapter = {14},
	abstract = {The Internet-of-Things (IoT) paradigm is supporting -and will support- an ever-increasing number of services and applications impacting on almost every aspect of our everyday life. The current trend is forecasting IoT to connect tens of billion objects by 2020 yielding a very-high volume of data to be acquired, transmitted and processed. IoT typically relies on Cloud Computing to process, analyze and store the data acquired by IoT entities. Unfortunately, the need to transmit all data from the information producing objects to the Cloud for a subsequent processing/analysis phase would require a large bandwidth and increase the latency in the {\textquotedblleft}decision-making process{\textquotedblright} whenever decisions/reactions must be promptly taken by the IoT units.
The Fog Computing (FC) paradigm aims at addressing these problems by extending Cloud Computing towards the edge of the network. In this direction, this paper introduces a novel FC-IoT paradigm designed
to move computing, storage and applications/services close to IoT objects so as to reduce communication bandwidth and energy consumption as well as {\textquotedblleft}decision-making{\textquotedblright} latency. The proposed IoT-based solution has been designed to have intelligent and autonomous IoT objects that are integrated with a FC and Fog Networking approach. The distinguishing features of the intelligent FC-IoT platform are low-latency, self-adaptation, low energy consumption and spectrum efficiency.
},
	doi = { 10.1109/MCOM.2016.1600541CM},
	author = {Alippi, Cesare and Fantacci, Romano and Marabissi, Dania and Roveri, Manuel}
}
@conference {18449,
	title = {Ensemble LSDD-based Change Detection Tests},
	booktitle = {IEEE-INNS  International Joint Conference on Neural Networks (IJCNN16)},
	year = {2016},
	month = {07/2016},
	address = {Vancouver, Canada},
	abstract = {The least squares density difference change detection test (LSDD-CDT) has proven to be an effective method in detecting concept drift by inspecting features derived from the discrepancy between two probability density functions (pdfs). The first pdf is associated with the concept drift free case, the second to the possible post change one. Interestingly, the method permits to control the ratio of false positives. This paper introduces and investigates the performance of a family of LSDD methods constructed by exploring different ensemble options applied to the basic CDT procedure. Experiments show that most of proposed methods are characterized by improved performance in change detection once compared with the direct ensemble-free counterpart.},
	author = {Bu, Li and Alippi, Cesare and Zhao, Dongbin}
}
@conference {18485,
	title = {Evaluating the Impact of Environmental Factors on Physically Unclonable Functions},
	booktitle = {International Symposium on Field-Programmable Gate Arrays FPGA 2016},
	series = {Proceedings of the 2016 ACM/SIGDA},
	year = {2016},
	month = {02/2016},
	pages = {279},
	publisher = {ACM New York, NY, USA},
	organization = {ACM New York, NY, USA},
	address = {Monterey, CA, USA},
	abstract = {Fabrication process introduces some inherent variability to the attributes of transistors (in particular length, widths, oxide thickness). As a result, every chip is physically unique. Physical uniqueness of microelectronics components can be used for multiple security applications. Physically Unclonable Functions (PUFs) are built to extract the physical uniqueness of microelectronics components and make it usable for secure applications.

However, the microelectronics components used by PUFs designs suffer from external, environmental variations that impact the PUF behavior. Variations of temperature gradients during manufacturing can bias the PUF responses. Variations of temperature or thermal noise during PUF operation change the behavior of the circuit, and can introduce errors in PUF responses. Detailed knowledge of the behavior of PUFs operating over various environmental factors is needed to reliably extract and demonstrate uniqueness of the chips.

In this work, we present a detailed and exhaustive analysis of the behavior of two PUF designs, a ring oscillator PUF and a timing path violation PUF. We have implemented both PUFs using FPGA fabricated by Xilinx, and analyzed their behavior while varying temperature and supply voltage. Our experiments quantify the robustness of each design, demonstrate their sensitivity to temperature and show the impact which supply voltage has on the uniqueness of the analyzed PUFs.
},
	isbn = {978-1-4503-3856-1},
	doi = {10.1145/2847263.2847308},
	url = {http://doi.acm.org/10.1145/2847263.2847308},
	author = {Bellon, Sebastien and Favi, Claudio and Malek, Miroslaw and Macchetti, Marco and Regazzoni, Francesco}
}
@article {18455,
	title = {A Framework for Disturbance Analysis in Smart Grids by Fault Injection},
	journal = {Springer Journal on "Computer Science - Research and Development"},
	year = {2016},
	month = {09/2016},
	abstract = {With growing complexity of electric power systems, a total number of disturbances is expected to increase. Analyzing these disturbances and understanding grid{\textquoteright}s behavior, when under a disturbance, is a pre-requisite for designing methods for boosting grid{\textquoteright}s stability. The main obstacle to the analysis is a lack of relevant data that are publicly available. In this paper, we design and implement a framework for emulation of grid disturbances by employing simula-tion and fault-injection techniques. We also present a case study on generating voltage sag related data. A foreseen usage of the framework considers mainly prototyping, root-cause analysis and design and comparison of methods for disturbance detection and prediction. },
	issn = {1865-2042},
	doi = {10.1007/s00450-016-0313-8},
	url = {http://dx.doi.org/10.1007/s00450-016-0313-8},
	author = {Kaitovi{\'c}, Igor and Obradovi{\'c}, Filip and Lukovi{\'c}, Slobodan and Malek, Miroslaw}
}
@conference {18459,
	title = {A Friend or a Foe? Detecting Malware Using Memory and CPU Features},
	booktitle = {SECRYPT 2016, 13th International Conference on Security and Cryptography},
	year = {2016},
	month = {07/2016},
	publisher = {SciTePress Digital Library},
	organization = {SciTePress Digital Library},
	address = {Lisbon, Portugal},
	author = {Milosevic, Jelena and Malek, Miroslaw and Ferrante, Alberto}
}
@conference {18513,
	title = {An improved Hilbert-Huang Transform for non-linear and time-variant signals},
	booktitle = {26th Italian Workshop on Neural Networks (WIRN 2016)},
	year = {2016},
	month = {05/2016},
	pages = {1-8},
	address = {Vietri sul Mare, Salerno, Italy},
	abstract = {Learning in non-stationary/evolving environments requires methods able to process and deal with non-stationary streams. In this paper we propose a novel algorithm providing a time-frequency decomposition
of time-variant signals. Outcoming signals can be used to identify anomalous events/patterns or extract features associated with the time variance of the signal, precious information for any consequent learning
action. The paper extends the Hilbert-Huang Transform notoriously used to deal with time-variant signals by introducing (i) a new Empirical Mode Decomposition that identies the number of frequency modes of
the signal and (ii) an extension of the Hilbert Transform that eliminates negative frequency-values in the time-frequency spectrum. The effectiveness of the proposed Transform has been tested on both synthetic and real time-variant signals acquired by a real-world intelligent system for landslide monitoring.
},
	author = {Alippi, Cesare and Wen, Qi and Roveri, Manuel}
}
@conference {18486,
	title = {Instruction Set Extensions for secure applications},
	booktitle = {Design, Automation Test in Europe Conference DATE 2016},
	year = {2016},
	month = {03/2016},
	pages = {1529-1534},
	publisher = {IEEE},
	organization = {IEEE},
	address = {Dresden, Germany},
	abstract = {The main goal of this paper is to expose the community to past achievements and future possible uses of Instruction Set Extension (ISE) in security applications. Processor customization has proven to be an effective way for achieving high performance with limited area and energy overhead for several applications, ranging from signal processing to graphical computation. Concerning cryptographic algorithms, a large body of work exists on speeding up block ciphers and asymmetric cryptography with specific ISEs. These algorithms often mix non-standard operations with regular ones, thus representing an ideal target for being accelerated with dedicated instructions. Tools supporting automatic generations of ISEs demonstrated to be useful for algorithm exploration, while secure instructions can increase the robustness against side channels attacks of software routines. In this paper, we discuss how processor customization and the relative tool chains can be used by designers to address security problems and we highlight possible research directions},
	keywords = {asymmetric cryptography, block ciphers, cryptographic algorithms protection, instruction set, security applications},
	isbn = {978-3-9815-3707-9},
	url = {http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=7459556},
	author = {Regazzoni, Francesco and Ienne, Paolo}
}
@conference {18562,
	title = {Lattice-based cryptography: From reconfigurable hardware to {ASIC}},
	booktitle = {2016 International Symposium on Integrated Circuits (ISIC)},
	year = {2016},
	month = {12/2016},
	publisher = {IEEE},
	organization = {IEEE},
	doi = {10.1109/isicir.2016.7829689},
	url = {https://doi.org/10.1109/isicir.2016.7829689},
	author = {Oder, Tobias and G{\"u}neysu, Tim and Valencia, Felipe and Khalid, Ayesha and O{\textquoteright}Neill, Maire and Regazzoni, Francesco}
}
@conference {18461,
	title = {MalAware: Effective and Efficient Run-time Mobile Malware Detector},
	booktitle = {The 14th  IEEE International Conference on Dependable,  Autonomic and Secure Computing (DASC 2016)},
	year = {2016},
	month = {08/2016},
	publisher = {IEEE Computer Society Press},
	organization = {IEEE Computer Society Press},
	address = {Auckland, New Zealand},
	author = {Milosevic, Jelena and Ferrante, Alberto and Malek, Miroslaw}
}
@conference {18503,
	title = {A Methodology for Proactive Maintenance of Uninterruptible Power Supplies},
	booktitle = {Latin-American Symposium on Dependable Computing  (LADC2016) - Workshop on Dependability in Evolving Systems (WDES)},
	year = {2016},
	month = {10/2016},
	address = {Cali, Colombia},
	abstract = {We propose a methodology for proactive maintenance of Uninterruptible Power Supply (UPS) devices based on online health-status monitoring and application of data analytics for prediction of UPS components{\textquoteright} failures. The goals of the work are (i) improvement of reliability of UPS devices by ensuring prompt action prior to a failure of a component, and (ii) provision of more cost-effective maintenance by servicing the device only when required instead of periodically. Improving reliability of UPS{\textquoteright}es also enhances dependability of critical infrastructures that require high quality power supply.},
	author = {Lukovi{\'c}, Slobodan and Kaitovi{\'c}, Igor and Lecuona, Gerardo and Malek, Miroslaw}
}
@article {18543,
	title = {Model Complexity, Regularization, and Sparsity [Guest Editorial]},
	year = {2016},
	keywords = {Adaptation models, Computational complexity, machine learning, Sparse matrices, Special issues and sections},
	doi = {10.1109/MCI.2016.2602071},
	author = {Alippi, Cesare and Boracchi, Giacomo and Wohlberg, Brendt}
}
@conference {18448,
	title = {One-Class Classification Through Mutual Information Minimization},
	booktitle = {IEEE-INNS  International Joint Conference on Neural Networks (IJCNN16)},
	year = {2016},
	month = {07/2016},
	address = {Vancouver, Canada},
	abstract = {In one-class classification problems, a model is synthesized by using only information coming from the nominal state of the data generating process. Many important applications can be cast in the one-class classification framework, such as anomaly and change in stationarity detection, and fault recognition. In this paper, we present a novel design methodology for oneclass classifiers derived from graph-based entropy estimators. The entropic graph is used to generate a partition of the input nominal conditions, which corresponds to the classifier model. Here we propose a criterion based on mutual information minimization to learn such a partition. The _-Jensen difference is considered, which provides a convenient way for estimating the mutual information. The classifier incorporates also a fuzzy model, providing a confidence value for a generic test sample during operational modality, expressed as a membership degree of the sample to the nominal conditions class. The fuzzification mechanism is based only on topological properties of the entropic spanning graph vertices; as such, it allows to model clusters of arbitrary shapes. We show preliminary {\textendash} yet very promising {\textendash} results on both synthetic problems and real-world datasets for one-class classification.
},
	author = {Livi, Lorenzo and Alippi, Cesare}
}
@conference {18450,
	title = {Online Model-free Sensor Fault Identification and Dictionary Learning in Cyber-Physical Systems},
	booktitle = {IEEE-INNS  International Joint Conference on Neural Networks (IJCNN16)},
	year = {2016},
	month = {07/2016},
	address = {Vancouver, Canada},
	abstract = {This paper presents a model-free method for the online identification of sensor faults and learning of their fault dictionary. The method, designed having in mind Cyber-Physical Systems (CPSs), takes advantage of functional relationships among the datastreams acquired by CPS sensing units. Existing model-free change detection mechanisms are proposed to detect faults and identify the fault type thanks to a fault dictionary
which is built over time. The main features of the proposed algorithm are its ability to operate without requiring any a priori information about the system under inspection or the nature of the possibly occurring faults. As such, the method follows the model-free approach, characterized by the fact the fault dictionary
is constructed online once faults are detected. Whenever available, humans can be considered in the loop to label a fault or a fault class in the dictionary as well as introduce fault instances generated thanks to a priori information. Experimental results on both synthetic and real datasets corroborate the effectiveness of the proposed fault diagnosis system.
},
	author = {Alippi, Cesare and Ntalampiras, Stavros and Roveri, Manuel}
}
@conference {18454,
	title = {Optimizing Failure Prediction to Maximize Availability},
	booktitle = {13th IEEE International Conference on Autonomic Computing (ICAC)},
	year = {2016},
	month = {07/2016},
	address = {W{\"u}rzburg, Germany},
	abstract = {Availability of autonomous systems can be enhanced with self-monitoring and fault-tolerance methods based on failures prediction. With each correct prediction, proactive actions may be taken to prevent or to mitigate a failure. On the other hand, incorrect predictions will introduce additional downtime associated with the overhead of a proactive action that may decrease availability. The total effect on availability will depend on the quality of prediction (measured with precision and recall), the overhead of proactive actions (penalty), and the benefit of proactive actions when prediction is correct (reward). In this paper, we quantify the impact of failure prediction and proactive actions on steady-state availability. Furthermore, we provide guidelines for optimizing failure prediction to maximize availability by selecting a proper precision and recall trade-off with respect to penalty and reward. A case study to demonstrate the approach is also presented.},
	author = {Kaitovi{\'c}, Igor and Malek, Miroslaw}
}
@conference {18580,
	title = {Physical Attacks and Beyond},
	booktitle = {Proceedings of the Selected Areas in Cryptography: 23nd International Conference (SAC) 2016},
	year = {2016},
	author = {Regazzoni, Francesco}
}
@conference {18484,
	title = {Round gating for low energy block ciphers},
	booktitle = {2016 IEEE International Symposium on Hardware Oriented Security and Trust, HOST},
	year = {2016},
	month = {05/2016},
	pages = {55-60},
	publisher = {IEEE Computer Society},
	organization = {IEEE Computer Society},
	address = {McLean, VA, USA},
	abstract = {Pushed by the pervasive diffusion of devices operated by battery or by the energy harvested, energy has become one of the most important parameter to be optimized for embedded systems. Particularly relevant would be to optimize the energy consumption of security primitives. In this paper we explore design techniques for implementing block ciphers in a low energy fashion. We concentrate on round based implementation and we discuss how gating, applied at round level can affect and improve the energy consumption of the most common lightweight block cipher currently used in the internet of things. Additionally, we discuss how to needed gating wave can be generated. Experimental results show that our technique is able to reduce the energy consumption in most block ciphers by over 60\% while incurring only a minimal overhead in hardware},
	keywords = {algorithm design and analysis, ciphers, clocks, computer architecture, energy consumption},
	isbn = {978-1-4673-8826-9},
	doi = {10.1109/HST.2016.7495556},
	url = {http://dx.doi.org/10.1109/HST.2016.7495556},
	author = {Banik, Subhadeep and Bogdanov, Andrey and Regazzoni, Francesco and Isobe, Takanori and Hiwatari, Harunaga and Akishita, Toru}
}
@conference {18489,
	title = {Secure architectures of future emerging cryptography},
	booktitle = {International Conference on Computing Frontiers CF{\textquoteright}16},
	series = {Proceedings of the ACM International Conference on Computing Frontiers},
	year = {2016},
	month = {05/2016},
	pages = {315-322},
	publisher = {ACM New York},
	organization = {ACM New York},
	address = {Como, italy},
	abstract = {Funded under the European Union{\textquoteright}s Horizon 2020 research and innovation programme, SAFEcrypto will provide a new generation of practical, robust and physically secure post-quantum cryptographic solutions that ensure long-term security for future ICT systems, services and applications. The project will focus on the remarkably versatile field of Lattice-based cryptography as the source of computational hardness, and will deliver optimised public key security primitives for digital signatures and authentication, as well identity based encryption (IBE) and attribute based encryption (ABE). This will involve algorithmic and design optimisations, and implementations of lattice-based cryptographic schemes addressing cost, energy consumption, performance and physical robustness. As the National Institute of Standards and Technology (NIST) prepares for the transition to a post-quantum cryptographic suite B, urging organisations that build systems and infrastructures that require long-term security to consider this transition in architectural designs; the SAFEcrypto project will provide Proof-of-concept demonstrators of schemes for three practical real-world case studies with long-term security requirements, in the application areas of satellite communications, network security and cloud. The goal is to affirm Lattice-based cryptography as an effective replacement for traditional number-theoretic public-key cryptography, by demonstrating that it can address the needs of resource-constrained embedded applications, such as mobile and battery-operated devices, and of real-time high performance applications for cloud and network management infrastructures},
	keywords = {identity based encryption, lattice-based cryptography, physical attacks, public-key cryptography},
	isbn = {978-1-4503-4128-8},
	doi = {10.1145/2903150.2907756},
	url = {http://doi.acm.org/10.1145/2903150.2907756},
	author = {O{\textquoteright}Neill, Maire and O{\textquoteright}Sullivan, Elizabeth and McWilliams, Gavin and Saarinen, Markku-Juhani and Moore, Ciara and Khalid, Ayesha and Howe, James and Del Pino, Rafael and Abdalla, Michel and Regazzoni, Francesco and Valencia, Andres Felipe and G{\"u}neysu, Tim and Oder, Tobias and Waller, Adrian and Jones, Glyn and Barnett, Anthony and Griffin, Robert and Byrne, Andrew and Ammar, Bassem and Lund, David}
}
@conference {18515,
	title = {Spotting the Malicious Moment: Characterizing Malware Behavior Using Dynamic Features},
	booktitle = {2016 11th International Conference on Availability, Reliability and Security (ARES)},
	year = {2016},
	month = {08/2016},
	address = {Salzburg, Austria},
	keywords = {Android applications, Androids, automatic mobile application analysis, dynamic features, Feature extraction, Humanoid robots, informative malware identification, invasive software, learning (artificial intelligence), local malicious behavior detection, machine learning, malicious activity, malware, malware behavior characterization, malware detection tools, mobile computing, mobile devices, Mobile handsets, monitoring, pattern classification, program diagnostics, resource usage, security, system calls, user protection},
	doi = {10.1109/ARES.2016.70},
	author = {Ferrante, Alberto and Mercaldo, Francesco and Milosevic, Jelena and Visaggio, Corrado Aaron},
	editor = {Medvet, Eric}
}
@conference {18487,
	title = {Standard lattices in hardware},
	booktitle = {Proceedings of the 53rd Annual Design Automation Conference DAC 2016},
	series = {Proceedings of DAC },
	year = {2016},
	month = {06/2016},
	pages = {162},
	publisher = {ACM},
	organization = {ACM},
	address = {Austin, TX, USA},
	abstract = {Lattice-based cryptography has gained credence recently as a replacement for current public-key cryptosystems, due to its quantum-resilience, versatility, and relatively low key sizes. To date, encryption based on the learning with errors (LWE) problem has only been investigated from an ideal lattice standpoint, due to its computation and size efficiencies. However, a thorough investigation of standard lattices in practice has yet to be considered. Standard lattices may be preferred to ideal lattices due to their stronger security assumptions and less restrictive parameter selection process.

In this paper, an area-optimised hardware architecture of a standard lattice-based cryptographic scheme is proposed. The design is implemented on a FPGA and it is found that both encryption and decryption fit comfortably on a Spartan-6 FPGA. This is the first hardware architecture for standard lattice-based cryptography reported in the literature to date, and thus is a benchmark for future implementations. Additionally, a revised discrete Gaussian sampler is proposed which is the fastest of its type to date, and also is the first to investigate the cost savings of implementing with λ/2-bits of precision.

Performance results are promising compared to the hardware designs of the equivalent ring-LWE scheme, which in addition to providing stronger security proofs; generate 1272 encryptions per second and 4395 decryptions per second.
},
	keywords = {encryption, hardware design, lattice-based cryptography, physical attack},
	isbn = {978-1-4503-4236-0},
	doi = {10.1145/2897937.2898037},
	url = {http://doi.acm.org/10.1145/2897937.2898037},
	author = {Howe, James and Moore, Ciara and O{\textquoteright}Neill, Maire and Regazzoni, Francesco and G{\"u}neysu, Tim and Beeden, K.}
}
@conference {18490,
	title = {Topology Optimization of Wireless Localization Networks},
	booktitle = {European Wireless 2016 },
	year = {2016},
	month = {05/2016},
	address = {Oulu, Finland},
	abstract = {This paper addresses topology optimization problem for an ultra wide band (UWB) localization network, where trilateration is used to obtain the target position based on its distances from fixed and known anchors. Our goal is to minimize the number of anchors needed to localize a target, while keeping the localization uncertainty lower than a given threshold in an area of arbitrary shape with obstacles. Our propagation model accounts for the presence of line of sight (LOS) between nodes, while geometric dilution of precision (GDoP) is used to express the localization error introduced by trilateration. We propose two integer linear programming formulations to solve the problem. To handle the problems of large sizes, we use the greedy placement with pruning heuristic. We test our solutions through simulation and show that the integer linear programming is appropriate to handle reasonably sized problems, and the heuristic achieves the results, in terms of the number of anchors placed, within less
than 2\% of optimum on average.
},
	keywords = {localization network, propagation model, topology optimization, ultra wide band, wireless protocols, wireless sensor networks},
	author = {Bala{\'c}, Katarina and Akhmedov, Murodzhon and Prevostini, Mauro and Malek, Miroslaw}
}
@conference {18505,
	title = {Trojan Families Identification Using Dynamic Features and Low Complexity Classifiers},
	booktitle = {24th EICAR Annual Conference 2016 "Trustworthiness in IT Security Products"},
	year = {2016},
	month = {10/2016},
	publisher = {EICAR},
	organization = {EICAR},
	address = {Nuremberg, Germany},
	author = {Milosevic, Jelena and Ferrante, Alberto and Malek, Miroslaw}
}
@conference {18579,
	title = {Trojans in Early Design Steps - An Emerging Threat},
	booktitle = {TRUDEVICE Final Conference (FCTRU{\^a}16)},
	year = {2016},
	author = {Polian, Ilia and Becker, Georg and Regazzoni, Francesco}
}
@conference {18385,
	title = {What Does the Memory Say? Towards the most indicative features for efficient malware detection},
	booktitle = {CCNC 2016, The 13th Annual IEEE Consumer Communications \& Networking Conference},
	year = {2016},
	month = {01/2016},
	publisher = {IEEE Communication Society},
	organization = {IEEE Communication Society},
	address = {Las Vegas, NV, USA},
	author = {Milosevic, Jelena and Ferrante, Alberto and Malek, Miroslaw}
}
@conference {18478,
	title = {200 MS/s ADC implemented in a FPGA employing TDCs},
	booktitle = {FPGA International Symposium on Field-Programmable Gate Arrays ACM/SIGDA 2015},
	series = {Proceedings of the 2015 ACM/SIGDA},
	year = {2015},
	month = {02/2015},
	pages = {228-235},
	publisher = {ACM},
	organization = {ACM},
	address = {Monterey, CA, USA},
	abstract = {Analog signals are used in many applications and systems, such as cyber physical systems, sensor networks and automotive applications. These are also applications where the use of FPGAs is continuously growing. To date, however there is no direct integration between FPGAs, which are digital, and the analog world (except for the newest generation of FPGAs). Currently, an external analog-to-digital converter (ADC) has to be added to the system, thus limiting its overall compactness and flexibility.

To address this issue we propose a novel architecture implementing a high speed ADC in reconfigurable devices. The system exploits picosecond resolution time-to-digital converters (TDCs) to reach a conversion as fast as its clock speed. The resulting analog-through-time-to-digital converter (ATDC) can achieve a sampling rate of 200 MS/s with a 7 bit resolution for signals ranging from 0 to 2.5 V. Except for the external resistor needed for the analog reference ramp, the system is fully integrated inside the target FPGA. Moreover, our design can be easily scaled for multichannel ADCs, proving the suitability of reconfigurable devices for applications requiring a deep integration between analog and digital world.
},
	keywords = {analog-through time to digital convertor, FPGA-based design, reference voltage},
	isbn = {978-1-4503-3315-3},
	doi = {10.1145/2684746.2689070},
	url = {http://doi.acm.org/10.1145/2684746.2689070},
	author = {Homulle, Harald and Regazzoni, Francesco and Charbon, Edoardo}
}
@article {18482,
	title = {Automatic Application of Power Analysis Countermeasures},
	journal = {IEEE Transactions on Computers },
	volume = {64},
	issue = {2},
	year = {2015},
	month = {02/2015},
	pages = {329-341},
	type = {journal},
	chapter = {329},
	abstract = {We introduce a compiler that automatically inserts software countermeasures to protect cryptographic algorithms against power-based side-channel attacks. The compiler first estimates which instruction instances leak the most information through side-channels. This information is obtained either by dynamic analysis, evaluating an information theoretic metric over the power traces acquired during the execution of the input program, or by static analysis. As information leakage implies a loss of security, the compiler then identifies (groups of) instruction instances to protect with a software countermeasure such as random precharging or Boolean masking. As software protection incurs significant overhead in terms of cryptosystem runtime and memory usage, the compiler protects the minimum number of instruction instances to achieve a desired level of security. The compiler is evaluated on two block ciphers, AES and Clefia; our experiments demonstrate that the compiler can automatically identify and protect the most important instruction instances. To date, these software countermeasures have been inserted manually by security experts, who are not necessarily the main cryptosystem developers. Our compiler offers significant productivity gains for cryptosystem developers who wish to protect their implementations from side-channel attacks},
	keywords = {cryptographic algorithms protection, cryptography, data protection, power analysis attacks, program compilers, side-channel attacks},
	issn = {0018-9340},
	doi = {10.1109/TC.2013.219},
	url = {http://dx.doi.org/10.1109/TC.2013.219},
	author = {Bayrak, Ali Galip and Regazzoni, Francesco and Novo, David and Brisk, Philip and Standaert, Fran{\c c}ois-Xavier and Ienne, Paolo}
}
@conference {18390,
	title = {Can we Achieve both Privacy Protection and Efficient Malware Detection on Smartphones?},
	booktitle = {1st Interdisciplinary Cyber Research Workshop 2015},
	year = {2015},
	month = {07/2015},
	publisher = {Tallinn University of Technology},
	organization = {Tallinn University of Technology},
	address = {Tallin, Estona},
	url = {http://cybercentre.cs.ttu.ee/wp/wp-content/uploads/2015/02/ICR_2015_proceedings.pdf},
	author = {Milosevic, Jelena and Ferrante, Alberto and Malek, Miroslaw}
}
@conference {18477,
	title = {Challenges in designing trustworthy cryptographic co-processors},
	booktitle = {IEEE International Symposium on Circuits and Systems (ISCAS) 2015},
	year = {2015},
	month = {09/2015},
	pages = {2009-2012},
	publisher = {IEEE},
	organization = {IEEE},
	address = {Lisbon, Portugal},
	abstract = {Security is becoming ubiquitous in our society. However, the vulnerability of electronic devices that implement the needed cryptographic primitives has become a major issue. This paper starts by presenting a comprehensive overview of the existing attacks to cryptography implementations. Thereafter, the state-of-the-art on some of the most critical aspects of designing cryptographic co-processors are presented. This analysis starts by considering the design of asymmetrical and symmetrical cryptographic primitives, followed by the discussion on the design and online testing of True Random Number Generation. To conclude, techniques for the detection of Hardware Trojans are also discussed},
	keywords = {asymmetrical cryptographic primitives, cryptography, hardware Trojan detection techniques},
	issn = {0271-4302 },
	doi = {10.1109/ISCAS.2015.7169070},
	url = {http://dx.doi.org/10.1109/ISCAS.2015.7169070},
	author = {Regazzoni, Francesco and Graves, Ricardo and Di Natale, Giorgio and Batina, Lejla and Bhasin, Shivam and Ege, Baris and Fournaris, Apostolos P. and Mentens, Nele and Picek, Stjepan and Rozic, Vladimir and Sklavos, Nicolas and Yang, Bohan}
}
@conference {18481,
	title = {Design methodologies for securing cyber-physical systems},
	booktitle = {2015 International Conference on Hardware/Software Codesign and System Synthesis CODES+ISSS},
	year = {2015},
	month = {10/2015},
	pages = {30-36},
	publisher = {IEEE},
	organization = {IEEE},
	address = {Amsterdam, Netherlands},
	abstract = {Cyber-Physical Systems (CPS) are in most cases safety- and mission-critical. Standard design techniques used for securing embedded systems are not suitable for CPS due to the restricted computation and communication budget available in the latter. In addition, the sensitivity of sensed data and the presence of actuation components further increase the security requirements of CPS. To address these issues, it is necessary to provide new design methods in which security is considered from the beginning of the whole design flow and addressed in a holistic way. In this paper, we focus on the design of secure CPS as part of the complete CPS design process, and provide insights into new requirements on platform-aware design of control components, design methodologies and architectures posed by CPS design. We start by discussing methods for the multi-disciplinary modeling, simulation, tools, and software synthesis challenges for CPS. We also present a framework for design of secure control systems for CPS, while taking into account properties of the underlying computation and communication platforms. Finally, we describe the security challenges in the computing hardware that is used in CPS},
	keywords = {cyber-physical system security, design flow, embedded systems, platform-aware design, safety-critical system, security of data, sensed data sensitivity},
	isbn = {978-1-4673-8321-9},
	doi = {10.1109/CODESISSS.2015.7331365},
	url = {http://dx.doi.org/10.1109/CODESISSS.2015.7331365},
	author = {Faruque, Mohammad Abdullah A and Regazzoni, Francesco and Pajic, Miroslav}
}
@article {18473,
	title = {Exploring Energy Efficiency of Lightweight Block Ciphers},
	journal = {(IACR) Cryptology ePrint Archive},
	volume = {2015},
	year = {2015},
	month = {09/2015},
	chapter = {847},
	abstract = {In the last few years, the field of lightweight cryptography has seen an influx in the number of block ciphers and hash functions being proposed. One of the metrics that define a good lightweight design is the energy consumed per unit operation of the algorithm. For block ciphers, this operation is the encryption of one plaintext. By studying the energy consumption model of a CMOS gate, we arrive at the conclusion that the total energy consumed during the encryption operation of an r-round unrolled architecture of any block cipher is a quadratic function in r. We then apply our model to 9 well known lightweight block ciphers, and thereby try to predict the optimal value of r at which an r-round unrolled architecture for a cipher is likely to be most energy efficient. We also try to relate our results to some physical design parameters like the signal delay across a round and algorithmic parameters like the number of rounds taken to achieve full diffusion of a difference in the plaintext/key. },
	keywords = {implementation AES, lightweight block cipher, Low Power Energy Circuits},
	url = {http://eprint.iacr.org/2015/847},
	author = {Banik, Subhadeep and Bogdanov, Andrey and Regazzoni, Francesco}
}
@conference {18474,
	title = {Exploring Energy Efficiency of Lightweight Block Ciphers},
	booktitle = {Selected Areas in Cryptography: 22nd International Conference (SAC)2015},
	series = {Lecture Notes in Computer Science},
	volume = {9566},
	year = {2015},
	month = {08/2015},
	pages = {178-194},
	publisher = {Springer},
	organization = {Springer},
	address = {Sackville, NB, Canada},
	abstract = {In the last few years, the field of lightweight cryptography has seen an influx in the number of block ciphers and hash functions being proposed. One of the metrics that define a good lightweight design is the energy consumed per unit operation of the algorithm. For block ciphers, this operation is the encryption of one plaintext. By studying the energy consumption model of a CMOS gate, we arrive at the conclusion that the energy consumed per cycle during the encryption operation of an r-round unrolled architecture of any block cipher is a quadratic function in r. We then apply our model to 9 well known lightweight block ciphers, and thereby try to predict the optimal value of r at which an r-round unrolled architecture for a cipher is likely to be most energy efficient. We also try to relate our results to some physical design parameters like the signal delay across a round and algorithmic parameters like the number of rounds taken to achieve full diffusion of a difference in the plaintext/key.},
	keywords = {AES, lightweight block cipher, Low Power Energy Circuits},
	isbn = {978-3-319-31300-9},
	issn = {0302-9743},
	doi = {10.1007/978-3-319-31301-6},
	url = {http://dx.doi.org/10.1007/978-3-319-31301-6},
	author = {Banik, Subhadeep and Bogdanov, Andrey and Regazzoni, Francesco}
}
@conference {18475,
	title = {Exploring the energy consumption of lightweight blockciphers in FPGA},
	booktitle = {International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015},
	year = {2015},
	month = {02/2016},
	pages = {1-6},
	publisher = {IEEE},
	organization = {IEEE},
	edition = {2015},
	address = {Rivera Maya, Mexico City},
	abstract = {Internet of things and cyber-physical systems requiring security functionality has pushed for the design of a number of block ciphers and hash functions specifically developed for being implemented in resource constrained devices. Initially the optimization was mainly on area and power consumption, but, nowadays the attention is more on the energy consumption. In this paper, for the first time, we look at energy consumption of lightweight block ciphers implemented in reconfigurable devices, and we analyze the effects that round unrolling might have on the energy consumed during the encryption. Concentrating on applications that require a number of parallel encryptions, we instantiate several designs on the target FPGA and we analyze how the energy consumption varies in each algorithm when changing the amount of unrolled rounds. Our results, obtained on the Xc6slx45t device of the Spartan6 family, demonstrate that Present is the most energy efficient algorithm and that the relation between the energy consumption and the number of unrolled rounds measured on FPGA is similar to the one measured on dedicated hardware.},
	keywords = {cryptography, cyber-physical systems, encryption, lightweight block cipher},
	isbn = {978-1-4673-9406-2},
	doi = {10.1109/ReConFig.2015.7393308},
	url = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=7390332},
	author = {Banik, Subhadeep and Bogdanov, Andrey and Regazzoni, Francesco}
}
@conference {18480,
	title = {Fault attacks, injection techniques and tools for simulation},
	booktitle = {10th International Conference on Design Technology of Integrated Systems in Nanoscale Era DTIS 2015},
	year = {2015},
	month = {04/2015},
	pages = {1-6},
	publisher = {IEEE},
	organization = {IEEE},
	address = {Naples, Italy},
	abstract = {Faults attacks are a serious threat to secure devices, because they are powerful and they can be performed with extremely cheap equipment. Resistance against fault attacks is often evaluated directly on the manufactured devices, as commercial tools supporting fault evaluation do not usually provide the level of details needed to assert the security of a device. Early identification of weak points would instead be very useful as it would allow to immediately apply the appropriate countermeasures directly at design time. Moving towards this goal, in this work, we survey existing fault attacks and techniques for injecting faults, and we analyze the suitability of existing electronic design automaton commodities for estimating resistance against fault attacks. Our exploration, which includes the type of attacks that can be simulated and the limitations of each considered simulation approach, is an initial step towards the development of a complete framework for asserting fault attack robustness},
	keywords = {fault attacks robustness, fault resilience, injection techniques, secure devices, security, security of data},
	isbn = {978-1-4799-1999-4},
	doi = {10.1109/DTIS.2015.7127352},
	url = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=7118811},
	author = {Piscitelli, Roberta and Bhasin, Shivam and Regazzoni, Francesco}
}
@misc {18391,
	title = {A General Practitioner or a Specialist for Your Infected Smartphone?},
	journal = {36th IEEE Symposium on Security and Privacy },
	year = {2015},
	month = {05/2015},
	publisher = {IEEE Computer Society Technical Committee on Security and Privacy},
	address = {San Jose, CA, USA},
	abstract = {With explosive growth in the number of mobile devices, the mobile malware is rapidly spreading as well, and the number of encountered malware families is increasing. Existing solutions, which are mainly based on one malware detector running on the phone or in the cloud, are no longer effective. Main problem lies in the fact that it might be impossible to create a unique mobile malware detector that would be able to detect different malware families with high accuracy, being at the same time lightweight enough not to drain battery quickly and fast enough to give results of detection promptly.

The proposed approach to mobile malware detection is analogous to general practitioner versus specialist approach to dealing with a medical problem. Similarly to a general practitioner that, based on indicative symptoms identifies potential illnesses and sends the patient to an appropriate specialist, our detection system distinguishes among symptoms representing different malware families and, once the symptoms are detected, it triggers specific analyses. A system monitoring application operates in the same way as a general practitioner. It is able to distinguish between different symptoms and trigger appropriate detection mechanisms. As an analogy to different specialists, an ensemble of detectors, each of which specifically trained for a particular malware family, is used. The main challenge of the approach is to define representative symptoms of different malware families and train detectors accordingly to them. The main goal of the poster is to foster discussion on the most representative symptoms of different malware families and to discuss initial results in this area obtained by using Malware Genome project dataset.},
	keywords = {Android, feature selection, malware detection, PCA, security},
	url = {http://www.ieee-security.org/TC/SP2015/posters/paper_16.pdf},
	author = {Milosevic, Jelena and Ferrante, Alberto and Malek, Miroslaw}
}
@conference {18483,
	title = {Midori: A Block Cipher for Low Energy},
	booktitle = {21st International Conference on the Theory and Application of Cryptology and Information Security ASIACRYPT 2015},
	series = {Lecture Notes in Computer Science},
	volume = {9453},
	year = {2015},
	month = {11/2015},
	pages = {411-436},
	publisher = {Springer Berlin Heidelberg},
	organization = {Springer Berlin Heidelberg},
	address = {Auckland, New Zealand},
	abstract = {In the past few years, lightweight cryptography has become a popular research discipline with a number of ciphers and hash functions proposed. The designers{\textquoteright} focus has been predominantly to minimize the hardware area, while other goals such as low latency have been addressed rather recently only. However, the optimization goal of low energy for block cipher design has not been explicitly addressed so far. At the same time, it is a crucial measure of goodness for an algorithm. Indeed, a cipher optimized with respect to energy has wide applications, especially in constrained environments running on a tight power/energy budget such as medical implants.

This paper presents the block cipher Midori (The name of the cipher is the Japanese translation for the word Green.) that is optimized with respect to the energy consumed by the circuit per bt in encryption or decryption operation. We deliberate on the design choices that lead to low energy consumption in an electrical circuit, and try to optimize each component of the circuit as well as its entire architecture for energy. An added motivation is to make both encryption and decryption functionalities available by small tweak in the circuit that would not incur significant area or energy overheads. We propose two energy-efficient block ciphers Midori128 and Midori64 with block sizes equal to 128 and 64 bits respectively. These ciphers have the added property that a circuit that provides both the functionalities of encryption and decryption can be designed with very little overhead in terms of area and energy. We compare our results with other ciphers with similar characteristics: it was found that the energy consumptions of Midori64  and Midori128  are by far better when compared ciphers like PRINCE and NOEKEON.
},
	keywords = {lightweight block cipher, low energy circuits},
	isbn = {978-3-662-48799-0},
	issn = {0302-9743},
	doi = {10.1007/978-3-662-48800-3_17},
	url = {http://dx.doi.org/10.1007/978-3-662-48800-3_17},
	author = {Banik, Subhadeep and Bogdanov, Andrey and Isobe, Takanori and Shibutani, Kyoji and Hiwatari, Harunaga and Akishita, Toru and Regazzoni, Francesco}
}
@article {18472,
	title = {Midori: (A) Block Cipher for Low Energy (Extended Version)},
	journal = {(IACR) Cryptology ePrint Archive},
	volume = {2015},
	year = {2015},
	month = {12/2015},
	chapter = {1142},
	abstract = {In the past few years, lightweight cryptography has become a popular research discipline with a number of ciphers and hash functions proposed. The designers{\textquoteright} focus has been predominantly to minimize the hardware area, while other goals such as low latency have been addressed rather recently only. However, the optimization goal of low energy for block cipher design has not been explicitly addressed so far. At the same time, it is a crucial measure of goodness for an algorithm. Indeed, a cipher optimized with respect to energy has wide applications, especially in constrained environments running on a tight power/energy budget such as medical implants. 

This paper presents the block cipher Midori that is optimized with respect to the energy consumed by the circuit per bit in encryption or decryption operation. We deliberate on the design choices that lead to low energy consumption in an electrical circuit, and try to optimize each component of the circuit as well as its entire architecture for energy. An added motivation is to make both encryption and decryption functionalities available by small tweak in the circuit that would not incur significant area or energy overheads. 

We propose two energy-efficient block ciphers Midori128 and Midori64 with block sizes equal to 128 and 64 bits respectively. These ciphers have the added property that a circuit that provides both the functionalities of encryption and decryption can be designed with very little overhead in terms of area and energy. We compare our results with other ciphers with similar characteristics: it was found that the energy consumptions of Midori64 and Midori128 are by far better when compared ciphers like PRINCE and NOEKEON. 
},
	keywords = {AES, lightweight block cipher, low energy circuits, secret-key cryptography},
	url = {http://eprint.iacr.org/2015/1142},
	author = {Regazzoni, Francesco and Banik, Subhadeep and Bogdanov, Andrey and Isobe, Takanori and Shibutani, Kyoji and Hiwatari, Harunaga and Akishita, Toru}
}
@conference {18380,
	title = {Optimizing Sensor Nodes Placement for Fault-tolerant Trilateration-based Localization},
	booktitle = {IEEE Pacific Rim International Symposium on Dependable Computing (PRDC)},
	year = {2015},
	month = {11/2015},
	address = {Zhangjiajie, China},
	author = {Bala{\'c}, Katarina and Prevostini, Mauro and Malek, Miroslaw}
}
@conference {18479,
	title = {Physical attacks, introduction and application to embedded processors},
	booktitle = {10th International Conference on Design Technology of Integrated Systems in Nanoscale Era DTIS 2015},
	year = {2015},
	month = {06/2015},
	pages = {1},
	publisher = {IEEE},
	organization = {IEEE},
	address = {Napoli, Italy},
	abstract = {Physical attacks exploit the physical weaknesses of cryptographic devices to reveal the secret information stored on them. Successful attacks demonstrated in the past were both active, when the adversary tampers with the device to alter its normal behavior, or passive, when the adversary monitors side channels to infer the secret key. In view of this increasingly relevant problem, this talk introduces the most powerful physical attacks presented in the past and highlights state of the art countermeasures, focusing in particular on the embedded systems{\textquoteright} scenario.},
	keywords = {cryptography, embedded processors, embedded systems, microprocessors chips, physical attacks},
	isbn = {978-1-4799-1999-4},
	doi = {10.1109/DTIS.2015.7127356},
	url = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=7118811},
	author = {Regazzoni, Francesco}
}
@conference {18379,
	title = {Proactive Failure Management in Smart Grids for Improved Resilience (A Methodology for Failure Prediction and Mitigation)},
	booktitle = {IEEE GLOBECOM SmartGrid Resilience (SGR) Workshop},
	year = {2015},
	month = {12/2015},
	address = {San Diego, CA, USA},
	abstract = {A gradual move in the electric power industry towards Smart Grids brings several challenges to the system operation such as preserving its resilience and ensuring security. As the system complexity grows and a number of failures increases, the need for grid management paradigm shift from reactive to proactive is apparent and can be realized by employing advanced monitoring instruments, data analytics and prediction methods. In order to improve resilience of the Smart Grid and to contribute to efficient system operation, we present a blueprint of a comprehensive methodology for proactive failure management that may also be applied to manage other types of disturbances and undesirable changes. The methodology is composed of three main steps: (i) continuous monitoring of the most indicative features, (ii) prediction of failures and (iii) their mitigation. The approach is complementary to the existing ones that are mainly based on fast detection and localization of grid disturbances, and reactive corrective actions.},
	keywords = {Failure Prediction, Proactive Management, Resilience, security, smart grid, Synchrophasor},
	author = {Kaitovi{\'c}, Igor and Lukovi{\'c}, Slobodan and Malek, Miroslaw}
}
@conference {18392,
	title = {SCV2: A model-based validation and verification approach to system-of-systems engineering},
	booktitle = {System of Systems Engineering Conference (SoSE), 2015 10th},
	year = {2015},
	month = {05/2015},
	publisher = {IEEE},
	organization = {IEEE},
	abstract = {Model-Based Systems Engineering provides an effective methodology for designing complex systems and System-of-Systems. More importantly, such an approach opens the possibility to automatically generate executable simulators from system modules using model-to-code transformations, in order to verify the system model{\textquoteright}s completeness and validate design requirements. However, the user may still need to write code segments to describe the detailed functionality of system components. In this paper, we present the SCV2 tool, which allows the simulation of big size heterogeneous/multiple-class systems and system-of-systems, imposes code-model consistency and aided statechart design through reverse code-to-model transformations, and provides query-based requirement validation and functionality verification through an intuitive user interface. Finally, we present a use-case showing the utilization of the tool in the WiBRATE FP7 project for early-stage validation of system requirements.},
	keywords = {Automated Code Generation, Model-based System Engineering, SoSE, StateCharts, SysML, System-of-Systems, Validation and Verification},
	doi = {10.1109/SYSOSE.2015.7151960},
	url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7151960},
	author = {Baddour, Rami and Paspaliaris, Alkiviadis and Herrera, Daniel Solis}
}
@conference {18462,
	title = {Security Challenges for Hardware Designers of Mobile Systems},
	booktitle = {2015 Mobile Systems Technologies Workshop (MST)},
	year = {2015},
	month = {May},
	keywords = {cryptographic capabilities, cryptographic primitives, cryptography, hardware, hardware design flow, hardware designers, hardware trojan, Hardware Trojans, Integrated optics, malware, mobile communication, mobile computing, mobile device, mobile devices, Mobile handsets, mobile systems, Optical device fabrication, pervasive mobile devices, physical attack, physical attacks, security, security challenges, software malware, telecommunication security, Trojan horses},
	doi = {10.1109/MST.2015.11},
	author = {Milosevic, Jelena and Ferrante, Alberto and Regazzoni, Francesco}
}
@conference {18360,
	title = {Simulation and Analysis of Negative-Bias Temperature Instability Aging on Power Analysis Attacks},
	booktitle = {IEEE Int. Symposium on Hardware-Oriented Security and Trust},
	year = {2015},
	month = {05/2015},
	address = {McLean, VA, USA},
	author = {Guo, Xiaofei and Karimi, Nagmeh and Regazzoni, Francesco and Jin, Chenglu and Karri, Ramesh}
}
@conference {18476,
	title = {A survey on hardware trojan detection techniques},
	booktitle = {IEEE International Symposium on Circuits and Systems (ISCAS) 2015},
	year = {2015},
	month = {08/2015},
	pages = {2021-2024},
	publisher = {IEEE},
	organization = {IEEE},
	edition = {2015},
	address = {Lisbon, Portugal},
	abstract = {Hardware Trojans recently emerged as a serious issue for computer systems, especially for those used in critical applications such as medical or military. Trojan proposed so far can affect the reliability of a device in various ways. Proposed effects range from the leakage of secret information to the complete malfunctioning of the device. A crucial point for securing the overall operation of a device is to guarantee the absence of hardware Trojans. In this paper, we survey several techniques for detecting malicious modification of circuit introduced at different phases of the design flow. We also highlight their capabilities limitations in thwarting hardware Trojans.},
	keywords = {hardware Trojan detection techniques, integrated circuit reliability},
	isbn = {978-1-4799-8391-9},
	issn = {0271-4302},
	doi = {10.1109/ISCAS.2015.7169073},
	url = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=7152138},
	author = {Bhasin, Shivam and Regazzoni, Francesco}
}
@conference {18378,
	title = {Unifying Dependability of Critical Infrastructures: Electric Power System and ICT (Concepts, Figures of Merit and Taxonomy)},
	booktitle = {IEEE Pacific Rim International Symposium on Dependable Computing (PRDC)},
	year = {2015},
	month = {11/2015},
	address = {Zhangjiajie, China},
	abstract = {With Smart Grids efficiency of the electric power delivery service can be significantly increased by using advanced ICT infrastructure. The looming danger of merging two critical infrastructures, ICT and electric power, is that dependability may be compromised due to interdependencies and different approaches to dependability in the two communities. This calls for a unified approach to dependability which may be achieved by viewing Smart Grids as cyber-physical systems. We analyze and compare definitions and figures of merit used in ICT and electric power systems{\textquoteright} communities to provide the basis for dependability analysis of Smart Grids. We propose a taxonomy of faults for Smart Grids by examining a large set of previous power system outages. Our work relies on the analysis of relevant events from the past in an attempt to understand present dependability state of Smart Grids and pave the way for proactive grid management.},
	keywords = {Critical Infrastructures, Cyber-Physical, Dependability, Fault Taxonomy, smart grid},
	author = {Kaitovi{\'c}, Igor and Lukovi{\'c}, Slobodan and Malek, Miroslaw}
}
@conference {18469,
	title = {Accelerating differential power analysis on heterogeneous systems},
	booktitle = {The 9th Workshop on Embedded Systems Security (WESS) 2014},
	year = {2014},
	month = {10/2014},
	publisher = {ACM},
	organization = {ACM},
	address = {New Delhi, India},
	abstract = {Differential Power Analysis (DPA) attacks allows discovering the secret key stored into secure embedded systems by exploiting the correlation between the power consumed by a device and the data being processed. The computation involved is generally relatively simple, however, if the used power traces are composed by a large number of points, the processing time can be long. In this paper we aim at speeding up the so called correlation power analysis (CPA). To do so, we used the OpenCL framework to distribute the workload of the attack over an heterogeneous platform composed by a CPU and multiple accelerators. We concentrate in the computation of the Pearson{\textquoteright}s correlation coefficients, as they cover approximately 80\% of the overall execution time, and we further optimize the attack by minimizing the data transfers between the host processor and the GPUs. Our results show performance improvements of up to 9x when compared with the reference parallel implementation},
	keywords = {heterogeneous systems, power analysis},
	isbn = {978-1-4503-2932-3},
	doi = {10.1145/2668322.2668326},
	url = {http://doi.acm.org/10.1145/2668322.2668326},
	author = {Amaral, Joao and Regazzoni, Francesco and Tomas, Pedro and Chaves, Ricardo}
}
@article {18058,
	title = {A Combined Design-Time/Test-Time Study of the Vulnerability of Sub-Threshold Devices to Low Voltage Fault Attacks},
	journal = {IEEE Transactions on Emerging Topics in Computing},
	volume = {PP},
	issue = {99},
	year = {2014},
	month = {04/2014},
	abstract = {The continuous scaling of VLSI technology and the possibility to run circuits in subthreshold voltage range make it possible to implement standard cryptographic primitives within the very limited circuit and power budget of RFID devices. However, such cryptographic implementations raise concerns regarding their vulnerability to both active and passive side-channel attacks. In particular, when focusing on RFID targeted designs, it is important to evaluate their resistance against low cost physical attacks. A low cost fault injection attack can be mounted, for example, by lowering the supply voltage of the chip with the goal of causing setup time violations. In this paper, we provide an in-depth characterization of a chip implementation of the AES cipher. The chip has been designed using a 65nm low power standard cell library and operates in a subthreshold voltage range. We first show that it is possible to inject faults (through lowering the supply voltage) compliant with the fault models required to perform attacks against the AES cipher. We then investigate the possibility of predicting, at design time, which parts of the chip are more likely to be sensitive to such fault injection attacks and produce the desirable (from the point of view of the attacker) faulty behavior. Identifying such sensitive logic signals allows us to suggest to the designer a tailored countermeasure strategy for thwarting these attacks, with a minimal impact on the circuit{\textquoteright}s performance.},
	issn = {2168-6750},
	doi = {10.1109/TETC.2014.2316509},
	author = {Barenghi, Alessandro and Hocquet, C{\'e}dric and Bol, David and Standaert, Fran{\c c}ois-Xavier and Regazzoni, Francesco and Koren, Israel}
}
@conference {18296,
	title = {A Conceptual Solution for Integration of EV Charging with Smart Grids },
	booktitle = {International Conference on Smart Grid and Clean Energy Technologies - ICSGCE 2014 },
	year = {2014},
	month = {10/2014},
	address = {Dubai},
	abstract = {Coordinated charging of electric vehicles (EVs) represents one of important aspects of future smart grid
implementation. The main focus of the present work is on designing a conceptual architecture as a solution for
managing (mobile) electric storages utilization. The solution requires holistic approach which takes into consideration
all actors in power system management. Requirements and use-cases are specified, structural and behavioral models
are developed and presented. The ICT (Information and Communication Technologies) model of the architecture that
supports smart charging with dynamic pricing is developed using systems engineering methods. Results are verified
by means of system level simulations.},
	keywords = {dynamic pricing, electric vehicles, Smart charging, systems engineering},
	author = {Lukovi{\'c}, Slobodan and Miladinovic, Bojan}
}
@conference {18091,
	title = {DRuiD: Designing Reconfigurable Architectures with Decision-making Support},
	booktitle = {19th Asia and South Pacific Design Automation Conference (ASP-DAC)},
	year = {2014},
	month = {01/2014},
	address = {Singapore},
	url = {http://home.deib.polimi.it/gpalermo/papers/ASPDAC14DRUID.pdf},
	author = {Mariani, Giovanni and Meeuws, Roel and Palermo, Gianluca and Sima, Vlad-Mihai and Silvano, Cristina and Bertels, Koen}
}
@conference {18464,
	title = {Embedded Systems Education: Job Market Expectations},
	booktitle = {Workshop on Embedded and Cyber-Physical Systems Education (WESE) },
	year = {2014},
	month = {10/2014},
	publisher = {ACM},
	organization = {ACM},
	address = {New Delhi, India},
	abstract = {In the fifteen years since the first Embedded Systems Design Master studies were proposed the embedded systems world has radically changed. The spectrum of application areas has increased beyond any expectation, and the increasing presence of embedded systems in the physical world has led to "cyber-physical systems." Devices tend to become a commodity in many cases, while sensors and IPs acquire a larger share of the market. The whole industrial ecosystem is changing as well, with "application" companies becoming increasingly present and SMEs emerging as major players. It becomes mandatory to reconsider the competences and capacities that should be provided in a Master of Science course oriented to Embedded Systems Design, so as to meet new and diverse requests that come from job market and prospective employers. Within the frame of the Nano-Tera Swiss Federal program (www.nano-tera.ch), the educational project Future Embedded Systems Education (FESTE) aimed at identifying requests coming from the job market, so as to outline the renewed professional profile for young Embedded Systems Designers. The results indicate that programming, networking, real time and system architecture know-how combined with soft skills such as teamwork and communication are in demand and frequently come under disguised names such as automation or control engineering.},
	keywords = {Cyber-Physical Systems Education, embedded systems, Nano Tera program},
	isbn = {978-1-4503-3090-9},
	url = {http://doi.acm.org/10.1145/2829957.2829961},
	author = {Sami, Mariagiovanna and Malek, Miroslaw and Bondi, Umberto and Regazzoni, Francesco}
}
@conference {18165,
	title = {ExCovery {\textendash} A Framework for Distributed System Experiments and a Case Study of Service Discovery},
	booktitle = {28th International Parallel \& Distributed Processing Symposium, Workshops and Phd Forum (IPDPSW)},
	year = {2014},
	month = {05/2014},
	publisher = {IEEE Computer Society},
	organization = {IEEE Computer Society},
	address = {Phoenix, AZ, USA},
	abstract = {Experiments are a fundamental part of science. They are needed when the system under evaluation is too complex to be analytically described and they serve to empirically validate hypotheses. This work presents the experimentation framework <i>ExCovery</i> for dependability analysis of distributed processes. It provides concepts that cover the description, execution, measurement and storage of experiments. These concepts foster transparency and repeatability of experiments for further sharing and comparison. <i>ExCovery</i> has been tried and refined in a manifold of dependability related experiments during the last two years. A case study is provided to describe service discovery as experiment process. A working prototype for IP networks runs on the Distributed Embedded System (DES) wireless testbed at the Freie Universit{\"a}t Berlin.},
	keywords = {Distributed Systems, Experiment Framework, Experiments, Tool Description},
	isbn = {978-1-4799-4116-2/14},
	doi = {10.1109/IPDPSW.2014.147},
	url = {http://andreas-dittrich.eu/2014/03/excovery},
	author = {Dittrich, Andreas and Wanja, Stefan and Malek, Miroslaw}
}
@article {18049,
	title = {Fault-Tolerant Network Interfaces for Networks-on-Chip},
	journal = {IEEE Trans. Dependable Secur. Comput.},
	volume = {11},
	issue = {1},
	year = {2014},
	month = {01/2014},
	pages = {16{\textendash}29},
	keywords = {fault tolerance, high-level error models, network interface, Networks-on-chip, online fault detection, reliability},
	issn = {1545-5971},
	doi = {10.1109/TDSC.2013.28},
	author = {Fiorin, Leandro and Sami, Mariagiovanna}
}
@conference {18088,
	title = {Malicious Wave: a Survey on Actively Tampering Using Electromagnetic Glitch},
	booktitle = {International Symposium on Electromagnetic Compatibility 2014},
	year = {2014},
	month = {08/2014},
	author = {Bhasin, Shivam and Maistri, Paolo and Regazzoni, Francesco}
}
@conference {18233,
	title = {Modeling Requirements For Security-enhanced Design of Embedded Systems},
	booktitle = {ICETE SECRYPT},
	year = {2014},
	month = {08/2014},
	publisher = {ICETE},
	organization = {ICETE},
	address = {Vienna, Austria},
	author = {Ferrante, Alberto and Kaitovi{\'c}, Igor and Milosevic, Jelena}
}
@inbook {18024,
	title = {Modeling Responsiveness of Decentralized Service Discovery in Wireless Mesh Networks},
	booktitle = {MMB \& DFT},
	series = {Lecture Notes in Computer Science},
	volume = {8376},
	year = {2014},
	pages = {88-102},
	publisher = {Springer International Publishing Switzerland},
	organization = {Springer International Publishing Switzerland},
	abstract = {In modern service networks, discovery plays a crucial role as a layer where providing instances of a given service can be published and enumerated. Since successful discovery is mandatory for service usage, comprehensive service dependability assessment needs to incorporate the dependability of the discovery layer. This work focuses on the responsiveness of the discovery layer, the probability to operate successfully within a deadline, even in the presence of faults. It proposes a hierarchy of stochastic models for decentralized discovery and uses it to describe the discovery of a single service using three well-known discovery protocols: domain name system based service discovery (DNS-SD), simple service discovery protocol (SSDP) and service location protocol (SLP). Further, a methodology to use the model hierarchy in wireless mesh networks is introduced. Given a pair service requester and provider, a discovery protocol and a deadline, it estimates packet loss probabilities and transmission time distributions for each link on the communication paths between the pair, generates specific model instances and calculates the expected responsiveness. Finally, the paper introduces a new metric, the expected responsiveness distance d_er to estimate the maximum distance from a provider where requesters are still able to discover it with a required responsiveness. The models and their methodology are demonstrated using monitoring data from the distributed embedded systems (DES) testbed at Freie Universit{\"a}t Berlin. It is shown how the responsiveness and d_er of the protocols change depending on the position of requester and provider and the overall link quality in the network.},
	keywords = {fault tolerance, Markov Models, Real time systems, Responsiveness, Service Discovery, Wireless mesh networks},
	isbn = {978-3-319-05358-5},
	issn = {0302-9743},
	doi = {10.1007/978-3-319-05359-2_7},
	url = {http://andreas-dittrich.eu/2013/12/modeling-responsiveness-of-decentralized-service-discovery-in-wireless-mesh-networks},
	author = {Dittrich, Andreas and Lichtblau, Bj{\"o}rn and Rezende, Rafael and Malek, Miroslaw},
	editor = {Fischbach, K. and Krieger, U. R.}
}
@conference {18043,
	title = {Probabilistic Breadth-First Search {\textendash} A Method for Evaluation of Network-Wide Broadcast Protocols},
	booktitle = {6th IEEE/ACM/IFIP International Conference on New Technologies, Mobility and Security (NTMS)},
	year = {2014},
	month = {03/2014},
	publisher = {IEEE Computer Society},
	organization = {IEEE Computer Society},
	address = {Dubai, UAE},
	abstract = {In wireless mesh networks (WMNs), network-wide broadcasts (NWBs) are a fundamental operation, required by routing and other mechanisms that distribute information to all nodes in the network. However, due to the characteristics of wireless communication, NWBs are generally problematic. Optimizing them is thus a prime target when improving the overall performance and dependability of WMNs. Most of the existing optimizations neglect the real nature of WMNs and are based on simple graph models, which provide optimistic assumptions of NWB dissemination. On the other hand, models that fully consider the complex propagation characteristics of NWBs quickly become unsolvable due to their complexity. In this paper, we present the Monte Carlo method probabilistic breadth-first search (PBFS) to approximate the reachability of NWB protocols. PBFS simulates individual NWBs on graphs with probabilistic edge weights, which reflect link qualities of individual wireless links in the WMN, and estimates reachability over a configurable number of simulated runs. This approach is not only more efficient than existing ones, but further provides additional information such as the distribution of path lengths. Furthermore, it is easily extensible to NWB schemes other than flooding. The applicability of PBFS is validated both theoretically and empirically, in the latter by comparing reachability as calculated by PBFS and measured in a real-world WMN. Validation shows that PBFS quickly converges to the theoretically correct value and approximates the behaviour of real-life testbeds very well. The feasibility of PBFS to support research on NWB optimizations or higher level protocols that employ NWBs is demonstrated in two use cases.},
	keywords = {Monte Carlo methods, Network-wide broadcasts, Probabilistic network graphs, Wireless mesh networks},
	isbn = {9781479932238},
	doi = {10.1109/NTMS.2014.6814046},
	url = {http://andreas-dittrich.eu/2014/01/pbfs},
	author = {Lichtblau, Bj{\"o}rn and Dittrich, Andreas}
}
@conference {18206,
	title = {A Resource-optimized Approach to Efficient Early Detection of Mobile Malware},
	booktitle = {3rd International Workshop on Security of Mobile Applications - IWSMA 2014},
	year = {2014},
	month = {09/2014},
	address = {Fribourg, Switzerland},
	author = {Milosevic, Jelena and Dittrich, Andreas and Ferrante, Alberto and Malek, Miroslaw}
}
@conference {18232,
	title = {Responsiveness of Service Discovery in Wireless Mesh Networks},
	booktitle = {20th Pacific Rim International Symposium on Dependable Computing (PRDC)},
	year = {2014},
	month = {11/2014},
	publisher = {IEEE Computer Society},
	organization = {IEEE Computer Society},
	address = {Singapore},
	abstract = {Service Discovery (SD) is an integral part of service networks. Before a service can be used, it needs to be discovered successfully. Comprehensive service dependability analysis thus needs to include the SD process. As a time-critical operation, an important property of SD is responsiveness: The probability of successful discovery within a deadline, even in the presence of faults. This is especially true for dynamic networks with complex fault behavior such as wireless networks. This work evaluates the responsiveness of decentralized SD in wireless mesh networks. For this reason, the experiment framework ExCovery has been employed, which provides a unified description, execution, measurement and storage of experiments. ExCovery runs on the Distributed Embedded System (DES) wireless testbed at Freie Universit{\"a}t Berlin. We present and discuss the results of the experiments and show how responsiveness is affected by the position and number of requester and providers as well as the load in the network. The results clearly demonstrate that in all but the most favorable conditions, the configurations of current SD protocols struggle to achieve a high responsiveness.},
	keywords = {Experiments, Responsiveness, Service Discovery, Wireless mesh networks, Zeroconf},
	doi = {10.1109/PRDC.2014.38},
	url = {http://andreas-dittrich.eu/2014/06/prdc2014},
	author = {Dittrich, Andreas and Herrera, Daniel Solis and Coto, Pablo and Malek, Miroslaw}
}
@conference {18227,
	title = {Risk Assessment of Atrial Fibrillation: a Failure Prediction Approach},
	booktitle = {41st Computing in Cardiology Conference (CinC)},
	year = {2014},
	month = {09/2014},
	publisher = {IEEE Computer Society},
	organization = {IEEE Computer Society},
	address = {Cambridge, MA, USA},
	abstract = {We present a methodology for identifying patients who have experienced Paroxysmal Atrial Fibrillation (PAF) among a given subjects population. Our work is intended as an initial step towards the design of an unobtrusive system for concurrent detection and monitoring of chronic cardiac conditions.

Our methodology comprises two stages: off-line training and on-line analysis. During training the most significant features are selected using machine-learning methods, without relying on a manual selection based on previous knowledge. Analysis is based on two phases: feature extraction and detection of PAF patients. Light-weight algorithms are employed in the feature extraction phase, allowing the on-line implementation of this step on wearable and resource-constrained sensor nodes. The detection phase employs techniques borrowed from the field of failure prediction. While these algorithms have found extensive applications in diverse scenarios, their application to automated cardiac analysis has not been sufficiently investigated.

Obtained results, in terms of performance, are comparable to similar efforts in the field. Nonetheless, the proposed method employs computationally simpler and more efficient algorithms, which are compatible with the computational constraints of state-of-the-art body sensor nodes.},
	url = {http://andreas-dittrich.eu/2014/06/risk-assessment-of-atrial-fibrillation-a-failure-prediction-approach},
	author = {Milosevic, Jelena and Dittrich, Andreas and Ferrante, Alberto and Malek, Miroslaw and Rojas Quiros, Camilo and Braojos, Rub{\'e}n and Ansaloni, Giovanni and Atienza, David}
}
@inbook {18065,
	title = {Security IPs and IP Security with FPGAs},
	booktitle = {Secure Smart Embedded Devices Platform and Applications},
	year = {2014},
	author = {Durvaux, Fran{\c c}ois and Kerckhof, St{\'e}phanie and Regazzoni, Francesco and Standaert, Fran{\c c}ois-Xavier},
	editor = {Markantonakis, Konstantinos}
}
@article {18467,
	title = {Simulation-Time Security Margin Assessment against Power-Based Side Channel Attacks},
	journal = {(IACR) Cryptology ePrint Archive},
	volume = {2014},
	year = {2014},
	month = {05/2014},
	chapter = {307},
	abstract = {A sound design time evaluation of the security of a digital device is a goal which has attracted a great amount of research effort lately. Common security metrics for the attack consider either the theoretical leakage of the device, or assume as a security metric the number of measurements needed in order to be able to always recover the secret key. In this work we provide a combined security metric taking into account the computational effort needed to lead the attack, in combination with the quantity of measurements to be performed, and provide a practical lower bound for the security margin which can be employed by a secure hardware designer. This paper represents a first exploration of a design-time security metric incorporating the computational effort required to lead a power- based side channel attack in the security level assessment of the device. We take into account in our metric the possible presence of masking and hiding schemes, and we assume the best measurement conditions for the attacker, thus leading to a conservative estimate of the security of the device. We provide a practical validation of our security metric through an analysis of transistor-level accurate power simulations of a 128-bit AES core implemented on a 65 nm library.},
	keywords = {AES, implementation, Side-channel analysis},
	author = {Barenghi, Alessandro and Pelosi, Gerardo and Regazzoni, Francesco}
}
@conference {18470,
	title = {Single-Photon Avalanche Diodes (SPADs) for quantum random number generators and beyond},
	booktitle = {19th Asia and South Pacific Design Automation Conference (ASP-DAC) 2014},
	year = {2014},
	month = {01/2014},
	publisher = {IEEE},
	organization = {IEEE},
	address = {Singapore},
	abstract = {Single-Photon Avalanche Diodes (SPADs) are solid-state photo-detectors capable of detecting single photons by exploiting the avalanche effect that occurs in the breakdown of a p-n junction biased above breakdown voltage. By this effect, a SPAD translates an incoming photon to a macroscopic current pulse. These devices are currently used for building medical devices characterized by a very high time resolution. An appealing application of SPAD is to use them as a basic block for building the entropy source of true random number generators. In this paper we focus on such application, and we explore the design challenges behind the realization of a quantum random number generator based on a massively parallel array of SPADs. The matrix under investigation comprises 512{\texttimes}128 independent cells that convert photons onto a raw bit-stream, which, as ensured by the properties of quantum physics, is characterized by a very high level of randomness. The sequences are read out in a 128-bit parallel bus, concatenated, and pipelined onto a de-biasing filter. Subsequently, we fabricated the proposed chip using a standard CMOS process. Our results, achieved on the manufactured device and coupling two matrices, show that our architecture can reach up to 5 Gbit/s while consuming 25pJ/bit, thus demonstrating scalability and performance for any random number generators based on SPADs},
	keywords = {quantum physics, random number generators, SPAD},
	isbn = {978-1-4799-2816-3},
	url = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6736726},
	author = {Regazzoni, Francesco and Burri, Samuel and Stucki, Damien and Maruyama, Yuki and Bruschini, Claudio and Charbon, Edoardo}
}
@conference {18251,
	title = {Smart Charging Cell for Smart Cities},
	booktitle = {The 2nd IEEE International Workshop on Intelligent Energy Systems (IWIES) },
	year = {2014},
	month = {08/2014},
	abstract = {Energy consumption can be to some extent steered not only in time but in special cases in space as well. This mostly concerns electric vehicles (EV) charging. In this work we present conceptual solution of a {\textquoteleft}GeoGreen Cell{\textquoteright} developed in scope of an international project {\textendash} Ge(o)Green. The main purpose of such an aggregation is to efficiently coordinate. EV charging with respect to price of energy both in time and space. Even though massive acceptance of EVs seems far, there is an emerging need for conceptual solutions and reference models of solutions for their seamless integration into energy system in particular in urban areas. In fact, system level models of the supporting ICT architecture, including structural and behavioral ones, have been
developed. The models have been verified by means of simulations to assure their correctness. Scheduling optimization algorithms have been created and the system has been validated by means of system-level simulations.},
	keywords = {aggregation, EV charging, structural and behavioral models, SyML},
	author = {Lukovi{\'c}, Slobodan and Kaitovi{\'c}, Igor}
}
@article {18059,
	title = {Stealthy Dopant-Level Hardware Trojans: Extended Version},
	journal = {Journal of Cryptographic Engineering},
	volume = {4},
	issue = {1},
	year = {2014},
	month = {04/2014},
	pages = {19-31},
	abstract = {In recent years, hardware Trojans have drawn the attention of governments and industry as well as the scientific community. One of the main concerns is that integrated circuits, e.g., for military or critical-infrastructure applications, could be maliciously manipulated during the manufacturing process, which often takes place abroad. However, since there have been no reported hardware Trojans in practice yet, little is known about how such a Trojan would look like and how difficult it would be in practice to implement one. In this paper we propose an extremely stealthy approach for implementing hardware Trojans below the gate level, and we evaluate their impact on the security of the target device. Instead of adding additional circuitry to the target design, we insert our hardware Trojans by changing the dopant polarity of existing transistors. Since the modified circuit appears legitimate on all wiring layers (including all metal and polysilicon), our family of Trojans is resistant to most detection techniques, including fine-grain optical inspection and checking against {\textquotedblleft}golden chips{\textquotedblright}. We demonstrate the effectiveness of our approach by inserting Trojans into two designs{\textemdash}a digital post-processing derived from Intel{\textquoteright}s cryptographically secure RNG design used in the Ivy Bridge processors and a side-channel resistant SBox implementation{\textemdash}and by exploring their detectability and their effects on security.},
	keywords = {Hardware Trojans, Layout modifications, Malicious hardware, Trojan side-channel},
	issn = {2190-8516},
	doi = {10.1007/s13389-013-0068-0},
	author = {Becker, Georg and Regazzoni, Francesco and Paar, Christof and Burleson, Wayne}
}
@conference {18468,
	title = {(THOR) - The hardware onion router},
	booktitle = {24th International Conference on Field Programmable Logic and Applications, (FPL) 2014},
	year = {2014},
	month = {09/2014},
	publisher = {IEEE},
	organization = {IEEE},
	address = {Munich, Germany},
	abstract = {Security and privacy of data traversing internet have always been a major concern for all users. In this context, The Onion Routing (Tor) is the most successful protocol to anonymize global Internet traffic and is widely deployed as software on many personal computers or servers. In this paper, we explore the potential of modern reconfigurable devices to efficiently realize the Tor protocol on embedded devices. In particular, this targets the acceleration of the complex cryptographic operations involved in the handshake of routing nodes and the data stream encryption. Our hardware-based implementation on the Xilinx Zynq platform outperforms previous embedded solutions by more than a factor of 9 with respect to the cryptographic handshake - ultimately enabling quite inexpensive but highly efficient routers. Hence, we consider our work as a further milestone towards the development and the dissemination of low-cost and high performance onion relays that hopefully ultimately leads again to a more private Internet.},
	keywords = {cyptographic protocol, encryption, hardware, onion routing protocol, security, THOR},
	url = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6913605},
	author = {G{\"u}neys, Tim and Regazzoni, Francesco and Sasdrich, Pascal and Wojcik, Marcin}
}
@conference {18047,
	title = {Time of Flight Error Compensation for In-Tunnel Vehicle Localization},
	booktitle = {The Fourth International Workshop on Pervasive Networks for Emergency Management, 2014 (PerNEM{\textquoteright}14)},
	year = {2014},
	month = {03/2014},
	publisher = {IEEE},
	organization = {IEEE},
	address = {Budapest, Hungary},
	keywords = {calibration, position estimation, time of flight, vehicle localization, wireless sensor networks},
	doi = {10.1109/PerComW.2014.6815226},
	author = {Bala{\'c}, Katarina and Di Giulio, Pablo Andres and Taddeo, Antonio Vincenzo and Prevostini, Mauro}
}
@inbook {18053,
	title = {Towards a Reliability-aware Design Flow for Kahn Process Networks on NoC-based Multiprocessors},
	booktitle = {10th Workshop on Dependability and Fault Tolerance (ARCS/VERFE{\textquoteright}14)},
	series = {Lecture Notes on Computer Science},
	year = {2014},
	publisher = {Springer},
	organization = {Springer},
	address = {L{\"u}beck, Germany},
	abstract = {In order to satisfy performance and low power requirements of applications, embedded systems are becoming increasingly complex and highly integrated with various types of cores. As complexity increases and CMOS technology scales down into the deep-submicron domain, the rate of hard and soft faults in such systems increases. Such trend requires the reliability aspect to be incorporated as a design goal along with the more conventional goals such as performance, cost and power. In this paper, we investigate the reliability achieved by two system-level fault tolerance techniques, namely online task remapping and N-modular redundancy. By means of an analytical model of applications represented as Kahn Process Networks running on heterogeneous multiprocessors based on Networks-on-Chip, we evaluate these techniques with respect to the obtained level of reliability (mean-time-to-failure) and the overhead in computation (execution time) and communication (amount of data transfer on the network). By presenting a reliability estimation method, we enable a reliability-aware design flow on NoC-based MPSoCs.},
	keywords = {fault tolerance, kahn process networks (KPN), networks-on-chip (NoC), reliability},
	author = {Derin, Onur and Fiorin, Leandro}
}
@conference {17770,
	title = {Adapting Multi-Agent Systems Approach for Integration of Prosumers in Smart Grids},
	booktitle = {Proceedings of the IEEE Eurocon 2013},
	year = {2013},
	month = {July},
	abstract = {Massive deployment of distributed energy resources, predominately renewable, is expected to be a general trend in the near future. Integration of such elements in distribution grid represents one of key challenges that Smart Grids will have to face with. In this work we aim at bridging
industrial and academic views on future trends in this field. We list main issues to be tackled and we propose a conceptual system-level solution based on Multi-Agent Systems. We show basic functionalities and structure for supporting ICT architecture.},
	author = {Lukovi{\'c}, Slobodan},
	editor = {Kovac, Boksov}
}
@conference {17578,
	title = {An Algorithm for Extended Dynamic Range Video in Embedded Systems},
	booktitle = {SENSORNETS 2013 - 2nd International Conference on Sensor Networks},
	year = {2013},
	month = {02/2013},
	publisher = {INSTICC},
	organization = {INSTICC},
	address = {Barcelona, Spain},
	keywords = {embedded systems, extended dynamic range, HDR, image processing, sensor, videocamera},
	author = {Ferrante, Alberto and Chelodi, Massimo and Bruschi, Francesco and Mozzetti, Valeria}
}
@article {17735,
	title = {ARTE: an Application-specific Run-Time Management Framework for Multi-cores based on Queuing Models},
	journal = {Parallel Computing},
	year = {2013},
	author = {Mariani, Giovanni and Palermo, Gianluca and Zaccaria, Vittorio and Silvano, Cristina}
}
@article {18060,
	title = {Automatic Application of Power Analysis Countermeasures},
	journal = {IEEE Transactions on Computers},
	volume = {PP},
	issue = {99},
	year = {2013},
	month = {12/2013},
	abstract = {We introduce a compiler that automatically inserts software countermeasures to protect cryptographic algorithms against power-based side-channel attacks. The compiler first estimates which instruction instances leak the most information through side-channels. This information is obtained either by dynamic analysis, evaluating an information theoretic metric over the power traces acquired during the execution of the input program, or by static analysis. As information leakage implies a loss of security, the compiler then identifies (groups of) instruction instances to protect with a software countermeasure such as random precharging or Boolean masking. As software protection incurs significant overhead in terms of cryptosystem runtime and memory usage, the compiler protects the minimum number of instruction instances to achieve a desired level of security. The compiler is evaluated on two block ciphers, AES and Clefia; our experiments demonstrate that the compiler can automatically identify and protect the most important instruction instances. To date, these software countermeasures have been inserted manually by security experts, who are not necessarily the main cryptosystem developers. Our compiler offers significant productivity gains for cryptosystem developers who wish to protect their implementations from side-channel attacks.},
	issn = {0018-9340},
	doi = {10.1109/TC.2013.219},
	author = {Bayrak, Ali Galip and Regazzoni, Francesco and Novo Bruna, David and Brisk, Philip and Standaert, Fran{\c c}ois-Xavier and Ienne, Paolo}
}
@conference {17741,
	title = {Calibration and in-Field Validation Tests of a Web-based Adaptive Management System for Monitoring - Scaphoideus titanus},
	booktitle = {Future Integrated Pest Management in Europe},
	year = {2013},
	abstract = {We developed a Web-based Adaptive Management System (WAMS) within a research project, called "SMART VINEYARD", which was funded by the Swiss Federal Commission for Technology and Innovation (Project 11307.1 PFES-ES). Goal of the project was to address the challenge of proposing a decision support system to provide real-time forecast of the life stages of - Scaphoideus titanus, vector of flavescence dor{\'e}e. The benefit of using the WAMS is to decide the timing of insecticide application and the planning of in-field monitoring tasks.},
	author = {Prevostini, Mauro and Taddeo, Antonio Vincenzo and Bala{\'c}, Katarina and Jermini, Mauro and Linder, Christian}
}
@conference {17768,
	title = {Characterization of In-tunnel Distance Measurements for Vehicle Localization},
	booktitle = {IEEE Wireless Communications and Networking Conference (WCNC)},
	year = {2013},
	address = {Shanghai, P.R. China},
	abstract = {An increased number of vehicular applications and services requires accurate distance measurements. Due to specific properties of radio waves propagation, it may not be effective to use ranging systems designed for other environments inside tunnels. In this paper we analysed the characteristics of time of flight based ranging for in-tunnel applications. Based on our analysis, we designed a vehicle localization system showing that the time of flight approach is a suitable, accurate and cost effective solution for this purpose. We designed and validated our solution by performing real experiments in a tunnel located in Lugano, Switzerland.},
	author = {Widmann, Daniel and Bala{\'c}, Katarina and Taddeo, Antonio Vincenzo and Prevostini, Mauro and Puiatti, Alessandro}
}
@conference {18069,
	title = {Comparison of Two Cameras based on Single Photon Avalanche Diodes (SPADS) for Fluorescence Lifetime Imaging Application with Picosecond Resolution},
	booktitle = {International Image Sensor Workshop (IISW)},
	year = {2013},
	month = {June},
	address = {Snowbird Resort, Utah, USA},
	author = {Powolny, Fran{\c c}ois and Burri, Samuel and Bruschini, Claudio and Michalet, Xavier and Regazzoni, Francesco and Charbon, Edoardo}
}
@article {18048,
	title = {A Configurable Monitoring Infrastructure for NoC-Based Architectures},
	journal = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
	volume = {PP},
	issue = {99},
	year = {2013},
	abstract = {In this brief, we propose a monitoring architecture for networks-on-chip that provides system information useful for designers to efficiently exploit, at design time and run-time, the system resources available in multiprocessor system-on-chip platforms. We focus on the analysis of the architectural details and design challenges of such a system, by describing powerful tools for monitoring information that can be used both at run-time for detecting dynamic changes in system behavior and at post-execution time for debugging and profiling of applications. This brief describes the design of the monitoring probes, together with the events detectable by them, and discusses an architecture for collecting, storing, and analyzing the information gathered during an application execution.},
	keywords = {hardware counters, networks-on-chip (NoCs), performance monitoring, systems-on-chip (SoCs).},
	issn = {1063-8210},
	doi = {10.1109/TVLSI.2013.2290102},
	author = {Fiorin, Leandro and Palermo, Gianluca and Silvano, Cristina}
}
@article {18093,
	title = {Design-space Exploration and Runtime Resource Management for Multicores},
	journal = {ACM Transactions on Embedded Computing Systems (TECS) - Special issue on application-specific processors},
	volume = {13},
	issue = {2},
	year = {2013},
	month = {09/2013},
	pages = {20:1{\textendash}20:27},
	abstract = {Application-specific multicore architectures are usually designed by using a configurable platform in which a set of parameters can be tuned to find the best trade-off in terms of the selected figures of merit (such as energy, delay, and area). This multi-objective optimization phase is called Design-Space Exploration (DSE). Among the design-time (hardware) configurable parameters we can find the memory subsystem configuration (such as cache size and associativity) and other architectural parameters such as the instruction-level parallelism of the system processors. Among the runtime (software) configurable parameters we can find the degree of task-level parallelism associated with each application running on the platform.

The contribution of this article is twofold; first, we introduce an evolutionary (NSGA-II-based) methodology for identifying a hardware configuration which is robust with respect to applications and corresponding datasets. Second, we introduce a novel runtime heuristic that exploits design-time identified operating points to provide guaranteed throughput to each application. Experimental results show that the design-time/runtime combined approach improves the runtime performance of the system with respect to existing reference techniques, while meeting the overall power budget.},
	keywords = {application-specific platforms, design-space exploration, genetic algorithms, Multicore architectures, operating systems, resource reservation, runtime resource management, throughput maximization},
	issn = {1539-9087},
	doi = {10.1145/2514641.2514647},
	author = {Mariani, Giovanni and Palermo, Gianluca and Zaccaria, Vittorio and Silvano, Cristina}
}
@conference {18072,
	title = {An eda-friendly protection scheme against side-channel attacks},
	booktitle = {Design, Automation and Test in Europe (DATE)},
	year = {2013},
	month = {March},
	address = {Grenoble, France},
	author = {Bayrak, Ali Galip and Velickovic, Nikola and Regazzoni, Francesco and Novo Bruna, David and Brisk, Philip and Ienne, Paolo}
}
@article {18061,
	title = {A Fast ULV Logic Synthesis Flow in Many-Vt CMOS Processes for Minimum Energy under Timing Constraints},
	journal = {IEEE Transactions on Circuits and Systems II},
	volume = {59},
	issue = {12},
	year = {2013},
	pages = {947-951},
	abstract = {Ultra-low-voltage (ULV) logic offers the opportunity to operate at the minimum-energy point (MEP) for applications with low-to-medium speed requirements. Unfortunately, the critical design constraint of achieving a reliable timing closure at the target frequency of the application becomes very complex in the wide design space of ULV including supply (Vdd) and threshold (Vt) voltage selection as well as netlist optimizations from the synthesis. In this paper, we propose a fast synthesis flow to accurately predict the Vdd/Vt MEP under strict timing constraints. Compared to an exhaustive search for the MEP under timing constraints based on numerous library recharacterizations and synthesis steps for all Vdd/Vt pairs, the proposed ULV flow dramatically speeds up the design process. Indeed, it requires a single library recharacterization and only three synthesis steps. Results obtained for several ITC{\textquoteright}99 benchmarks under a wide range of timing constraints from 0.1 to 30 MHz in 65-nm LP/GP CMOS demonstrate that the proposed flow has a less than 10\% energy penalty with respect to the absolute MEP computed with an exhaustive search and energy savings enhanced up to 2.4{\texttimes} compared to a conventional flow with Vdd scaling only.},
	issn = {1549-7747},
	doi = {10.1109/TCSII.2012.2231034},
	author = {Bol, David and Hocquet, C{\'e}dric and Regazzoni, Francesco}
}
@conference {18068,
	title = {Jailbreak Imagers: Transforming a Single-Photon Image Sensor into a True Random Number Generator},
	booktitle = {International Image Sensor Workshop (IISW)},
	year = {2013},
	month = {June},
	address = {Snowbird Resort, Utah, USA},
	author = {Burri, Samuel and Stucki, Damien and Maruyama, Yuki and Bruschini, Claudio and Charbon, Edoardo and Regazzoni, Francesco}
}
@conference {18071,
	title = {Lightweight AES-Based Authenticated Encryption},
	booktitle = {Fast Software Encryption (FSE)},
	year = {2013},
	month = {March},
	address = {Singapore},
	author = {Bogdanov, Andrey and Mendel, Florian and Regazzoni, Francesco and Rijmen, Vincent and Tischhauser, Elmar}
}
@conference {17730,
	title = {A Low Overhead Self-adaptation Technique for KPN Applications on NoC-based MPSoCs},
	booktitle = {Proceedings of the 3rd International Conference on Pervasive and Embedded Computing and Communication Systems (PECCS) - Special Session on Self-Adaptive Networked Embedded Systems (SANES)},
	year = {2013},
	month = {February 19-21},
	address = {Barcelona, Spain},
	abstract = {Self-adaptive systems are able to adapt themselves to mutating internal/external conditions so as to meet their goals. One of the challenges to be tackled when designing such systems is the overhead introduced in making the system monitorable and adaptable. A large overhead can easily compensate the benefits of adaptation. In this work, we are addressing this challenge within the context of KPN applications on NoC-based MPSoCs. In particular, parametric adaptations at the application level are considered. We present a low overhead technique for the implementation of the monitor-controller-adapter loop, which is present in self-adaptive systems. The technique is fundamentally based on an extended network interface which provides the ability to interrupt remote tiles on a NoC-based multiprocessor platform. Results from the MJPEG case study show that the proposed interrupt-based approach incurs an overhead as low as 0.4\% without compromising the quality of the adaptation control. Our new technique provides an improvement of approximately 6.25\% compared to another state-of-the-art technique that interacts with the application using KPN semantics (i.e., blocking channels). Moreover, the sensitivity of the overhead to the complexity of the adaptation controller is much lower in case of our interrupt-based technique as compared to the blocking channel based scheme.},
	keywords = {event-based control, kahn process networks (KPN), network-on-chip (NoC), self-adaptivity},
	author = {Derin, Onur and Ramankutty, Prasanth Kuncheerat and Meloni, Paolo and Tuveri, Giuseppe}
}
@conference {17729,
	title = {A Model for the Evaluation of User-Perceived Service Properties},
	booktitle = {International Symposium on Parallel Distributed Processing, Workshops and Phd Forum (IPDPSW)},
	year = {2013},
	month = {May},
	publisher = {IEEE Computer Society},
	organization = {IEEE Computer Society},
	address = {Boston, Massachusetts, USA},
	abstract = {An ever-increasing number of both functional and non-functional requirements has resulted in growing system complexity which demands new solutions in system modeling and evaluation. As a remedy, service-oriented architecture (SOA) offers services as basic building elements of system design. Service dependability is highly dependent on the properties of the underlying information and communications technology (ICT) infrastructure. This is especially true for the user-perceived dependability of a specific pair service client and provider as every pair may utilize different ICT components. We provide a model for the description of ICT components and their non-functional properties based on the Unified Modeling Language (UML). Given a service description, a network topology model and a pair service client and provider, we propose a methodology to automatically identify relevant ICT components and generate a user-perceived service infrastructure model (UPSIM). We demonstrate the feasibility of the methodology by applying it to parts of the service network infrastructure at Universit{\`a} della Svizzera italiana, Switzerland. We then show how this methodology can be used to facilitate user-perceived service dependability analysis.},
	keywords = {availability, design engineering, metamodeling, modeling, object oriented modeling, quality of service (QoS), service dependability, service network management, service networks},
	isbn = {978-0-7695-4979-8},
	doi = {10.1109/IPDPSW.2013.163},
	url = {http://andreas-dittrich.eu/2013/03/a-model-for-the-evaluation-of-user-perceived-service-properties},
	author = {Dittrich, Andreas and Kaitovi{\'c}, Igor and Murillo, Cristina and Rezende, Rafael}
}
@inbook {17731,
	title = {Model-Driven Evaluation of User-Perceived Service Availability},
	booktitle = {Dependable Computing},
	series = {Lecture Notes in Computer Science},
	volume = {7869},
	year = {2013},
	month = {May},
	pages = {39-53},
	publisher = {Springer Berlin Heidelberg},
	organization = {Springer Berlin Heidelberg},
	abstract = {Service-oriented architecture (SOA), which proposes services as basic building elements of system design, has emerged as an approach to master growing system complexity. However, it remains difficult to evaluate dependability of such distributed and heterogeneous functionality as it depends highly on the properties of the enabling information and communications technology (ICT) infrastructure. Moreover, every specific pair service client and provider can utilize different ICT components, constituting for the user-perceived view of a service. We provide a model-driven methodology to automatically create reliability block diagrams of such views. Given a service description, a network topology model and a pair service client and provider, it identifies relevant ICT components and generates a user-perceived service availability model (UPSAM). We then use this UPSAM to calculate the steady-state availability of different views on an examplary mail service deployed in the network infrastructure of University of Lugano.},
	keywords = {availability, design engineering, modeling, object oriented modeling, quality of service (QoS), service dependability, service network management, service networks},
	issn = {978-3-642-38788-3},
	doi = {10.1007/978-3-642-38789-0_4},
	url = {http://andreas-dittrich.eu/2013/04/model-driven-evaluation-of-user-perceived-service-availability},
	author = {Dittrich, Andreas and Rezende, Rafael},
	editor = {Vieira, Marco and Cunha, Jo{\~a}o Carlos}
}
@conference {18090,
	title = {Run-time Optimization of a Dynamically Reconfigurable Embedded System Through Performance Prediction},
	booktitle = {23rd International Conference on Field Programmable Logic and Applications (FPL)},
	year = {2013},
	month = {09/2013},
	publisher = {IEEE},
	organization = {IEEE},
	address = {Porto, Portugal},
	doi = {10.1109/FPL.2013.6645523},
	author = {Mariani, Giovanni and Sima, Vlad-Mihai and Palermo, Gianluca and Zaccaria, Vittorio and Marchiori, Giacomo and Silvano, Cristina and Bertels, Koen}
}
@conference {17772,
	title = {A Security-enhanced Design Methodology For Embedded Systems},
	booktitle = { ICETE SECRYPT 2013},
	year = {2013},
	month = {07/2013},
	publisher = {ICETE},
	organization = {ICETE},
	address = {Reykjavik, Iceland},
	keywords = {design methodology, design space exploration, embedded systems, metric, security, security metric},
	author = {Ferrante, Alberto and Milosevic, Jelena and Janjusevic, Marija}
}
@inbook {17996,
	title = {Self-Organizing Real-Time Services in Mobile Ad Hoc Networks},
	booktitle = {Self-Organization in Embedded Real-Time Systems},
	year = {2013},
	pages = {55-74},
	publisher = {Springer New York},
	organization = {Springer New York},
	isbn = {978-1-4614-1968-6},
	doi = {10.1007/978-1-4614-1969-3_3},
	url = {http://dx.doi.org/10.1007/978-1-4614-1969-3_3},
	author = {Kakuda, Yoshiaki and Ohta, Tomoyuki and Malek, Miroslaw},
	editor = {Higuera-Toledano, Teresa and Brinkschulte, Uwe and Rettberg, Achim}
}
@conference {18070,
	title = {Single-Photon Image Sensors},
	booktitle = {Special Session, 50th Design Automation Conference (DAC)},
	year = {2013},
	month = {June},
	address = {Austin, Texas, USA},
	author = {Charbon, Edoardo and Regazzoni, Francesco}
}
@conference {18066,
	title = {Sleuth: Automated Verification of Software Power Analysis Countermeasures},
	booktitle = {Workshop on Cryptographic Hardware and Embedded Systems (CHES)},
	year = {2013},
	month = {August},
	address = {Santa Barbara, California, USA},
	author = {Bayrak, Ali Galip and Regazzoni, Francesco and Novo Bruna, David and Ienne, Paolo}
}
@conference {18039,
	title = {Smart Building Integration in Smart Grids},
	booktitle = {The 44th Heating Ventilation Air Condition and Refrigeration Congress and Exhibition - KGH 2013},
	year = {2013},
	abstract = {Modern power distribution systems gradually evolve into Smart Grids. Intelligence is getting inserted in all segments of the grid, monitoring and controlling entire power flow from generation and distribution down to consumption of home appliances. On the other hand renewable generation systems are getting widely deployed in public and residential buildings turning them into prosumers. Such scenario requires novel solutions for smart coupling of generation and consumption. Different kinds of prosumers clustering have been proposed by scientific community as a response. In the present work we propose an ICT structure capable of tackling this challenge. The conceptual solution represents an architecture which enables seamless integration of Smart Buildings into Smart Grids.},
	keywords = {Clustering, smart grid, smart home, System Level Model},
	author = {Lukovi{\'c}, Slobodan and {\v C}ongradac, Velimir and Kuli{\'c}, Filip}
}
@conference {18067,
	title = {Stealthy Dopant-Level Hardware Trojans},
	booktitle = {Workshop on Cryptographic Hardware and Embedded Systems (CHES)},
	year = {2013},
	month = {August},
	address = {Santa Barbara, California, USA},
	author = {Becker, Georg and Regazzoni, Francesco and Paar, Christof and Burleson, Wayne}
}
@conference {18054,
	title = {STRATOS: open System for TRAcTOrs{\textquoteright} autonomous OperationS},
	booktitle = {EFITA Internation Conference on Sustainable Agriculture through ICT Innovation },
	year = {2013},
	month = {06/2013},
	publisher = {European Federation for Information Technology in Agriculture, Food and the Environment},
	organization = {European Federation for Information Technology in Agriculture, Food and the Environment},
	address = {Torino, Italy},
	abstract = {This paper describes the objectives and final results of the STRATOS project (System for TRAcTOrs{\textquoteright} autonomous OperationS), within the framework of ICT-AGRI ERA-NET (Coordination of European Research within ICT and Robotics in Agriculture and related Environmental Issues). The main objective of the STRATOS project was the development of an open ICT hardware-software infrastructure enabling the acquisition of geo-referenced information on soil and terrain parameters. In more detail, STRATOS project target was to develop and demonstrate new functions enabled by ISOBUS technology (ISO 11783) that support a substantial improvement of the quality of the farming jobs. In particular the idea is to develop a technology based on ISOBUS compliant, wireless self-powered sensor network for the real time measurement of soil and harvester conditions. In this way, Task Controller (an ICT component defined by ISOBUS specification which supervises actively the farming job performed by the tractor) can optimize the whole tractor and implement operational modes to improve the farming job quality and safety of the overall systems. The project lasted from 1st April, 2011 to31st March, 2013, and this paper reports about the project achievements.},
	keywords = {agriculture, ICT, model-driven approach, precision farming, Safety},
	author = {Fantuzzi, Cesare and Gutman, Per-Olof and Kaitovi{\'c}, Igor and Larcher, Luca and Marzani, Stefano and Ruggeri, Massimiliano and Zagurskis, Valerijs}
}
@article {18050,
	title = {A system-level approach to adaptivity and fault-tolerance in NoC-based MPSoCs: The MADNESS project.},
	journal = {Microprocessors and Microsystems - Embedded Hardware Design},
	volume = {37},
	issue = {6-7},
	year = {2013},
	pages = {515{\textendash}529},
	doi = {10.1016/j.micpro.2013.07.007},
	author = {Derin, Onur and Cannella, Emanuele and Tuveri, Giuseppe and Meloni, Paolo and Stefanov, Todor and Fiorin, Leandro and Raffo, Luigi and Sami, Mariagiovanna}
}
@inbook {18089,
	title = {Systems Engineering for Assessment of Virtual Power System Implementations},
	booktitle = {Artificial Intelligence Applications and Innovations},
	series = {9th IFIP WG 12.5 International Conference, AIAI 2013, Paphos, Cyprus, September 30 {\textendash} October 2, 2013, Proceedings},
	volume = {412},
	year = {2013},
	pages = {667-676},
	publisher = {Springer Berlin Heidelberg},
	organization = {Springer Berlin Heidelberg},
	abstract = {In this work we present an adoption of systems engineering methodology for design and assessment of a Virtual Power System (VPS). The VPS has been defined as an aggregation of distributed energy resources, consumers and storages which can operate autonomously, and is presented to the power system as a single unit in technical and commercial terms. The complexity of these critical systems is tackled by means of systems engineering. We have applied our approach in scope of a research project AlpEnergy.},
	keywords = {assessment, modeling, SysML, systems engineering, VPS},
	isbn = {978-3-642-41141-0},
	issn = {1868-4238},
	doi = {10.1007/978-3-642-41142-7_67},
	author = {Lukovi{\'c}, Slobodan and Kaitovi{\'c}, Igor}
}
@conference {17846,
	title = {User-Perceived Instantaneous Service Availability Evaluation},
	booktitle = {19th Pacific Rim International Symposium on Dependable Computing (PRDC)},
	year = {2013},
	month = {12/2013},
	publisher = {IEEE Computer Society},
	organization = {IEEE Computer Society},
	address = {Vancouver, British Columbia, Canada},
	abstract = {Today{\textquoteright}s businesses rely ever more on dependable service provision deployed on information and communications technology (ICT) infrastructures. Service dependability is highly influenced by the individual infrastructure component properties. Combining these properties for consistent dependability analysis is challenging as every service requester might use a different set of components during service usage, constituting the user-perceived view on a service. This paper presents a methodology to evaluate user-perceived instantaneous service availability. It uses three input models: (1) The ICT infrastructure, with failure rates, repair rates and deployment times of all components, (2) an abstract description of complex hierarchical services, (3) a mapping that contains concrete ICT components for the service pair requester and provider, as well as their existing replicas, and a duration of usage. The methodology then automatically generates an availability model from those parts of the ICT infrastructure needed during provision for the specified pair. To calculate instantaneous availability, the age of the ICT components, the order and time of their usage during service provision are taken into account. The methodology supports generation of different availability models, we demonstrate this by providing reliability block diagrams and fault-trees. We demonstrate the feasibility of the methodology by applying it to parts of the network infrastructure of Universit{\`a} della Svizzera italiana, Switzerland.},
	keywords = {availability, Client-server systems, Distributed computing, fault tolerance, modeling},
	doi = {10.1109/PRDC.2013.49},
	url = {http://andreas-dittrich.eu/2013/08/user-perceived-instantaneous-service-availability-evaluation},
	author = {Rezende, Rafael and Dittrich, Andreas and Malek, Miroslaw}
}
@article {155.CaDeMeTuSt12.VLSI,
	title = {Adaptivity Support for MPSoCs based on Process Migration in Polyhedral Process Networks},
	journal = {VLSI Design},
	volume = {2012},
	number = {Article ID 987209},
	year = {2012},
	note = {Special issue on Application-Driven Design of Processor, Memory, and Communication Architectures for MPSoCs},
	month = {February},
	pages = {15 pages},
	publisher = {Hindawi},
	abstract = {System adaptivity is becoming an important feature of modern embedded multiprocessor systems. To achieve the goal of system adaptivity when executing Polyhedral Process Networks (PPNs) on a generic tiled Network-on-Chip (NoC) MPSoC platform, we propose an approach to enable the run-time migration of processes among the available platform resources. In our approach, process migration is allowed by a middleware layer which comprises two main components. The first component concerns the inter-tile data communication between processes. We develop and evaluate a number of different communication approaches which implement the semantics of the PPN model of computation on a generic NoC platform. The presented communication approaches do not depend on the mapping of processes, and have been implemented on a Network-on-Chip multiprocessor platform prototyped on an FPGA. Their comparison in terms of the introduced overhead is presented in two case studies with different communication characteristics. The second middleware component allows the actual run-time migration of PPN processes. To this end, we propose and evaluate a process migration mechanism which leverages the PPN model of computation to guarantee a predictable and efficient migration procedure. The efficiency and applicability of the proposed migration mechanism is shown in a real-life case study.},
	keywords = {middleware, network-on-chip (NoC), polyhedral process networks (PPN), process migration, system adaptivity},
	author = {Cannella, Emanuele and Derin, Onur and Meloni, Paolo and Tuveri, Giuseppe and Stefanov, Todor}
}
@conference {18075,
	title = {Compact Implementation and Performance Evaluation of Block Ciphers in ATtiny Devices},
	booktitle = {Progress in Cryptology - Africacrypt},
	year = {2012},
	month = {July},
	address = {Ifrance, Morocco},
	author = {Eisenbarth, Thomas and Gong, Zheng and Gneysu, Tim and Heyse, Stefan and Indesteege, Sebastiaan and Kerckhof, St{\'e}phanie and Koeune, Francois and Nad, Tomislav and Plos, Thomas and Regazzoni, Francesco and Standaert, Fran{\c c}ois-Xavier and Oldenzeel, Loic Van Oldene}
}
@conference {18073,
	title = {Compact Implementation and Performance Evaluation of Hash Functions in ATtiny Devices},
	booktitle = {11th Smart Card Research and Advanced Application Conference (CARDIS)},
	year = {2012},
	month = {November},
	address = {Graz, Austria},
	author = {Balasch, Josep and Ege, Baris and Eisenbarth, Thomas and Grard, Benot and Gong, Zheng and Gneysu, Tim and Heyse, Stefan and Kerckhof, St{\'e}phanie and Koeune, Francois and Plos, Thomas and Poppelmann, Thomas and Regazzoni, Francesco and Standaert, Fran{\c c}ois-Xavier and Van Assche, Gilles and Van Keer, Ronny and Oldenzeel, Loic Van Oldene and von Maurich, Ingo}
}
@inbook {17695,
	title = {Dynamic Adaptation of Security and QoS in Energy-Harvesting Sensors Nodes},
	booktitle = {e-Business and Telecommunications},
	series = {Communications in Computer and Information Science},
	volume = {222},
	year = {2012},
	pages = {243-258},
	publisher = {Springer},
	organization = {Springer},
	address = { Berlin Heidelberg},
	keywords = {energy harvesting, priority, quality of service (QoS), security, wireless sensor networks},
	isbn = {978-3-642-25205-1},
	doi = {10.1007/978-3-642-25206-8_16},
	url = {http://dx.doi.org/10.1007/978-3-642-25206-8_16},
	author = {Taddeo, Antonio Vincenzo and Mura, Marcello and Ferrante, Alberto},
	editor = {Obaidat, Mohammad and Tsihrintzis, George and Filipe, Joaquim}
}
@conference {157.mariani2012parma,
	title = {Evaluating Run-time Resource Management Policies for Multi-core Embedded Platforms with the EMME Evaluation Framework},
	booktitle = {Workshop on Parallel Programming and Run-time Management Techniques for Many-core Architectures},
	year = {2012},
	month = {February},
	keywords = {EMME, multi-core, run-time resource management, simulation},
	author = {Mariani, Giovanni and Palermo, Gianluca and Zaccaria, Vittorio and Silvano, Cristina}
}
@article {18491,
	title = {A Fast ULV Logic Synthesis Flow in Many-Vt CMOS Processes for Minimum Energy Under Timing Constraints},
	journal = {IEEE Transactions on Circuits and Systems II: Express Briefs  },
	volume = {59-II},
	issue = {12},
	year = {2012},
	month = {02/2012},
	pages = {947-951},
	type = {journal},
	chapter = {947},
	abstract = {Ultra-low-voltage (ULV) logic offers the opportunity to operate at the minimum-energy point (MEP) for applications with low-to-medium speed requirements. Unfortunately, the critical design constraint of achieving a reliable timing closure at the target frequency of the application becomes very complex in the wide design space of ULV including supply (Vdd) and threshold (Vt) voltage selection as well as netlist optimizations from the synthesis. In this paper, we propose a fast synthesis flow to accurately predict the Vdd/Vt MEP under strict timing constraints. Compared to an exhaustive search for the MEP under timing constraints based on numerous library recharacterizations and synthesis steps for all Vdd/Vt pairs, the proposed ULV flow dramatically speeds up the design process. Indeed, it requires a single library recharacterization and only three synthesis steps. Results obtained for several ITC{\textquoteright}99 benchmarks under a wide range of timing constraints from 0.1 to 30 MHz in 65-nm LP/GP CMOS demonstrate that the proposed flow has a less than 10\% energy penalty with respect to the absolute MEP computed with an exhaustive search and energy savings enhanced up to 2.4{\texttimes} compared to a conventional flow with Vdd scaling only},
	keywords = {circuit optimisation, CMOS logic circuits, fast ULV logic synthesis flow, Low power electronics},
	issn = {1549-7747},
	doi = {10.1109/TCSII.2012.2231034},
	url = {http://dx.doi.org/10.1109/TCSII.2012.2231034},
	author = {Bol, David and Hocquet, C{\'e}dric and Regazzoni, Francesco}
}
@inbook {18062,
	title = {Interaction between Fault Attack Countermeasures and the Resistance against Power Analysis Attacks},
	booktitle = {Fault Analysis in Cryptography},
	series = {Information Security and Cryptography Series, Springer},
	year = {2012},
	pages = {257-272},
	publisher = {Springer Berlin Heidelberg},
	organization = {Springer Berlin Heidelberg},
	abstract = {Most of the countermeasures against fault attacks on cryptographic systems that have been developed so far are based on the addition of information redundancy. While these countermeasures have been evaluated with respect to their cost (implementation overhead) and efficiency (fault coverage), little attention has been devoted to the question of the impact their use has on the effectiveness of other types of side-channel attacks, in particular, power analysis attacks. This chapter presents an experimental study whose goal is to determine whether the added information redundancy can increase the vulnerability of a cryptographic circuit to power analysis attacks.},
	isbn = {978-3-642-29656-7},
	doi = {10.1007/978-3-642-29656-7_15},
	author = {Regazzoni, Francesco and Breveglieri, Luca and Ienne, Paolo and Koren, Israel},
	editor = {Joye, Marc and Tunstall, Michael}
}
@conference {18076,
	title = {LEXCOMM: A low energy, secure and flexible communication protocol for a heterogenous body sensor network},
	booktitle = {IEEE-EMBS International Conference on Biomedical and Health Informatics},
	year = {2012},
	month = {January},
	address = {Hong Kong, China},
	author = {Lamichhane, Bishal and Mudda, Steven and Regazzoni, Francesco and Puiatti, Alessandro}
}
@conference {17732,
	title = {Model-driven approach to design ICT infrastructure for precision farming},
	booktitle = {17th IEEE Conference on Emerging Technologies and Factory Automation (ETFA)},
	year = {2012},
	month = {09/2012},
	publisher = {IEEE Industrial Electronics Society},
	organization = {IEEE Industrial Electronics Society},
	address = {Krak{\'o}w, Poland},
	abstract = {Design of complex systems involving a number of experts from various fields necessarily includes modeling at different levels of abstraction. Modeling is particularly important in the initial phase of a joint project when all system requirements and constraints have to be clearly defined and understood by all the partners. Once an unambiguous structural model has been achieved and components interfaces fixed, design of components can be done independently. For the initial phase, a very simplified modeling methodology based on UML that can be easily understood and applied has been proposed. The application of the methodology has been presented through the design of full structural model of the infrastructure for precision farming. Modeled infrastructure is an open ICT hardware-software solution based on ISOBUS specification, that enables partial automation of tractors increasing safety and production efficiency. Model achieved through several steps presents a mutual understanding platform between the partners. Most importantly, a precise model has been achieved without the necessity of in deep study of UML by all the partners.},
	keywords = {agriculture, ICT infrastructure Design, ISOBUS, model-driven approach, precision farming, Safety, Unified Modeling Language},
	isbn = {978-1-4673-4736-5},
	doi = {10.1109/ETFA.2012.6489709},
	author = {Kaitovi{\'c}, Igor and Rezende, Rafael and Murillo, Cristina and Fantuzzi, Cesare}
}
@article {156.MaPaSiZa12.TCAD,
	title = {OSCAR: an Optimization Methodology Exploiting Spatial Correlation in Multi-core Design Space},
	journal = {IEEE Transactions on Computer-Aided Design},
	volume = {21},
	number = {-},
	issue = {5},
	year = {2012},
	month = {05/2012},
	pages = {740-753},
	publisher = {IEEE},
	abstract = {This paper presents OSCAR, an Optimization methodology exploiting Spatial CorrelAtion of multi-coRe design space. The paper builds upon the observation that power consumption and performance metrics of spatially close design configurations (or points) are statistically correlated. We propose to exploit the correlation by using a Response Surface Model (RSM), i.e., a closed-form expression suitable for predicting the quality of non-simulated design points. This model is useful during the design space exploration (DSE) phase to quickly converge to the Pareto set of the multi-objective problem without executing lengthy simulations. We compare the proposed heuristic with state-of-the-art approaches (conventional, RSM-based and structured DOEs). Experimental results show that OSCAR is a faster heuristic with respect to state of the art techniques such as Response-Surface Pareto Iterative Refinement - ReSPIR and Nondominated Sorting Genetic Algorithm - NSGA-II. Reported results also show that OSCAR can significantly improve structured DOE approaches by slightly increasing the number of experiments.},
	keywords = {chip multi processor, correlation based design, design space exploration, multi-core, multi-objective optimization, OSCAR},
	author = {Mariani, Giovanni and Palermo, Gianluca and Silvano, Cristina and Zaccaria, Vittorio}
}
@conference {17994,
	title = {Securability: the Key Challenge for Autonomic and Trusted Computing},
	booktitle = {IEEE International Conference on Ubiquitous Intelligence Computing / International Conference on Autonomic Trusted Computing (UIC/ATC)},
	year = {2012},
	month = {03/2012},
	edition = {9},
	author = {Malek, Miroslaw}
}
@conference {17577,
	title = {Security Enhanced Linux on Embedded Systems: a Hardware-accelerated Implementation},
	booktitle = {17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012},
	year = {2012},
	month = {02/2012},
	address = {Sydney, Australia},
	abstract = {Security Enhanced Linux implements fine-grained mandatory access control. Despite its usefulness, the overhead of implementing it on embedded devices is prohibitive. Therefore, in the past it has been proposed to accelerate SELinux by means of dedicated hardware; in this work we demonstrate the feasibility of such an approach by implementing a hardware accelerator for SELinux on a FPGA-based platform. Our implementation obtains a huge reduction in the performance overhead and energy consumption of SELinux, yet employing a limited chip area.},
	keywords = {authorisation, dedicated hardware, embedded systems, energy consumption, field programmable gate arrays, fine-grained mandatory access control, FPGA-based platform, hardware accelerator, hardware-accelerated implementation, linux, performance overhead reduction, security enhanced Linux},
	doi = {10.1109/ASPDAC.2012.6164960},
	author = {Fiorin, Leandro and Ferrante, Alberto and Padarnitsas, Konstantinos and Regazzoni, Francesco}
}
@conference {18074,
	title = {Simulation-Time Security Margin Assessment against power-based Side Channel Attacks},
	booktitle = {7th Workshop on Embedded Systems Security (WESS)},
	year = {2012},
	month = {October},
	address = {Tampere, Finland},
	author = {Barenghi, Alessandro and Pelosi, Gerardo and Regazzoni, Francesco}
}
@conference {18140,
	title = {STRATOS: Open System For Tractors{\textquoteright} Autonomous Operations},
	booktitle = {5th International Conference on Automation Technology for Off-road Equipment (ATOE)},
	year = {2012},
	month = {07/2012},
	pages = {162-187},
	publisher = {International Commission of Agricultural and Biosystems Engineering (CIGR)},
	organization = {International Commission of Agricultural and Biosystems Engineering (CIGR)},
	address = {Valencia, Spain},
	abstract = {This paper describes the objectives and preliminary results of the STRATOS project (System for TRAcTOrs{\textquoteright} autonomous OperationS), within the framework of ICT-AGRI ERA-NET (Coordination of European Research within ICT and Robotics in Agriculture and related Environmental Issues). The main objective of the STRATOS project is to develop an open ICT hardware-software infrastructure enabling the partial automation of tractors and at the same time enhancing their operational safety and production efficiency, with the positive effects of reduced accident risk and environmental impact. In more detail, STRATOS project target is to develop and demonstrate new functions enabled by ISOBUS technology (ISO 11783) that support a substantial improvement of the quality of the farming jobs. In particular the idea is to develop a technology based on ISOBUS compliant, wireless self-powered sensor network for the real time measurement of soil and harvester conditions. In this way, Task Controller (an ICT component defined by ISOBUS specification which supervises actively the farming job performed by the tractor) can optimize the whole tractor and implement operational modes to improve the farming job quality and safety of the overall systems. The project started on 1 st April, 2011, and will end the 31 st March, 2013, This paper reports about some achievement gained so far.},
	keywords = {agriculture, ICT infrastructure Design, model-driven approach, precision farming, Safety},
	isbn = {84-615-9654-4},
	author = {Fantuzzi, Cesare and Gutman, Per-Olof and Kaitovi{\'c}, Igor and Larcher, Luca and Marzani, Stefano and Ruggeri, Massimiliano and Zagurskis, Valerijs}
}
@conference {17737,
	title = {System Adaptivity and Fault-tolerance in NoC-based MPSoCs: the MADNESS Project Approach},
	booktitle = {Proceedings of the 15th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD{\textquoteright}12)},
	year = {2012},
	month = {September 5-8},
	address = {Izmir, Turkey},
	abstract = {Modern embedded systems increasingly require adaptive run-time management. The system may adapt the mapping of the applications in order to accommodate the current workload conditions, to balance load for efficient resource utilization, to meet quality of service agreements, to avoid thermal hot-spots and to reduce power consumption. As the possibility of experiencing run-time faults becomes increasingly relevant with deep-sub-micron technology nodes, in the scope of the MADNESS project, we focus particularly on the problem of graceful degradation by dynamic remapping in presence of run-time faults. In this paper, we summarize the major results achieved in the MADNESS project until now regarding the system adaptivity and fault tolerant processing. We report the first results of the integration between platform level and middleware level support for adaptivity and fault tolerance. A case study demonstrates the survival ability of the platform via a low-overhead process migration mechanism and a near-optimal online remapping heuristic.},
	keywords = {fault tolerance, kahn process networks (KPN), middleware, network-on-chip (NoC), process migration, system adaptivity},
	doi = {http://dx.doi.org/10.1109/DSD.2012.122},
	author = {Meloni, Paolo and Tuveri, Giuseppe and Raffo, Luigi and Cannella, Emanuele and Stefanov, Todor and Derin, Onur and Fiorin, Leandro and Sami, Mariagiovanna}
}
@conference {17766,
	title = {System Level Approach to Denial-of-Service Detection in MPSoCs},
	booktitle = {Proceedings of the 7th Workshop on Embedded Systems Security (WESS{\textquoteright}2012), A Workshop of the Embedded Systems Week (ESWEEK{\textquoteright}12)},
	year = {2012},
	month = {10/2012},
	abstract = {Multiprocessor Systems-on-Chip (MPSoCs) are pervading our lives, acquiring ever increasing relevance in a large number of applications, including even safety-critical ones. MPSoCs, are becoming increasingly complex and heterogeneous; the increased complexity as well as the networking approach in turn make security aspects more critical. In this work we propose and implement a hierarchical multi-agent approach providing solutions to secure Network-on-Chip based MPSoCs at different levels of design from nondeterministic attacks such as Denial-of-Service (DoS). We develop a flexible, scalable and modular structure integrating protection of different elements in the MPSoC (e.g. memory, processors) that can be tuned to particular attack scenarios - in this case a DoS attack. This work aims at providing a comprehensive, system-level protection strategy: this constitutes its main methodological contribution. We prove feasibility of the concepts via prototype realization in FPGA technology.},
	author = {Lukovi{\'c}, Slobodan and Srivastava, Anubhav}
}
@article {17738,
	title = {Towards Self-adaptive KPN Applications on NoC-based MPSoCs},
	journal = {Advances in Software Engineering},
	volume = {2012},
	year = {2012},
	month = {September},
	pages = {16 pages},
	abstract = {Self-adaptivity is the ability of a system to adapt itself dynamically to internal and external changes. Such a capability helps systems to meet the performance and quality goals, while judiciously using available resources. In this paper, we propose a framework to implement application level self-adaptation capabilities in KPN applications running on NoC-based MPSoCs. The monitor-controller-adapter mechanism is used at the application level. The monitor measures various parameters to check whether the system meets the assigned goals. The controller takes decisions to steer the system towards the goal, which are applied by the adapters. The proposed framework requires minimal modifications to the application code and offers ease of integration. It incorporates a generic adaptation controller based on fuzzy logic. We present the MJPEG encoder as a case study to demonstrate the effectiveness of the approach. Our results show that even if the parameters of the fuzzy controller are not tuned optimally, the adaptation convergence is achieved within reasonable time and error limits. Moreover, the incurred steady-state overhead due to the framework is 4\% for average frame-rate, 3.5\% for average bit-rate, and 0.5\% for additional control data introduced in the network.},
	keywords = {kahn process networks (KPN), network-on-chip (NoC), quality of service (QoS), self-adaptivity},
	doi = {http://dx.doi.org/10.1155/2012/172674},
	author = {Derin, Onur and Ramankutty, Prasanth Kuncheerat and Meloni, Paolo and Cannella, Emanuele}
}
@conference {158.mariani2012date,
	title = {Using Multi-objective Design Space Exploration to Enable Run-time Resource Management for Reconfigurable Architectures},
	booktitle = {Proc. Design, Automation Test in Europe Conf. Exhibition (DATE)},
	year = {2012},
	month = {March},
	author = {Mariani, Giovanni and Sima, Vlad-Mihai and Palermo, Gianluca and Zaccaria, Vittorio and Silvano, Cristina and Bertels, Koen}
}
@conference {159.LuVuKaEr12.MELECON,
	title = {Virtual Metering for Virtual PHEV Aggregation},
	booktitle = {Proceedings of the 16th IEEE Mediterranean Electrotechnical Conference (MELECON2012)},
	year = {2012},
	month = {March 25-28},
	address = {Yasmine Hammamet, Tunisia},
	abstract = {Technically sustainable solutions for integration of (PH)EVs in Smart Grid emerge as an important concern. We discuss the need for introduction of Virtual Aggregations supported by implementation of Virtual Meters in power system structures. We advocate our proposal with an evaluation of scenarios based on realistic data. The structure and functionalities of the Virtual Aggregator, as well as proposed enhancements on the Smart Grid side, are presented.},
	author = {Lukovi{\'c}, Slobodan and Vukmirovi{\'c}, Srdjan and Kaitovi{\'c}, Igor and Erdeljan, Aleksandar}
}
@conference {150.KaLu11,
	title = {Adoption of Model-Driven methodology to aggregations design in Power Grid},
	booktitle = {INDIN {\textquoteright}11: Proceedings of the 9th IEEE International Conference on Industrial Informatics},
	year = {2011},
	month = {July 26-29},
	pages = {1{\textendash}6},
	address = {Caparica, Lisbon, Portugal},
	abstract = {Economical and environmental concerns push toward novel solutions for sustainable, renewable and intelligent energy power grid, the Smart Grid. Very often, this includes aggregation of renewable resources and intelligent loads such as electrical vehicles. Such complex system involve a number of various stakeholders coming from different areas of expertise. Even so, on-going projects do not apply unique formal language. In order to better correlate the projects, model-driven methodology and SysML are proposed for system design.},
	keywords = {EVs agregation, model-driven design, smart grid, SysML},
	doi = {http://dx.doi.org/10.1109/INDIN.2011.6034936},
	author = {Kaitovi{\'c}, Igor and Lukovi{\'c}, Slobodan}
}
@conference {18493,
	title = {ADSC: Application-Driven Storage Control for Energy Efficiency},
	booktitle = {Information and Communication on Technology for the Fight against Global Warming - First International Conference ICT-GLOW},
	series = {Lecture Notes in Computer Science },
	volume = {6868},
	year = {2011},
	month = {08/2011},
	pages = {165-179},
	publisher = {Springer},
	organization = {Springer},
	address = {Toulouse, France},
	abstract = {While performance and quality of service are the main criteria for application data management on storage units, energy efficiency is increasingly being stated as an additional criterion for evaluation. Due to the increasing energy consumption of storage subsystems, improving their energy efficiency is an important issue. In this paper we present a novel approach to storage management whereby both mid-level (file placement) and low level (disk mode) aspects are controlled, in a tiered storage architecture. The proposed mechanism is based on policies, and it is implemented via fuzzy logic rules, in contrast to attempting to build a model of the storage subsystem. The inputs to the storage management system are high level (application), mid level (file system) and low level (disk access patterns) information. The effectiveness of our approach has been validated by means of a case study using a TPC-C benchmark modified to access file level data. Results from this simulation are presented.},
	isbn = {978-3-642-23446-0},
	doi = {10.1007/978-3-642-23447-7_15},
	url = {http://dx.doi.org/10.1007/978-3-642-23447-7_15},
	author = {Cappiello, Cinzia and Hinostroza, Alicia and Pernici, Barbara and Sami, Mariagiovanna and Henis, Ealan and Kat, Ronen I. and Meth, Kalman Z. and Mura, Marcello}
}
@inbook {141.aetherinbook.2011,
	title = {AETHER: Self-Adaptive Networked Entities: Autonomous Computing Elements for Future Pervasive Applications and Technologies},
	booktitle = {Reconfigurable Computing: From FPGAs to Hardware/Software Codesign},
	year = {2011},
	pages = {149{\textendash}184},
	publisher = {Springer},
	organization = {Springer},
	address = {New York, USA},
	abstract = {The AETHER project has laid the foundation of a complete new framework for designing and programming computing resources that live in changing environments and need to re-configure their objectives in a dynamic way. This chapter contributes to a strategic research agenda in the field of self-adaptive computing systems. It brings inputs to the reconfigurable hardware community and proposes directions to go for reconfigurable hardware and research on self-adaptive computing; it tries to identify some of the most promising future technologies for reconfiguration, while pointing out the main foreseen Challenges for reconfigurable hardware. This chapter presents the main solutions the AETHER project proposed for some of the major concerns in trying to engineer a self-adaptive computing system. The text exposes the AETHER vision of self-adaptation and its requirements. It describes and discusses the proposed solutions for tackling self-adaptivity at the various levels of abstractions. It exposes how the developed technologies could be put together in a real methodology and how self-adaptation could then be used in potential applications. Finally and based on lessons learned from AETHER, we discuss open issues and research opportunities and put those in perspective along other investigations and roadmaps.},
	isbn = {978-1-4614-0061-5},
	author = {Gamrat, Christian and Philippe, Jean-Marc and Jesshope, Chris and Shafarenko, Alex and Bisdounis, Labros and Bondi, Umberto and Ferrante, Alberto and Cabestany, Joan and Huebner, Michael and Parsinnen, Juha and Kadlec, Jiri and Danek, Martin and Tain, Benoit and Eisenbach, Susan and Auguin, Michel and Diguet, Jean-Philippe and Lenormand, Eric and Roux, Jean-Luc},
	editor = {Cardoso, Joao Manuel Pai and Huebner, Michael}
}
@conference {149.MaPaSiZa.SASP11,
	title = {ARTE: an Application-specific Run-Time Management Framework for Multi-core Systems},
	booktitle = {Proceedings IEEE SASP{\textquoteright}11 - Symposium on Application Specific Processors},
	year = {2011},
	month = {June},
	address = {San Diego, CA, USA},
	abstract = {Programmable multi-core and many-core platforms increase exponentially the challenge of task mapping and scheduling, provided that enough task-parallelism does exist for each application. This problem worsens when dealing with small ecosystems such as embedded systems-on-chip. In fact, in this case, the assumption of exploiting a traditional operating system is out of context given the memory available to satisfy the run-time footprint of such a configuration. An efficient Run-time Resource Management (RRM) becomes of paramount importance to dispatch tasks to the cores by taking into account the task-parallelization options that each application provides. State-of-the-art approaches to RRM try to allocate re- sources to maximize the instantaneous throughput while meeting a power budget constraint. In this paper, we will show that queuing theory can be an alternative yet effective way of solving resource allocation by presenting ARTE, an Application-specific Run-Time managEment framework. The framework exploits few assumptions about the target many-core computing fabric such as the availability of performance (throughput) information about the platform applications. We will show that this information can be combined, at run-time, with queuing models to enhance the response time of the applications by pounding the actual effect on the system power consumption better than previous approaches. Experimental results show that, compared to reference state-of-the-art RRM techniques, ARTE is able to efficiently improve system performance by pro-actively reducing the response time while meeting the same power consumption requirements. Besides, we will show that the run-time overhead of ARTE does not signicantly impact neither the system performance nor the on-chip-memory occupation.},
	doi = {http://dx.doi.org/10.1109/SASP.2011.5941085},
	author = {Mariani, Giovanni and Palermo, Gianluca and Silvano, Cristina and Zaccaria, Vittorio}
}
@conference {152.KrLeAhPoLi11.SiPS,
	title = {Beamforming for interference mitigation and its implementation on an SDR baseband processor},
	booktitle = {SiPS{\textquoteright}11: Proceedings of the IEEE Workshop on Signal Processing Systems},
	year = {2011},
	month = {October 4-7},
	pages = {1{\textendash}6},
	address = {Beirut, Lebanon},
	abstract = {We present the first implementation of a distributed beamforming algorithm for interference mitigation on an SDR baseband processor. Co-channel interference (CCI) is becoming a major source of impairments in wireless communications and distributed beamforming is a promising technique to mitigate its negative impact. However, such schemes are challenging to implement in practical scenarios due to their complexity and synchronization requirements. In this paper, we report on implementation of a suboptimal, yet efficient, beamforming scheme for CCI mitigation and present the complexity modeling and algorithm transformations for achieving numerically stability. We also present the fixed-point quantization and the proper mapping on a parallel programmable baseband architecture aimed for software-defined radio (SDR). We optimize this algorithm for a coarse grained reconfigurable array (CGRA) processor and evaluate it in the context of the LTE standard.},
	keywords = {beamforming, coarse grained reconfigurable array (CGRA), fixed-point arithmetic, long term evolution (LTE), software defined radio (SDR)},
	doi = {http://dx.doi.org/10.1109/SiPS.2011.6088973},
	author = {Krdu, Adrian and Lebrun, Yann and Ahmad, Ubaid and Pollin, Sofie and Li, Min}
}
@conference {151.FiMiSa11,
	title = {Design of Fault Tolerant Network Interfaces for NoCs},
	booktitle = {Proceedings of 14th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD{\textquoteright}11)},
	year = {2011},
	month = {September},
	address = {Oulu, Finland},
	keywords = {fault tolerance, network interface, network-on-chip (NoC), system-on-chip (SoC)},
	doi = {http://dx.doi.org/10.1109/DSD.2011.54},
	author = {Fiorin, Leandro and Micconi, Laura and Sami, Mariagiovanna}
}
@inbook {18092,
	title = {Design Space Exploration for Run-Time Management of a Reconfigurable System for Video Streaming},
	booktitle = {Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach},
	year = {2011},
	pages = {189-204},
	publisher = {Springer},
	organization = {Springer},
	edition = {1},
	isbn = {978-1-4419-8836-2},
	author = {Mariani, Giovanni and Avasare, Prabhat and Ykman-Couvreur, Chantal and Vanmeerbeeck, Geert and Palermo, Gianluca and Silvano, Cristina and Zaccaria, Vittorio},
	editor = {Silvano, Cristina and Fornaciari, William and Villar, Eugenio}
}
@inbook {138.MaAvYkVaPaSiZa.2011,
	title = {Design Space Exploration of a Reconfigurable System for Supporting Video Streaming Run-time Management},
	booktitle = {Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach},
	year = {2011},
	publisher = {Springer},
	organization = {Springer},
	address = {New York, USA},
	abstract = {This paper reports a case study of Design Space Exploration for supporting Run-time Resource Management (RRM). In particular the management of system resources for an MPSoC dedicated to multiple MPEG4 encoding is addressed in the context of an Automotive Cognitive Safety System (ACSS). The runtime management problem is defined as the minimization of the platform power consumption under resource and Quality of Service (QoS) constraints. The paper provides an insight of both, design-time and run-time aspects of the problem. During the prelimiary design-time Design Space Exploration (DSE) phase, the best configurations of run-time tunable parameters are statically identified for providing the best trade-offs in terms of run-time costs and application QoS. To speed up the optimization process without reducing the quality of final results, a multi-simulator framework is used for modeling platform performance. At run-time, the RRM exploits the design-time DSE results for deciding an operating configuration to be loaded for each MPEG4 encoder. This operation is carried out dynamically, by following the QoS requirements of the specific use-case.},
	author = {Mariani, Giovanni and Avasare, Prabhat and Ykman-Couvreur, Chantal and Vanmeerbeeck, Geert and Palermo, Gianluca and Silvano, Cristina and Zaccaria, Vittorio}
}
@inbook {140.KaTuPaSiZaMaBoDo.2011,
	title = {Design Space Exploration of Parallel Architectures},
	booktitle = {Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach},
	year = {2011},
	publisher = {Springer},
	organization = {Springer},
	address = {New York, USA},
	abstract = {This chapter will present two significant applications of the MULTICUBE design space exploration framework. The first part will present the design space exploration of a low power processor developed by STMicroelectronics by using the modeFRONTIER tool to demonstrate the benefits DSE not only in terms of objective quality, but also in terms of impact on the design process within the corporate environment. The second part will describe the application of RSM models developed within MULTICUBE to a tiled, multiple-instruction, many-core architecture developed by ICT China. Overall, the results have showed that different models can present a trade-off of accuracy versus computational effort. In fact, throughout the evaluation, we observed that high accuracy models require high computational time (for both model construction time and prediction time); vice-versa low model construction and prediction time has led to low accuracy.},
	author = {Kavka, Carlos and Turco, Alessandro and Palermo, Gianluca and Silvano, Cristina and Zaccaria, Vittorio and Mariani, Giovanni and Bocchio, Sara and Dongrui, Fan}
}
@inbook {144.AvYkVaMaPaSiZa.2011,
	title = {Design Space Exploration Supporting Run-time Resource Management},
	booktitle = {Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach},
	year = {2011},
	publisher = {Springer},
	organization = {Springer},
	address = {New York, USA},
	abstract = {Running multiple applications optimally in terms of Quality of Service (e.g., performance and power consumption) on embedded multi-core platforms is a huge challenge.Moreover, current applications exhibit unpredictable changes of the environment and workload conditions which makes the task of running them optimally even more difficult. This dynamic trend in application runs will grow even more in future applications. This paper presents an automated tool flow which tackles this challenge by a two-step approach: first at design-time, a Design Space Exploration (DSE) tool is coupled with a platform simulator(s) to get optimum operating points for the set of target applications. Secondly, at run-time, a lightweight Run-time Resource Manager (RRM) leverages the design-time DSE results for deciding an operating configuration to be loaded at run-time for each application. This decision is performed dynamically, by taking into consideration available platform resources and the QoS requirements of the specific use-case. To keep RRM execution and resource overhead at minimum, a very fast optimisation heuristic is integrated. Application of this tool-flow on a real-life multimedia use case (described in Chapter 9 of the book of this paper) will demonstrate a significant speedup in optimisation process while maintaining desired Quality of Service.},
	author = {Avasare, Prabhat and Ykman-Couvreur, Chantal and Vanmeerbeeck, Geert and Mariani, Giovanni and Palermo, Gianluca and Silvano, Cristina and Zaccaria, Vittorio}
}
@conference {154.BaChDe11.ISWCS,
	title = {Energy-Throughput Simulation Approach for Heterogeneous LTE scenarios},
	booktitle = {ISWCS{\textquoteright}11: Proceedings of The Eighth International Symposium on Wireless Communication Systems},
	year = {2011},
	month = {November 6-9},
	pages = {1{\textendash}5},
	address = {Aachen, Germany},
	abstract = {In order to increase overall LTE system performance femtocells have been proposed as a user-based solution promising to give much better service to the user specially indoor. Their deployment should improve the total system capacity noticeably and decrease drastically the power consumption. On the other hand these small indoor cells make the network planning strategies much more complex given the uncertainty of their position and their load; femtocells are after all managed by the users. Goal of this work is to provide a simulation approach to determine the effects of heterogeneous cell deployment on the performance of an LTE network. The simulation framework allows to realistically compare the power consumption and throughput of the overall system. The key components are the combination of indoor and outdoor propagation modeling, and the diversification of femto, micro and macro-cell energy consumption models. The model further contains complex city-like building structures, multiple communication layers (eNodeBs and femtocells) distributed over a three-dimensional map and numerous users moving across different areas while adapting their service requirements. The simulation approach results in relatively computationally inexpensive simulations and allows to model the expected throughput and energy consumption for various heterogeneous LTE scenarios.},
	keywords = {long term evolution (LTE)},
	doi = {http://dx.doi.org/10.1109/ISWCS.2011.6125377},
	author = {Baddour, Rami and Chiumento, Alessandro and Desset, Claude}
}
@conference {18079,
	title = {Exploring the Feasibility of Low Cost Fault Injection Attacks on Sub-Threshold Devices through an Example of a 65nm AES Implementation},
	booktitle = {7th Workshop on RFID Security and Privacy (RFIDSec)},
	year = {2011},
	month = {June},
	address = {Amherst, Massachussets, USA},
	author = {Barenghi, Alessandro and Hocquet, C{\'e}dric and Bol, David and Standaert, Fran{\c c}ois-Xavier and Regazzoni, Francesco and Koren, Israel}
}
@conference {18080,
	title = {A First Step Towards Automatic Application of Power Analysis Countermeasures},
	booktitle = {48th Design Automation Conference (DAC)},
	year = {2011},
	month = {June},
	address = {San Diego, Califorina},
	author = {Bayrak, Ali Galip and Regazzoni, Francesco and Brisk, Philip and Standaert, Fran{\c c}ois-Xavier and Ienne, Paolo}
}
@conference {18086,
	title = {FPGA Implementations of the AES Masked Against Power Analysis Attacks},
	booktitle = {2nd International Workshop on Constructive Side-Channel Analysis and Secure Design (COSADE)},
	year = {2011},
	month = {February},
	address = {Darmstadt, Germany},
	author = {Regazzoni, Francesco and Yi, Wang and Standaert, Fran{\c c}ois-Xavier}
}
@conference {17696,
	title = {A Framework for Security and Workload Gradual Adaptation},
	booktitle = {SECRYPT},
	year = {2011},
	month = {07/2011},
	publisher = {ICETE},
	organization = {ICETE},
	address = {Seville, Spain},
	author = {Taddeo, Antonio Vincenzo and Morales, Luis Germ{\'a}n Garcia and Ferrante, Alberto}
}
@conference {18077,
	title = {Fresh Re-Keying II: Securing Multiple Parties against Side-Channel and Fault Attacks},
	booktitle = {10th Smart Card Research and Advanced Application Conference (CARDIS)},
	year = {2011},
	month = {September},
	address = {Leuven, Belgium},
	author = {Medwed, Marcel and Petit, Christophe and Regazzoni, Francesco and Renauld, Mathieu and Standaert, Fran{\c c}ois-Xavier}
}
@article {18063,
	title = {Harvesting the potential of nano-CMOS for lightweight cryptography: An ultra-low-voltage 65 nm AES coprocessor for passive RFID tags},
	journal = {Springer Journal of Cryptographic Engineering},
	volume = {1},
	issue = {1},
	year = {2011},
	author = {Hocquet, C{\'e}dric and Kamel, Dina and Regazzoni, Francesco and Legat, Jean-Didier and Flandre, Denis and Bol, David and Standaert, Fran{\c c}ois-Xavier}
}
@article {145.YkAvMaZaPaSi11,
	title = {Linking run-time resource management of embedded multi-core platforms with automated design-time exploration},
	journal = {IET Computers and Digital Techniques},
	volume = {5},
	number = {-},
	year = {2011},
	pages = {123{\textendash}135},
	abstract = {Nowadays, owing to unpredictable changes of the environment and workload variation, optimally running multiple applications in terms of quality, performance and power consumption on embedded multi-core platforms is a huge challenge. A lightweight run-time manager, linked with an automated design-time exploration and incorporated in the host processor of the platform, is required to dynamically and efficiently configure the applications according to the available platform resources (e.g. processing elements, memories, communication bandwidth), for minimising the cost (e.g. power consumption), while satisfying the constraints (e.g. deadlines). This study presents a flow linking a design-time design space explorer, coupled with platform simulators at two abstraction levels, with a fast and lightweight priority-based heuristic integrated in the run-time manager to select near-optimal application configurations. To illustrate its feasibility and the very low complexity of the run-time selection, the proposed flow is used to manage the processors and clock frequencies of a multiple-stream MPEG4 encoder chip dedicated to automotive cognitive safety applications.},
	doi = {http://dx.doi.org/10.1049/iet-cdt.2010.0030},
	author = {Ykman-Couvreur, Chantal and Avasare, Prabhat and Mariani, Giovanni and Zaccaria, Vittorio and Palermo, Gianluca and Silvano, Cristina}
}
@conference {18078,
	title = {Low Cost FPGA Implementations of the SHA-3 Finalists},
	booktitle = {10th Smart Card Research and Advanced Application Conference (CARDIS)},
	year = {2011},
	month = {September},
	address = {Leuven, Belgium},
	author = {Kerckhof, St{\'e}phanie and Durvaux, Fran{\c c}ois and Veyrat-Charvillon, Nicolas and Regazzoni, Francesco and de Dormale, Guerric Meurice and Standaert, Fran{\c c}ois-Xavier}
}
@article {146.DeDiFi11.IJRC,
	title = {A Middleware Approach to Achieving Fault-tolerance of Kahn Process Networks on Networks-on-Chips},
	journal = {International Journal of Reconfigurable Computing},
	volume = {2011},
	number = {Article ID 295385},
	year = {2011},
	note = {Selected Papers from the International Workshop on Reconfigurable Communication-centric Systems on Chips (ReCoSoC{\textquoteright} 2010)},
	month = {February},
	pages = {14 pages},
	publisher = {Hindawi},
	abstract = {Kahn process networks (KPN) is a distributed model of computation used for describing systems where streams of data are transformed by processes executing in sequence or parallel. Autonomous processes communicate through unbounded FIFO channels in absence of a global scheduler. In this work, we propose a task-aware middleware concept that allows adaptivity in KPN implemented over a Network-on-Chip (NoC). We also list our ideas on the development of a simulation platform as an initial step towards creating fault-tolerance strategies for KPNs applications running on NoCs. In doing that, we extend our SACRE (Self-adaptive Component Run-time Environment) framework by integrating it with an open source NoC simulator, Noxim. We evaluate the overhead that the middleware brings to the the total execution time and to the total amount of data transferred in the NoC. With this work, we also provide a methodology that can help in identifying the requirements and implementing fault tolerance and adaptivity support on real platforms.},
	keywords = {fault tolerance, kahn process networks (KPN), middleware, network-on-chip (NoC), self-adaptivity},
	issn = {1687-7195},
	doi = {doi:10.1155/2011/295385},
	author = {Derin, Onur and Diken, Erkan and Fiorin, Leandro}
}
@conference {153.CaDeSt11.DASIP,
	title = {Middleware Approaches for Adaptivity of Kahn Process Networks on Networks-on-Chip},
	booktitle = {DASIP{\textquoteright}11: Proceedings of the Conference on Design and Architectures for Signal and Image Processing},
	year = {2011},
	month = {November 2-4},
	pages = {1{\textendash}8},
	address = {Tampere, Finland},
	abstract = {We investigate and propose a number of different middleware approaches, namely virtual connector, virtual connector with variable rate, and request-based, which implement the semantics of Kahn Process Networks on Network-on-Chip architectures. All of the presented solutions allow for run-time system adaptivity. We implement the approaches on a Network-on-Chip multiprocessor platform prototyped on an FPGA. Their comparison in terms of the introduced overhead is presented on two case studies with different communication characteristics. We found out that the virtual connector mechanism outperforms other approaches in the communication-intensive application. In the other case study, which has a higher computation/communication ratio, the middleware approaches show similar performance.},
	keywords = {kahn process networks (KPN), middleware, network-on-chip (NoC), self-adaptivity},
	doi = {http://dx.doi.org/10.1109/DASIP.2011.6136862},
	author = {Cannella, Emanuele and Derin, Onur and Stefanov, Todor}
}
@inbook {17734,
	title = {The MULTICUBE Design Flow},
	booktitle = {Multi-objective Design Space Exploration of Multiprocessor SoC Architectures},
	year = {2011},
	pages = {3-17},
	publisher = {Springer New York},
	organization = {Springer New York},
	isbn = {978-1-4419-8836-2},
	doi = {10.1007/978-1-4419-8837-9_1},
	url = {http://dx.doi.org/10.1007/978-1-4419-8837-9_1},
	author = {Silvano, Cristina and Fornaciari, William and Palermo, Gianluca and Zaccaria, Vittorio and Castro, Fabrizio and Martinez, Marcos and Bocchio, Sara and Zafalon, Roberto and Avasare, Prabhat and Vanmeerbeeck, Geert and Ykman-Couvreur, Chantal and Wouters, Maryse and Kavka, Carlos and Onesti, Luka and Turco, Alessandro and Bondi, Umberto and Mariani, Giovanni and Posadas, Hector and Villar, Eugenio and Wu, Chris and Dongrui, Fan and Hao, Zhang},
	editor = {Silvano, Cristina and Fornaciari, William and Villar, Eugenio}
}
@inbook {139.Sietal2.2011,
	title = {MULTICUBE: Multi-Objective Design Space Exploration of Multi-Core Architectures},
	booktitle = {VLSI 2010 Annual Symposium},
	volume = {105},
	year = {2011},
	pages = {47-63},
	publisher = {Springer},
	organization = {Springer},
	address = {Netherlands},
	abstract = {Given the increasing complexity of Chip Multi-Processors (CMPs), a wide range of architecture parameters must be explored at design time to find the best trade-off in terms of multiple competing objectives (such as energy, delay, bandwidth, area, etc.) The design space of the target architectures is huge because it should consider all possible combinations of each hardware parameter (e.g., number of processors, processor issue width, L1 and L2 cache sizes, etc.). In this complex scenario, intuition and past experience of design architects is no more a sufficient condition to converge to an optimal design of the system. Indeed, Automatic Design Space Exploration (DSE) is needed to systematically support the analysis and quantitative comparison of a large amount of design alternatives in terms of multiple competing objectives (by means of Pareto analysis). The main goal of the MULTICUBE project consists of the definition of an automatic Design Space Exploration framework to support the design of next generation many-core architectures.},
	isbn = {978-94-007-1487-8},
	url = {http://dx.doi.org/10.1007/978-94-007-1488-5_4},
	author = {Silvano, Cristina and Fornaciari, William and Palermo, Gianluca and Zaccaria, Vittorio and Castro, Fabrizio and Martinez, Marcos and Bocchio, Sara and Zafalon, Roberto and Avasare, Prabhat and Vanmeerbeeck, Geert and Ykman-Couvreur, Chantal and Wouters, Maryse and Kavka, Carlos and Onesti, Luka and Turco, Alessandro and Bondi, Umberto and Mariani, Giovanni and Posadas, Hector and Villar, Eugenio and Wu, Chris and Dongrui, Fan and Hao, Zhang and Shibin, Tang}
}
@conference {148.DeKaFi11.NOCS,
	title = {Online Task Remapping Strategies for Fault-tolerant Network-on-Chip Multiprocessors},
	booktitle = {NOCS {\textquoteright}11: Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip},
	year = {2011},
	month = {05/2011},
	pages = {1{\textendash}8},
	address = {Pittsburgh, Pennsylvania, USA},
	abstract = {As CMOS technology scales down into the deep submicron domain, the aspects of fault tolerance in complex Networks-on-Chip (NoCs) architectures are assuming an increasing relevance. Task remapping is a software based solution for dealing with permanent failures in processing elements in the NoC. In this work, we formulate the optimal task mapping problem for mesh-based NoC multiprocessors with deterministic routing as an integer linear programming (ILP) problem with the objective of minimizing the communication traffic in the system and the total execution time of the application. We find the optimal mappings at design time for all scenarios where single-faults occur in the processing nodes. We propose heuristics for the online task remapping problem and compare their performances with the optimal solutions.},
	keywords = {adaptivity, fault tolerance, kahn process networks (KPN), mapping, network-on-chip (NoC), self-adaptivity},
	doi = {http://dx.doi.org/10.1145/1999946.1999967},
	author = {Derin, Onur and Kabakci, Deniz and Fiorin, Leandro}
}
@inbook {143.RiKaTuPaSiZaMa.2011,
	title = {Optimization Algorithms for Embedded System Design Space Exploration},
	booktitle = {Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach},
	year = {2011},
	publisher = {Springer},
	organization = {Springer},
	address = {New York, USA},
	abstract = {This paper is dedicated to the optimization algorithms developed in the MULTICUBE project and to their surrounding environment. Two software design space exploration (DSE) tools host the algorithms: Multicube Explorer and mode-FRONTIER. The description of the proposed algorithms is the central part of the paper. The focus will be on newly developed algorithms and on ad-hoc extensions of existing techniques in order to face with discrete and categorical design space parameters that are very common when working with embedded systems design. This paper will also provide some fundamental guidelines to build a strategy for testing the performance and accuracy of such algorithms. The aim is mainly to build confidence in optimization techniques, rather than to simply compare one algorithm versus another one. The no-free-lunch theorem for optimization has to be taken into consideration and therefore the analysis will look forward to robustness and industrial reliability of the results.},
	author = {Rigoni, Enrico and Kavka, Carlos and Turco, Alessandro and Palermo, Gianluca and Silvano, Cristina and Zaccaria, Vittorio and Mariani, Giovanni}
}
@conference {18081,
	title = {Power-Gated MOS Current Mode Logic (PG-MCML): A Power-Aware DPA-Resistant Standard Cell Library},
	booktitle = {48th Design Automation Conference (DAC)},
	year = {2011},
	month = {June},
	address = {San Diego, Califorina},
	author = {Cevrero, Alessandro and Regazzoni, Francesco and Schwander, Michael and Badel, St{\'e}phane and Ienne, Paolo and Leblebici, Yusuf}
}
@inbook {160.MuSaLuMa.2011,
	title = {Progettazione e valutazione di soluzioni wireless multi-hop per il monitoraggio ambientale},
	booktitle = {MIARIA: Techologia e Conoscenza al Servizio della Sicurezza},
	year = {2011},
	pages = {108-120},
	publisher = {Bellavite},
	organization = {Bellavite},
	address = {Missaglia, Italy},
	abstract = {The creation of a sensors network for environmental monitoring, taking into account the functional and non-functional requirements, poses a series of problems that must be dealt with during the design phase. The main difficulties are related to the power of the nodes and their location so that the resulting network topology minimizes the overall energy consumption while guaranteeing the desired measurement accuracy. The adoption of a {\textquoteright}wireless{\textquoteright} communication model allows for greater flexibility during installation and allows creating remote connections more easily than the traditional wired pattern. Extension of the network topology by add ing new devices in the monitoring area or movement of devices already deployed are greatly simplified. But the requirements in terms of fault-tolerance and power consumption of a wireless network are in general more difficult to meet. In this chapter we propose two different solutions that improve performance in terms of power consumption of the main standard for communication in wireless sensor networks field (e.g. ZigBee) customizing it for monitoring applications in an open environment on geographical areas of several hectares. While the standard is intended to be as general as possible, optimizations have been included considering the special needs of our monitoring applications, in terms of number of nodes, topology density, nodes duty cycle and data-load. The first solution deals with the management of multi-hop communication and allows the use of devices that can be powered by batteries (and possibly small solar panels) for the relaying nodes. The second solution optimizes the management of faults (transient or permanent) in the network topology. It is rarely possible to develop and evaluate proposed solutions in the field prior to actual deployment, therefore simulation is an essential step in developing solutions for these applications. The simulation must be accurate and must provide an analysis of all issues related to communication and the behavioural dynamics of the single node in the network structure. For this reason the evaluation has been carried out by means of a modelling methodology developed expressly for wireless sensor networks.},
	isbn = {978-88-7511-164-9},
	author = {Mura, Marcello and Sami, Mariagiovanna and Luppi, Alessandro and Malchiodi, Gianluca}
}
@inbook {142.PaSiZaRiKaTuMa.2011,
	title = {Response Surface Modeling for Embedded System Design Space Exploration},
	booktitle = {Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach},
	year = {2011},
	publisher = {Springer},
	organization = {Springer},
	address = {New York, USA},
	abstract = {A typical design space exploration flow involves an event-based simulator in the loop, often leading to an actual evaluation time that can exceed practical limits for realistic applications. Chip multi-processor architectures further exacerbate this problem given that the actual simulation speed decreases by increasing the number of cores of the chip. Traditional design space exploration lacks of efficient techniques that reduce the number of architectural alternatives to be analyzed. In this chapter, we introduce a set of statistical and machine learning techniques that can be used to predict system level metrics by using closed-form analytical expressions instead of lengthy simulations; the latter are called Response Surface Models (RSM). The principle of RSM is to exploit a set of simulations generated by one or more Design of Experiments strategies to build a surrogate model to predict the system-level metrics. The response model has the same input and output features of the original simulation based model but offers significant speed-up by leveraging analytical, closed-form functions which are tuned during model training. The techniques presented in this chapter can be used to improve the performance of traditional design space exploration algorithms such as those presented in Chap. 3.},
	author = {Palermo, Gianluca and Silvano, Cristina and Zaccaria, Vittorio and Rigoni, Enrico and Kavka, Carlos and Turco, Alessandro and Mariani, Giovanni}
}
@conference {147.TaMoFe11,
	title = {System Policies for Gradual Tuning of Security and Workload in Wireless Sensor Networks},
	booktitle = {Proceedings of the IEEE Wireless Telecommunication Symposium (WTS)},
	year = {2011},
	month = {April},
	address = {New York, USA},
	abstract = {In wireless sensor networks (WSN) energy consumption is a key issue. Security of communications, with its demand of computational resources, as well as performances are other fundamental issues. Finding a trade-off between performance and energy consumption, yet providing an adequate level of security is very challenging. Traditional solutions for the aforementioned problem assume that the operative environment is well-known and static, thus limiting the flexibility of the system. In this paper, instead, we propose a self-adaptation mechanism for gradual adaption of security and system workload in WSNs. The adaptation process can be tuned by using specific policies both for controlling the running tasks and for customizing the behavior of the self-adaptation mechanism. The ultimate goal is to perform adaptations by maximizing system performances while satisfying power constraints. A case study, implemented on Sun SPOTs, is also presented to show how the self-adaptation mechanism works in a real sensor node.},
	doi = {http://dx.doi.org/10.1109/WTS.2011.5960883},
	author = {Taddeo, Antonio Vincenzo and Morales, Luis Germ{\'a}n Garcia and Ferrante, Alberto}
}
@conference {17740,
	title = {Towards an ESL design framework for adaptive and fault-tolerant MPSoCs: MADNESS or not?},
	booktitle = {Embedded Systems for Real-Time Multimedia (ESTIMedia), 2011 9th IEEE Symposium on},
	year = {2011},
	abstract = {The MADNESS project aims at the definition of innovative system-level design methodologies for embedded MP-SoCs, extending the classic concept of design space exploration in multi-application domains to cope with high heterogeneity, technology scaling and system reliability. The main goal of the project is to provide a framework able to guide designers and researchers to the optimal composition of embedded MPSoC architectures, according to the requirements and the features of a given target application field. The proposed approach will tackle the new challenges, related to both architecture and design methodologies, arising with the technology scaling, the system reliability and the ever-growing computational needs of modern applications. The methodologies proposed with this project act at different levels of the design flow, enhancing the state-of-the art with novel features in system-level synthesis, architectural evaluation and prototyping. Support for fault resilience and efficient adaptive runtime management is introduced at hardware and middleware level, and considered by the system-level synthesis as one of the optimization factors to be taken into account. This paper presents the first stable results obtained in the MADNESS project, already demonstrating the effectiveness of the proposed methods.},
	keywords = {adaptive MPSoC, adaptive runtime management, computer architecture, embedded MPSoC architectures, emulation, ESL design framework, fault resilience, fault tolerance, fault tolerant MPSoC, field programmable gate arrays, hardware, integrated circuit reliability, libraries, MADNESS project, middleware, multiprocessing systems, network synthesis, program processors, system level design methodologies, system level synthesis, system reliability, system-on-chip (SoC)},
	doi = {10.1109/ESTIMedia.2011.6088518},
	author = {Cannella, Emanuele and Di Gregorio, Lorenzo and Fiorin, Leandro and Lindwer, Menno and Meloni, Paolo and Neugebauer, Olaf and Pimentel, Andy}
}
@conference {17694,
	title = {WAMS - an adaptive system for knowledge acquisition and decision support: the case of Scaphoideus titanus},
	booktitle = {IOBC/WPRS European Meeting},
	year = {2011},
	month = {10/2011},
	pages = {57-64},
	publisher = {Working Group on Integrated Protection and Production in Viticulture},
	organization = {Working Group on Integrated Protection and Production in Viticulture},
	address = {Lacanau, France},
	author = {Prevostini, Mauro and Taddeo, Antonio Vincenzo and Bala{\'c}, Katarina and Rigamonti, Ivo and Baumg{\"a}rtner, Johann and Jermini, Mauro}
}
@conference {124.LuKaBo10,
	title = {Adopting system engineering methodology to Virtual Power Systems design flow},
	booktitle = {CPSWEEK/GREEMBED 2010: Proceedings of the First Workshop on Green and Smart Embedded System Technology: Infrastructures, Methods and Tools},
	year = {2010},
	month = {April},
	address = {Stockholm, Sweden},
	abstract = {The concept of Virtual Power System (VPS) emerges as a promising response for increased concerns on secure, sustainable and at the same time {\textquoteright}clean{\textquoteright} energy supply requests. This novel concept aims at boosting operational efficiency of Distributed Energy Resources (DER) but also at establishing them as an autonomous commercial actor on the open energy market. Nevertheless, VPSs are fairly complex HW/SW systems that require holistic multidisciplinary approach and also novel specification, modeling and analysis instruments to facilitate mutual understanding among stakeholders from different fields. We introduce UML/SysML based modeling methodology to describe such power system related issues aiming at providing an unified modeling instrument applicable for VPSs design flow. In the proposed system engineering methodology, system representation starts from a very general context description and gets refined through different levels of abstraction down to concrete embedded systems employed to perform defined tasks.},
	author = {Lukovi{\'c}, Slobodan and Kaitovi{\'c}, Igor and Bondi, Umberto}
}
@conference {126.MaPaZaBrJoSi11,
	title = {A Correlation-based Design Space Exploration Methodology for Multi-Processor Systems-on-Chip},
	booktitle = {Proceedings of DAC 2010: Design Automation Conference},
	year = {2010},
	month = {June},
	pages = {120{\textendash}125},
	address = {Anheim, CA, USA},
	abstract = {Given the increasing complexity of multi-processor systems-on-chip, a wide range of parameters must be tuned to find the best trade-offs in terms of the selected system figures of merit (such as energy, delay and area). This optimization phase is called Design Space Exploration (DSE) consisting of a Multi-Objective Optimization (MOO) problem. In this paper, we propose an iterative design space exploration methodology exploiting the statistical properties of known system configurations to infer, by means of a correlation-based analysis, the next design points to be analyzed with low-level simulations. In fact, the knowledge of few design points is used to predict the expected improvement of unknown configurations. We show that the correlation of the configurations within the multi-processor design space can be modeled successfully with analytical functions and, thus, speed up the overall exploration phase. This makes the proposed methodology a model-assisted heuristic that, for the first time, exploits the correlation about architectural configurations to converge to the solution of the multi-objective problem.},
	keywords = {design space exploration, kriging, multiprocessor system-on-chip (MPSoC), response surface},
	author = {Mariani, Giovanni and Palermo, Gianluca and Zaccaria, Vittorio and Brankovic, Aleksandar and Jovic, Jovana and Silvano, Cristina}
}
@conference {114.MaYkZhZhLa10,
	title = {An Efficient Run-Time Management Methodology for Stereo Matching Application},
	booktitle = {2PARMA: Proceedings of the Workshop on Parallel Programming and Run-time Management Techniques for Many-core Architectures},
	year = {2010},
	month = {February},
	address = {Hannover, Germany},
	abstract = {This paper presents a methodology for Run-Time Management (RTM) of algorithmic parameters. The RTM is able to trade-off the algorithm output quality and the execution time. Thus, once a requirement in terms of maximum execution time is set, the RTM dynamically tunes the parameters in order to maximize the output quality while respecting the given requirement. The run-time decision making relies on design-time modeling techniques able to characterize key relations between algorithm parameters, execution time and output quality. Models generated during the design-time analysis are accurate enough to drive the RTM in its decision making while enough generic to model application behaviors over datasets which were not included at design-time. In this paper the methodology is applied on the Stereo Matching application, a computational intensive artificial vision application aimed at inferring object depths using two or more cameras. Experimental results prove the effectiveness of the methodology which is able to identify high quality solutions respecting required deadline while introducing negligible overhead.},
	author = {Mariani, Giovanni and Ykman-Couvreur, Chantal and Zhang, Ke and Zhang, Lu and Lafruit, Gauthier}
}
@conference {135.VuLuErKu10.2,
	title = {An enhanced workflow management for Utility Management System},
	booktitle = {Proceedings of the International Congress on Ultra Modern Telecommunications and Control Systems (ICUMT 2010)},
	year = {2010},
	month = {October 18-20},
	address = {Moscow, Russia},
	abstract = {The emerging computational grid infrastructure consists of widely distributed heterogeneous resources, which makes mapping of increasingly complex applications a very challenging task. Utility Management Systems (UMS) manage very large number of workflows with very high resource requirements and thereby optimization of resource utilization has to be adapted. In this work we propose architecture that implements a novel concept for dynamical execution of a scheduling algorithm using near real-time feedback from the execution monitoring process. An Artificial Neural Network (ANN) was trained for workflow scheduling. In the case study, we first perform experiments with same number of workflows and then introduce two additional in the system observing its behavior with and without proposed improvements. Performance tests show that significant improvements of overall execution time can be achieved by introducing adaptive Artificial Neural Network.},
	doi = {http://dx.doi.org/10.1109/ICUMT.2010.5676601},
	author = {Vukmirovi{\'c}, Srdjan and Lukovi{\'c}, Slobodan and Erdeljan, Aleksandar and Kuli{\'c}, Filip}
}
@conference {133.LuNi10.2,
	title = {Enhancing Network-on-Chip Components to Support Security of Processing Elements},
	booktitle = {Proceedings of the 5th Workshop on Embedded Systems Security (WESS{\textquoteright}2010) A Workshop of the Embedded Systems Week (ESWEEK {\textquoteright}10)},
	year = {2010},
	month = {October 24},
	address = {Scottsdale, AZ, USA},
	abstract = {Network-on-Chip (NoC) has emerged as a promising solution for scalable communication among steadily growing number of cores integrated in MultiProcessor System-on-Chips (MPSoCs). The increasing system heterogeneity together with the possibility of recon guration makes the overall system security one of the major concerns in MPSoC design. On the other hand, modular and scalable design of NoCs enables their enhancements in various directions for supporting services other than simple data routing. In this work we propose and implement a solution to secure attached processing units from a bu er over ow type of the attacks that comes in a form of a protection module that is embedded into the Network Interface of the NoC. At the same time, our solution prevents potential propagation of the attack through the NoC towards other processors. We prove feasibility via prototype realization in FPGA technology for a MicroBlaze processor on Xilinx Virtex-II Pro board.},
	doi = {http://dx.doi.org/10.1145/1873548.1873560},
	author = {Lukovi{\'c}, Slobodan and Christianos, Nikolaos}
}
@conference {18083,
	title = {Fresh Re-Keying: Security against Side-Channel and Fault Attacks for Low-Cost Devices},
	booktitle = {Proceedings of Progress in Cryptology - Africacrypt},
	year = {2010},
	month = {May},
	address = {Stellenbosch, South Africa},
	author = {Medwed, Marcel and Standaert, Fran{\c c}ois-Xavier and Gro{\ss}sch{\"a}dl, Johann and Regazzoni, Francesco}
}
@conference {130.LuKaMuBoKuPo10,
	title = {Functional model of Virtual Power Plant (VPP)},
	booktitle = {Proceedings of the 2010 CIGRE (International Council on Large Electric Systems) Session},
	year = {2010},
	month = {July},
	address = {Paris, France},
	keywords = {smart grid, unified modeling language (UML), virtual power plants},
	author = {Lukovi{\'c}, Slobodan and Kaitovi{\'c}, Igor and Mura, Marcello and Bondi, Umberto and Kuli{\'c}, Filip and Popovi{\'c}, Dragan}
}
@conference {127.TaMiFe10,
	title = {Gradual Adaptation of Security for Sensor Networks},
	booktitle = {IEEE WoWMoM 2010: Proceedings of the IEEE International Symposium on a World of Wireless Mobile and Multimedia Networks},
	year = {2010},
	month = {June 13},
	address = {Montreal, Canada},
	abstract = {Wireless sensor networks are composed by nodes with stringent constraints on resources. In particular, a very limited power consumption is often a key factor for this kind of devices. In this paper we describe a method for security self-adaptation tailed for wireless sensor networks. This method allows devices to adapt security of applications gradually with the goal of guaranteeing the maximum possible level of security while satisfying system constraints. A case study is also presented to show how the method works in a real wireless sensor network.},
	keywords = {graceful degradation, gradual adaptation, security, sensors networks},
	doi = {http://dx.doi.org/10.1109/WOWMOM.2010.5534903},
	author = {Taddeo, Antonio Vincenzo and Micconi, Laura and Ferrante, Alberto}
}
@conference {18082,
	title = {Hardware Trojans for Inducing or Amplifying Side-Channel Leakage of Cryptographic Software},
	booktitle = {2nd International Conference on Trusted Systems (INTRUST)},
	year = {2010},
	month = {December},
	address = {Beijing, China},
	author = {Gallais, Jean-Francois and Gro{\ss}sch{\"a}dl, Johann and Hanley, Neil and Kasper, Markus and Medwed, Marcel and Regazzoni, Francesco and Schmidt, Joern-Marc and Tillich, Stefan and Wojcik, Marcin}
}
@conference {134.FiFePaCa10,
	title = {Hardware-assisted Security Enhanced Linux in Embedded Systems: a Proposal},
	booktitle = {Proceedings of the 5th Workshop on Embedded Systems Security (WESS{\textquoteright}2010)},
	year = {2010},
	month = {October 24},
	address = {Scottsdale, Arizona, USA},
	abstract = {As computing and communications increasingly pervade our lives, security and protection of sensitive data and systems are emerging as extremely important issues. This is especially true for embedded systems, often operating in non-secure environments, and with limited amount of computational, storage, and communication resources available. In servers and desktop systems, Security Enhanced Linux (SELinux) is currently used as a method to enhance security by enforcing a security control based on policies that confine user programs, or processes, to the minimum amount of privileges that they require for their execution. While providing a powerful mean for enhancing security in UNIX-like systems, SELinux still remains a feature that is too heavy to be fully supported by constrained devices. In this paper, we propose a hardware architecture for enhancing security and accelerating retrieval and applications of SELinux policies in embedded processors. We describe the general ideas be hind our work, discussing motivations, advantages, and limits of the solution proposed, while suggesting the main steps needed to implement the described architecture on common embedded processors.},
	keywords = {access controls, embedded systems, SELinux},
	author = {Fiorin, Leandro and Ferrante, Alberto and Padarnitsas, Konstantinos and Carucci, Stefano}
}
@conference {132.LuNi10,
	title = {Hierarchical Multi-Agent Protection System for NoC based MPSoCs},
	booktitle = {Proceedings of the International Workshop on Security and Dependability for Resource Constrained Embedded Systems (SD4RCES 2010)},
	year = {2010},
	month = {September 14},
	address = {Vienna, Austria},
	abstract = {Network-on-Chip (NoC) has emerged as a promising solution for scalable communication among steadily growing number of cores integrated in MultiProcessor System-on-Chips (MPSoCs). The increasing system heterogeneity together with the possibility of reconfiguration makes the overall system security one of the major concerns in MPSoC design. On the other hand, modular and scalable design of NoCs enables their enhancements in various directions for supporting services other than simple data routing. In this work we propose a conceptual solution to secure NoC based MPSoCs at different levels of design. The basic idea is to integrate various kinds of security approaches from attack specific protection strategies up to system level security. The concept aims at securing single cores but also, at the same time, prevents potential propagation of the attack through the NoC towards. We prove feasibility via prototype realization in FPGA technology.},
	keywords = {multiprocessor system-on-chip (MPSoC), network-on-chip (NoC), security},
	doi = {http://dx.doi.org/10.1145/1868433.1868441},
	author = {Lukovi{\'c}, Slobodan and Christianos, Nikolaos}
}
@conference {117.MaAvVaYkPaSiZa10,
	title = {An industrial design space exploration framework for supporting run-time resource management on multi-core systems},
	booktitle = {Proceedings of Design, Automation and Test in Europe (DATE) Conference},
	year = {2010},
	month = {March},
	address = {Dresden, Germany},
	abstract = {Current multi-core design methodologies are facing increasing unpredictability in terms of quality due to the actual diversity of the workloads that characterize the deployment scenario. To this end, these systems expose a set of dynamic parameters which can be tuned at run-time to achieve a specified Quality of Service (QoS) in terms of performance. A run-time manager operating system module is in charge of matching the specified QoS with the available platform resources by manipulating the overall degree of task-level parallelism of each application as well as the frequency of operation of each of the system cores. In this paper, we introduce a design space exploration framework for enabling and supporting enhanced resource management through software re-configuration on an industrial multicore platform. From one side, the framework operates at design time to identify a set of promising operating points which represent the optimal trade-off in terms of the target power consumption and performance. The operating points are used after the system has been deployed to support an enhanced resource management policy. This is done by a light-weight resource management layer which filters and selects the optimal parallelism of each application and operating frequency of each core to achieve the QoS constraints imposed by the external world and/or the user. We show how the proposed design-time and run-time techniques can be used to optimally manage the resources of a multiple-stream MPEG4 encoding chip dedicated to automotive cognitive safety tasks.},
	author = {Mariani, Giovanni and Avasare, Prabhat and Vanmeerbeeck, Geert and Ykman-Couvreur, Chantal and Palermo, Gianluca and Silvano, Cristina and Zaccaria, Vittorio}
}
@conference {119.AvVaYkMaPaZaSi10,
	title = {Linking run-time management with design space exploration at multiple abstraction levels},
	booktitle = {Proceedings of the DATE{\textquoteright}10 workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications},
	year = {2010},
	month = {March},
	address = {Dresden, Germany},
	abstract = {In present era of Multi-Processor System-on-Chip (MPSoC) embedded devices, to run multiple applications optimally (in terms of execution time and power consumption) is an enormous challenge. Embedded designers usually tackle this challenge by dividing it in two parts : at design-time Design Space Explorations (DSE) are performed to derive Pareto set of optimum operating points for each application and at run-time embedded device is monitored continuously to operate at one of the points in the derived Pareto set. Obviously run-time management relies heavily on accuracy of DSE. With growing complexity of embedded devices and with time-to-market pressures, at design-time, it is not trivial to derive the operating point Pareto set. On the other hand, at run-time, overhead introduced by a run-time management scheme should also not be high so as to minimally affect embedded device performance . We have developed techniques to tackle these embedded design issues. At design time, we use DSE with multiple simulators running at multiple abstraction levels to converge quickly to Pareto set of operating points. At runtime, to keep run-time overhead to a minimum, a hierarchical Runtime Resource Manager (RRM) is used with well-defined interfaces (services) between global and local resource managers. We applied our methodology on an embedded device having eight processor cores running multiple MPEG4 encoders. With our DSE methodology, we could derive Pareto set much quickly (as compared to full-space explorations). With our run-time schemes, overhead introduced by run-time manager was negligible.},
	author = {Avasare, Prabhat and Vanmeerbeeck, Geert and Ykman-Couvreur, Chantal and Mariani, Giovanni and Palermo, Gianluca and Zaccaria, Vittorio and Silvano, Cristina}
}
@conference {18087,
	title = {Low Cost Software Countermeasures Against Fault Attacks: Implementation and Performances Trade Offs},
	booktitle = {5th Workshop on Embedded Systems Security (WESS)},
	year = {2010},
	month = {October},
	address = {Scottsdale, Arizona, USA},
	author = {Barenghi, Alessandro and Breveglieri, Luca and Koren, Israel and Pelosi, Gerardo and Regazzoni, Francesco}
}
@inbook {17693,
	title = {MDE Support for HW/SW Codesign: a UML-based Design Flow},
	booktitle = {Advances in Design Methods from Modeling Languages for Embedded Systems and SoC{\textquoteright}s},
	year = {2010},
	pages = {19-37},
	publisher = {Springer},
	organization = {Springer},
	address = {Dordrecht, The Netherlands},
	author = {Murillo, Luis Gabriel and Mura, Marcello and Prevostini, Mauro}
}
@conference {136.FiPaSi10,
	title = {A Monitoring System for NoCs},
	booktitle = {Proceedings of the Third International Workshop on Network on Chip Architectures (NoCArc{\textquoteright}2010)},
	year = {2010},
	month = {December},
	address = {Atlanta, Georgia, USA},
	abstract = {In this paper, we propose and discuss a monitoring architecture for Networks-on-Chip (NoCs) that provides system information useful for helping designers in efficiently exploiting resources available in new complex Multiprocessor System-on-Chip (MPSoC) platforms, and in understanding their behavior. We focus on the analysis of the architectural details and design challenges of such systems, by describing power- ful tools for detecting information that can be used both at run-time for detecting dynamic changes in system behavior and at post-execution time for debugging and profiling of applications. We detail the design of the probes monitoring the events and discuss an architecture for collection, storage, and analysis of information generated by them. We evaluate cost of the implementation of the system in terms of area and traffic overhead, and we present results obtained when monitoring a use-case multimedia application.},
	keywords = {hardware counters, network-on-chip (NoC), performance monitoring, system-on-chip (SoC)},
	author = {Fiorin, Leandro and Palermo, Gianluca and Silvano, Cristina}
}
@conference {115.ZaPaCaSiMa10,
	title = {Multicube Explorer: An Open Source Framework for Design Space Exploration of Chip Multi-Processors},
	booktitle = {2PARMA: Proceedings of the Workshop on Parallel Programming and Run-time Management Techniques for Many-core Architectures},
	year = {2010},
	month = {February},
	address = {Hannover, Germany},
	abstract = {Given the increasing complexity of Chip Multi-Processors (CMPs), a wide range of architecture parameters must be explored at design time to find the best trade-off in terms of multiple competing objectives (such as energy, delay, bandwidth, area, etc.) The design space of the target architecture is huge because of it should consider all possible combinations of each parameter (number of processors, processor issue width, L1 and L2 cache sizes, etc.). In this complex scenario, the multi-objective exploration of the huge design space of next generation CMPs cannot be anymore based on intuition and past experience of the design architects. An Automatic Design Space Exploration methodology is needed to support systematically the exploration and the quantitative comparison of the design alternatives in terms of multiple competing objectives (Pareto analysis). An overall design space exploration framework is needed to combine all optimizations into a global search space with a common interface to the simulation and evaluation tools. Our work1 focuses on the definition of an automatic multi-objective Design Space Exploration (DSE) framework for tuning Chip Multi-Processor architectures by evaluating a set of metrics (such as energy and delay) for the next generation embedded computing platforms. Multicube Explorer is an interactive open-source framework to enable the designer to automatically explore a design space of configurations for a parameterized architecture for which an executable model (use case simulator) exists. Multicube Explorer is an advanced multi-objective optimization framework which is entirely command-line/script driven and can be re-targeted to any configurable platform by writing a suitable XML design space definition file and providing a configurable simulator},
	author = {Zaccaria, Vittorio and Palermo, Gianluca and Castro, Fabrizio and Silvano, Cristina and Mariani, Giovanni}
}
@conference {129.Sietal.ISVLSI11,
	title = {Multicube: Multi-objective design space exploration of multi-core architectures},
	booktitle = {ISVLSI 2010: IEEE Annual Symposium on VLSI},
	year = {2010},
	month = {July},
	pages = {488{\textendash}493},
	address = {Lixouri, Kefalonia - Greece},
	abstract = {Technology trends enable the integration of many processor cores in a System-on-Chip (SoC). In these complex architectures, several architectural parameters can be tuned to find the best trade-off in terms of multiple metrics such as energy and delay. The main goal of the MULTICUBE project consists of the definition of an automatic Design Space Exploration framework to support the design of next generation many-core architectures.},
	doi = {http://dx.doi.org/10.1109/ISVLSI.2010.67},
	author = {Silvano, Cristina and Fornaciari, William and Palermo, Gianluca and Zaccaria, Vittorio and Castro, Fabrizio and Martinez, Marcos and Bocchio, Sara and Zafalon, Roberto and Avasare, Prabhat and Vanmeerbeeck, Geert and Ykman-Couvreur, Chantal and Wouters, Maryse and Kavka, Carlos and Onesti, Luka and Turco, Alessandro and Bondi, Umberto and Mariani, Giovanni and Posadas, Hector and Villar, Eugenio and Wu, Chris and Dongrui, Fan and Hao, Zhang and Shibin, Tang}
}
@conference {128.Taddeo2010c,
	title = {QoS and Security in Energy-harvesting Wireless Sensor Networks},
	booktitle = {Proceedings of ICETE SECRYPT},
	year = {2010},
	month = {July},
	address = {Athens, Greece},
	abstract = {Wireless sensor networks are composed of small nodes that might be used for a variety of purposes. Nodes communicate together through a wireless connection that might be subject to different attacks when the network is placed in hostile environments. Furthermore, the nodes are usually equipped with very small batteries providing limited battery life, therefore limited power consumption is of utmost importance for nodes. This is in clear opposition with the requirement of providing security to communications as security might be very expensive from the power consumption stand point. Energy harvesting methods can be used to recharge batteries, but, in most of the cases the recharge profile cannot be known in advance. Therefore, nodes might face periods of time in which no recharge is available and the battery level is low. In this paper we introduce an optimization mechanism that allows the system to change the communication security settings at runtime with the goal of improving node lifetime, yet providing a suitable security level. The optimization mechanism further improves energy consumption by putting in place a quality of service mechanism: when energy is scarce, the system tends to send only essential packets. As shown by the simulations presented in this paper, this mechanism optimizes the energy consumption among different recharges.},
	keywords = {energy harvesting, priority, quality of service (QoS), security, wireless sensor networks},
	author = {Taddeo, Antonio Vincenzo and Mura, Marcello and Ferrante, Alberto}
}
@conference {116.TuRePaFeSc10,
	title = {A Reconfigurable Multiprocessor Architecture for a Reliable Face Recognition Implementation},
	booktitle = {Proceedings of Design, Automation and Test in Europe (DATE) Conference},
	year = {2010},
	month = {March},
	address = {Dresden, Germany},
	abstract = {Face Recognition techniques are solutions used to quickly screen a huge number of persons without being intrusive in open environments or to substitute id cards in companies or research institutes. There are several reasons that require to systems implementing these techniques to be reliable. This paper presents the design of a reliable face recognition system implemented on Field Programmable Gate Array (FPGA). The proposed implementation uses the concepts of multiprocessor architecture, parallel software and dynamic reconfiguration to satisfy the requirement of a reliable system. The target multiprocessor architecture is extended to support the dynamic reconfiguration of the processing unit to provide reliability to processors fault. The experimental results show that, due to the multiprocessor architecture, the parallel face recognition algorithm can achieve a speed up of 63\% with respect to the sequential version. Results regarding the overhead in maintaining a reliable architecture are also shown},
	author = {Tumeo, Antonino and Regazzoni, Francesco and Palermo, Gianluca and Ferrandi, Fabrizio and Sciuto, Donatella}
}
@conference {121.DeFe10,
	title = {Scheduling energy consumption with local renewable micro-generation and dynamic electricity prices},
	booktitle = {CPSWEEK/GREEMBED 2010: Proceedings of the First Workshop on Green and Smart Embedded System Technology: Infrastructures, Methods and Tools},
	year = {2010},
	month = {April},
	address = {Stockholm, Sweden},
	abstract = {The electricity market is going through a deep modification as it is moving toward the integration of smart grids. Future homes will include smarter electric devices that will be easily managed from the power consumption stand point. The capability of performing short-term negotiation of energy purchases, if introduced and if efficiently exploited, will give the user the ability to reduce energy costs. In this paper we discuss a scheduling problem for household tasks that will help users save money spent on their energy consumption. Our system model relies on electricity price signals, availability of locally-generated power and flexible tasks with deadlines. A case study shows that cost savings are possible but fast and efficient solutions to the scheduling problem are needed for their real world use.},
	keywords = {scheduling, smart grid, smart home},
	author = {Derin, Onur and Ferrante, Alberto}
}
@conference {17743,
	title = {Security and Packets Delivery Trade-Off for WSN},
	booktitle = {Consumer Communications and Networking Conference (CCNC), 2010 7th IEEE},
	year = {2010},
	abstract = {The optimization of resources to be used for securing transmissions in wireless sensor networks while retaining communication quality of service is a challenging task. In this paper, we propose an energy-aware mechanism to determine the most efficient set of packets to be processed according with the resource consumed and the packets delivery requirements.},
	keywords = {authentication, costs, data security, delay, energy consumption, energy-aware mechanism, information security, network security, packet radio networks, packets delivery requirements, packets delivery trade-off, protection, quality of service (QoS), runtime, telecommunication security, wireless sensor networks, WSN},
	doi = {10.1109/CCNC.2010.5421689},
	author = {Taddeo, Antonio Vincenzo and Ferrante, Alberto}
}
@conference {137.VuLuErKu10.3,
	title = {A Smart Metering Architecture as a step towards Smart Grid realization},
	booktitle = {Proceedings of the IEEE EnergyCon 2010},
	year = {2010},
	month = {December 18-22},
	address = {Bahrain},
	abstract = {Emerging concept of Smart Grids aims at increasing visibility and controllability of electricity grids boosting their operational efficiency, enabling novel enhanced services to customers and utilities at a same time. Successful realization of this concept will in great part depend on efficient management of tremendous amounts of data to be gathered and processed in very short time periods. In this work we propose a novel smart metering architecture to manage data collected from deployed smart meters logically encapsulated in form of virtual meters. The metering infrastructure is structured in the form of Advanced Metering Infrastructure (AMI). The architecture of Meter Data Management (MDM) system as well and its integration in Control Center structure of power system is described in details. The testing and verification of proposed solution is performed on data from power distribution company Vattenfall, Sweden.},
	doi = {http://dx.doi.org/10.1109/ENERGYCON.2010.5771705},
	author = {Vukmirovi{\'c}, Srdjan and Lukovi{\'c}, Slobodan and Erdeljan, Aleksandar and Kuli{\'c}, Filip}
}
@conference {122.VuErKuLu10,
	title = {Software architecture for Smart Metering systems with Virtual Power Plant},
	booktitle = {Proceedings of the 15th IEEE Mediterranean Electrotechnical Conference (MELECON2010)},
	year = {2010},
	month = {April},
	address = {La Valleta, Malta},
	abstract = {This paper presents a novel architecture for Smart Metering systems which enables their seamless, secure and efficient integration in wider SmartGrid software structures. Smart metering solutions represent one of the fastest evolving areas in the field of power distribution systems. There is an extensive interest of leading software vendors in the field, for development of architectures that can efficiently manage transmission, processing and storing of tremendous amount of data produced by such metering devices deployed at the end-end side. The integration of these systems into existing power system software architectures (outage management, workforce management, etc.) represents a major challenge for research community. In such an environment it is extremely important to adopt standardized data exchange mechanisms. The proposed architecture is conceived as modular and scalable structure so that it can help implementation of novel power distribution concepts such as Virtual Power Plants (VPPs). The proposed architecture has been successfully tested and verified in real-life operation as one of modules of Smart Metering system named Meter Data Management (MDM) developed by Telvent DMS Llc, Serbia.},
	doi = {http://dx.doi.org/10.1109/MELCON.2010.5476237},
	author = {Vukmirovi{\'c}, Srdjan and Erdeljan, Aleksandar and Kuli{\'c}, Filip and Lukovi{\'c}, Slobodan}
}
@conference {131.VuLuErKu10,
	title = {A solution for CIM based integraton of Meter Data Management in Control Center of a power system},
	booktitle = {Proceedings of the 2010 IEEE Workshop on Environmental, Energy, and Structural Monitoring Systems (EESMS{\textquoteright}10)},
	year = {2010},
	month = {September 9},
	address = {Taranto, Italy},
	abstract = {Modern power systems, in particular Control Center structures, involve more and more software applications in their normal operation. Such scenario urges for standardization of inter and intra processes communication and data exchange. In this work we propose a solution for seamless Meter Data Management (MDM) integration with Control Center structures through Common Information Model (CIM). The solution is implemented in form of a wrapper that adopts messages (i.e. payloads) to the standard requested form. The proposed solution has been verified using a simulation framework which emulates regular control and data.},
	keywords = {monitoring and control, system level modeling, virtual power plants},
	doi = {http://dx.doi.org/10.1109/EESMS.2010.5634169},
	author = {Vukmirovi{\'c}, Srdjan and Lukovi{\'c}, Slobodan and Erdeljan, Aleksandar and Kuli{\'c}, Filip}
}
@conference {123.LuPeFi10,
	title = {Stack Protection Unit as a step towards securing MPSoCs},
	booktitle = {Proceedings of 24th IEEE International Parallel and Distributed Processing Symposium (IPDPS)},
	year = {2010},
	month = {April 19-23},
	address = {Atlanta, USA},
	abstract = {Reconfigurable technologies are getting popular as an instrument for not only verification and prototyping but also commercial implementation of Multi-Processor Systems-on-Chip (MPSoC) architectures. At the same time, these systems in particular Networks-on-Chip (NoCs) based ones, have emerged as a design strategy to cope with increased requirements and complexity of modern applications. Nevertheless, increasing heterogeneity coupled with possibility of reconfiguration makes security become one of major concerns in MPSoC design. Protection strategies must consider attack scenarios at both levels - individual cores and system level security. This work represents an element in a wider security framework, it shows a solution against one of the most widespread types of attacks - code injection. Our response to tackle this challenge is given in form of Stack Protection Unit (SPU) embedded into processing core. MicroBlaze soft-core processor serves as a case study for verification of the proposed solution in FPGA technology.},
	keywords = {FPGA, microblaze, security, stack protection unit},
	doi = {http://dx.doi.org/10.1109/IPDPSW.2010.5470728},
	author = {Lukovi{\'c}, Slobodan and Pezzino, Paolo and Fiorin, Leandro}
}
@conference {113.LuCoKu10,
	title = {A system level model of possible integration of Building Management System in SmartGrid},
	booktitle = {Complexity in Engineering (COMPENG 2010)},
	year = {2010},
	month = {February 22-24},
	address = {Rome, Italy},
	abstract = {SmartGrids are conceived as modular, end-to-end interoperable systems. It is envisaged that power systems components (modules) will be hierarchically coordinated and integrated in order to form certain autonomous clusters which would perform as much as possible local data storing and processing in order to decrease overall communicational and computational overhead. Building Management Systems (BMS) could be seen as one of such modules inside wider SmartGrid system. The incorporation of BMS must consider both technical as well as commercial issues. Hence, the efficient integration will require standards{\textquoteright} harmonization and closer interaction among key elements of these systems. Moreover, another important issue will be adopting of new market models to BMS. In order to represent the system and relations among its components in a clear and understandable fashion, we introduce system level modeling concept as an instrument to bridge functional requirements and implementation constraints.},
	doi = {http://dx.doi.org/10.1109/COMPENG.2010.43},
	author = {Lukovi{\'c}, Slobodan and {\v C}ongradac, Velimir and Kuli{\'c}, Filip}
}
@conference {125.DeDi10,
	title = {A Task-aware Middleware for Fault-tolerance and Adaptivity of Kahn Process Networks on Network-on-Chip},
	booktitle = {ReCoSoC 2010: Proceedings of the Fifth International Workshop on Reconfigurable Communication Centric System-on-Chips},
	year = {2010},
	month = {May},
	address = {Karlsruhe, Germany},
	abstract = {We propose a task-aware middleware concept and provide details for its implementation on Network-on-Chip (NoC). We also list our ideas on the development of a simulation platform as an initial step towards creating fault-tolerance strategies for Kahn Process Networks (KPN) applications running on NoCs. In doing that, we extend our SACRE (Self-adaptive Component Run-time Environment) framework by integrating it with an open source NoC simulator, Noxim. We also hope that this work may help in identifying the requirements and implementing fault tolerance and adaptivity support on real platforms.},
	keywords = {fault tolerance, kahn process networks (KPN), middleware, network-on-chip (NoC), self-adaptivity},
	author = {Derin, Onur and Diken, Erkan}
}
@conference {118.CaVeStShCeLeAsMe10,
	title = {Trace-based KPN Composability Analysis for Mapping Simultaneous Applications to MPSoC Platforms},
	booktitle = {Proceedings of Design, Automation and Test in Europe(DATE) Conference},
	year = {2010},
	month = {March},
	address = {Dresden, Germany},
	abstract = {Nowadays, most embedded devices need to support multiple applications running concurrently. In contrast to desktop computing, very often the set of applications is known at design time and the designer needs to assure that critical applications meet their constraints in every possible use-case. In order to do this, all possible use-cases, i.e. subset of applications running simultaneously, have to be verified thoroughly. An approach to reduce the verification effort, is to perform composability analysis which has been studied for sets of applications modeled as Synchronous Dataflow Graphs. In this paper we introduce a framework that supports a more general parallel programming model based on the Kahn Process Networks Model of Computation and integrates a complete MPSoC programming environment that includes: compilercentric analysis, performance estimation, simulation as well as mapping and scheduling of multiple applications. In our solution, composability analysis is performed on parallel traces obtained by instrumenting the application code. A case study performed on three typical embedded applications, JPEG, GSM and MPEG-2, proved the applicability of our approach.},
	author = {Castrill{\'o}n, Jer{\'o}nimo and Vel{\'a}squez, Ricardo and Stulova, Anastasia and Sheng, Weihua and Ceng, Jianjiang and Leupers, Rainer and Ascheid, Gerd and Meyr, Heinrich}
}
@conference {120.ArMuPr10,
	title = {Using MARTE for Designing power Supply Section of WSNs},
	booktitle = {M-BED 2010: Proceedings of the 1st Workshop on Model Based Engineering for Embedded Systems Design (a DATE 2010 Workshop)},
	year = {2010},
	month = {March 12},
	address = {Dresden, Germany},
	abstract = {Probably the biggest issue while tackling Wireless Sensor Networks design has always been providing them with adequate power supplies. Energy Harvesting was proposed as an essential feature for Wireless Sensor Networks (WSN)s in many application fields when the amount of energy contained in a commercial battery does not allow fulfilling the required mission. Solar energy is the most widespread mechanism used to harvest energy of the environment because of its good power density. However it introduces a level of uncertainty on the amount of energy available in the system. In this paper we propose a high level methodology for designing the power supply section of sensor nodes. In particular we suggest how to use MARTE UML design language in order to collect requirements for the application and transform them into specifications of the power supply system. The framework we propose aims at validating the design by simulating appropriate scenarios.},
	author = {Argyris, Ioannis and Mura, Marcello and Prevostini, Mauro}
}
@conference {112.LuKaMuBo10,
	title = {Virtual Power Plant as a bridge between Distributed Energy Resources and Smart Grid},
	booktitle = {Proceedings of 43th Hawaii International Conference on System Sciences (HICSS{\textquoteright}43)},
	year = {2010},
	month = {January},
	address = {Hawaii, USA},
	abstract = {The liberalization of energy markets, especially in correlation with the Smart Grid concept development, requires adjusted legislation, new business models, energy stock exchanges establishment and many other advanced instruments. Realization of these features necessitates novel concepts to support such changes in the power system while granting security and reliability of supply. Such evolution poses new challenges to ICT (Information and Communication Technologies) to bridge the gap between increased complexity of deregulated market and on the other side expected rapid growth of number of players in power systems. Increasing presence of Distributed Energy Resources (DER) implementations constitutes a further source of complexity. Bearing in mind ongoing and possible scenarios we aim to determinate the place and role of the novel Virtual Power Plants (VPP) concept, related to the Smart Grid structure. At the same time we introduce an innovative modeling approach as an instrument to determine actors and highlight their actual roles and interactions from different point of view, trying to pave the way for development of a common understanding platform for variety of stakeholders. The effectiveness of the proposed modeling concept is shown through a number of UML models representing system level description of VPP at different levels of abstraction.},
	keywords = {distributed energy resources, smart grid, unified modeling language (UML), virtual power plants},
	doi = {http://dx.doi.org/10.1109/HICSS.2010.437},
	author = {Lukovi{\'c}, Slobodan and Kaitovi{\'c}, Igor and Mura, Marcello and Bondi, Umberto}
}
@article {18492,
	title = {Breaking ECC2K-130},
	journal = {IACR Cryptology ePrint Archive},
	volume = {2009},
	year = {2009},
	month = {11/2009},
	pages = {541},
	abstract = {Elliptic-curve cryptography is becoming the standard public-key primitive not only for mobile devices but also for high-security applications. Advantages are the higher cryptographic strength per bit in comparison with RSA and the higher speed in implementations. To improve understanding of the exact strength of the elliptic-curve discrete-logarithm problem, Certicom has published a series of challenges. This paper describes breaking the ECC2K-130 challenge using a parallelized version of Pollard{\textquoteright}s rho method. This is a major computation bringing together the contributions of several clusters of conventional computers, PlayStation~3 clusters, computers with powerful graphics cards and FPGAs. We also give /preseestimates for an ASIC design. In particular we present * our choice and analysis of the iteration function for the rho method; * our choice of finite field arithmetic and representation; * detailed descriptions of the implementations on a multitude of platforms: CPUs, Cells, GPUs, FPGAs, and ASICs; * details about running the attack. },
	keywords = {Attacks, automorphisms, binary fields, Certicom challenges, DLP, ECC, implementation, Koblitz curves, parallelized Pollard rho},
	url = {http://eprint.iacr.org/2009/541},
	author = {Bailey, Daniel V. and Batina, Lejla and Bernstein, Daniel J. and Birkner, Peter and Bos, Joppe W. and Chen, Hsieh - Chung and Cheng, Chen - Mou and van Damme, Gauthier and G{\"u}neysu, Tim and Gurkaynak, Frank and Kleinjung, Thorsten and Paar, Christof and Regazzoni, Francesco and Niederhagen, Ruben and Schwabe, Peter and Uhsadel, Leif and Van Herrewege, Anthony}
}
@conference {18084,
	title = {The Certicom Challenges ECC2-X},
	booktitle = {Workshop on Special Purpose Hardware for Attacking Cryptographic Systems (SHARCS)},
	year = {2009},
	month = {September},
	address = {Lausanne, Switzerland},
	author = {Bailey, Daniel V. and Baldwin, Brian and Batina, Lejla and Bernstein, Daniel J. and Birkner, Peter and Bos, Joppe W. and van Damme, Gauthier and de Meulenaer, Giacomo and Fan, Junfeng and Gurkaynak, Frank and G{\"u}neys, Tim and Kleinjung, Thorsten and Lange, Tanja and Mentens, Nele and Paar, Christof and Regazzoni, Francesco and Schwabe, Peter and Uhsadel, Leif}
}
@article {94.DeFeTa08,
	title = {Coordinated management of hardware and software self-adaptivity},
	journal = {Journal of Systems Architecture},
	volume = {55},
	number = {{3}},
	issue = {3},
	year = {2009},
	note = {{Challenges in self-adaptive computing (Selected papers from the Aether-Morpheus 2007 workshop), Accepted Manuscript, Available online 29 July 2008}},
	month = {03/2009},
	pages = {170 - 179},
	abstract = {Self-adaptivity is the capability of a system to adapt itself dynamically to achieve its goals. Self-adaptive systems will be widely used in the future both to efficiently use system resources and to ease the management of complex systems. The frameworks for self-adaptivity developed so far usually concentrate either on self-adaptive software or on self-adaptive hardware, but not both. In this paper, we propose a model of self-adaptive systems and we describe how to manage self-adaptivity at all levels (both hardware and software) by means of a decentralized control algorithm. The key advantage of decentralized control is in the simplicity of the local controllers. Simulation results are provided to show the main characteristics of the model and to discuss it.},
	keywords = {application, architecture, autonomic, goal, hardware, model, reconfigurable, run-time environment, self-adaptivity, software},
	issn = {1383-7621},
	doi = {http://dx.doi.org/10.1016/j.sysarc.2008.07.002},
	author = {Derin, Onur and Ferrante, Alberto and Taddeo, Antonio Vincenzo}
}
@conference {106.BoSa09,
	title = {Creating an Embedded Systems Program from Scratch: Nine years of experience at ALaRI},
	booktitle = {Proceedings of the 2009 Workshop on Embedded System Education},
	year = {2009},
	month = {October},
	address = {Grenoble, France},
	abstract = {In 1999, experts form academia and industry met in a workshop dealing with education in Embedded Systems Design: at the time there were no specifically oriented programs, and an {\textquoteright}ideal{\textquoteright} educational track was designed. One year later, that educational design was implemented with a one-year {\textquoteright}executive-type{\textquoteright} Master at Universit{\`a} della Svizzera italiana, in Switzerland; over the years, the program blossomed and extended, with development of a two-year Master of Science program as well. The experience is discussed here; results and perspectives are analyzed.},
	keywords = {education, embedded systems},
	doi = {http://dx.doi.org/10.1145/1719010.1719012},
	author = {Bondi, Umberto and Sami, Mariagiovanna}
}
@inbook {18085,
	title = {A Design Flow and Evaluation Framework for DPA-resistant Instruction Set Extensions},
	booktitle = {Cryptographic Hardware and Embedded Systems (CHES)},
	series = {Lecture Notes in Computer Science},
	volume = {5747},
	year = {2009},
	month = {September},
	pages = {205-219},
	publisher = {Springer Berlin Heidelberg},
	organization = {Springer Berlin Heidelberg},
	address = {Lausanne, Switzerland},
	abstract = {Power-based side channel attacks are a significant security risk, especially for embedded applications. To improve the security of such devices, protected logic styles have been proposed as an alternative to CMOS. However, they should only be used sparingly, since their area and power consumption are both significantly larger than for CMOS. We propose to augment a processor, realized in CMOS, with custom instruction set extensions, designed with security and performance as the primary objectives, that are realized in a protected logic. We have developed a design flow based on standard CAD tools that can automatically synthesize and place-and-route such hybrid designs. The flow is integrated into a simulation and evaluation environment to quantify the security achieved on a sound basis. Using MCML logic as a case study, we have explored different partitions of the PRESENT block cipher between protected and unprotected logic. This experiment illustrates the tradeoff between the type and amount of application-level functionality implemented in protected logic and the level of security achieved by the design. Our design approach and evaluation tools are generic and could be used to partition any algorithm using any protected logic style.},
	isbn = {978-3-642-04137-2},
	doi = {10.1007/978-3-642-04138-9_15},
	author = {Regazzoni, Francesco and Cevrero, Alessandro and Standaert, Fran{\c c}ois-Xavier and Badel, St{\'e}phane and Kluter, Theo and Brisk, Philip and Leblebici, Yusuf and Ienne, Paolo}
}
@conference {98.MaPaSiZa309,
	title = {A Design Space Exploration Methodology Supporting Run-Time Resource Management for Multi-Processors System on-Chip},
	booktitle = {Proceedings IEEE SASP{\textquoteright}09 - Symposium on Application Specific Processors},
	year = {2009},
	month = {July},
	address = {San Francisco, CA, USA},
	abstract = {Application Specific multi-processor Systems-on-chip are currently designed by using platform-based synthesis techniques. In this approach, a wide range of platform parameters are tuned either at design-time or at run-time, to provide the best trade-offs in terms of the selected system figures of merit (such as power and throughput) for a dynamic application-specific workload. Among the design-time (hardware) configurable parameters we can find the memory sub-system configuration (e.g. cache size and associativity) and other architectural parameters such as the instruction-level parallelism of the system processors. Among the run-time (software) configurable parameters we can find the overall degree of task-level parallelism associated with each application running on the chip. Typically, while the design-time exploration is performed in the early development stages for a set of static parameters, the tuning of the run-time parameters is performed dynamically by a run-time management software module after the system has been deployed. In this paper, we introduce a methodology for identifying a hardware configuration which is robust with respect to the variable workload scenario introduced by the run-time management. Moreover, the proposed methodology is aimed at providing useful information about the optimal software operating points of the applications in terms of task-level parallelism. The proposed methodology is based on the NSGA-II evolutionary heuristic algorithm assisted by an Artificial Neural Network (ANN). We then introduce a run-time management policy which is able to exploit the above information to maximize the performance of the system under power budget constraints. Experimental results show that the proposed technique is able to reduce the overall design space exploration time yet providing a near-optimal solution, in terms of hardware parameters, to enable an innovative and efficient run-time anagement policy.},
	keywords = {artificial neural network, design space exploration, meta-model assisted optimization, multi-objective optimization, multiprocessor system-on-chip (MPSoC), run-time resource management},
	doi = {http://dx.doi.org/10.1109/SASP.2009.5226331},
	author = {Mariani, Giovanni and Palermo, Gianluca and Silvano, Cristina and Zaccaria, Vittorio}
}
@conference {77.MaToFi08,
	title = {Design Space Exploration of PISA Architecture For ONU Auto-discovery Process},
	booktitle = {proceedings of 6th International Conference of Electrical Engineering (ICEENG)},
	year = {2009},
	month = {May 27-29},
	address = {Cairo, Egypt},
	abstract = {The goal of the paper is to optimize the PISA architecture for the ONU Auto-discovery process. This Auto-discovery process has been written in C language following the IEEE 802.3ah MPCP standard. Using SimpleScalar [3] simulation tool, the architecture profile is evaluated in order to decide the range of the design exploration. Then, using Wattch [1] and CACTI [2] simulation tools the CPI, average power consumed and cache area are calculated for each design point, the cost function is defined and evaluated for each design point using greedy strategy. The Auto-discovery process has been written in VHDL and using Synopys power compiler [4] the power consumption has been calculated and then we compared between the VHDL implementation and the PISA architecture from the power consumption point of view.},
	keywords = {design space exploration},
	doi = {http://dx.doi.org/10.1109/ICNM.2009.4907186},
	author = {Mady, Alie El-Din and Tonini, Andrea and Finardi, Davide}
}
@article {108.DeFe09.3,
	title = {Enabling Self-adaptivity in Component-based Streaming Applications},
	journal = {ACM SIGBED Review - Special Issue on the 2nd International Workshop on Adaptive and Reconfigurable Embedded Systems},
	volume = {6},
	number = {{3}},
	year = {2009},
	note = {Special Issue on the 2nd International Workshop on Adaptive and Reconfigurable Embedded Systems (APRES{\textquoteright}09)},
	month = {10/2009},
	pages = {14:1-14:4},
	publisher = {ACM SIGBED},
	abstract = {Self-adaptivity is the capability of a system to adapt itself dynamically to achieve its goals. By means of this mechanism the system is able to autonomously modify its behavior or the way in which applications are run and implemented to achieve the goals set.In this paper we propose a framework that uses a component-based approach to implement self-adaptivity at application level. By using this mechanism, the framework provides the ability to perform both adaptation on the structure of the application (i.e., how the components are connected together) and on internal parameters of each component. At application level, there is a mechanism to monitor different parameters and to check whether the system is meeting the assigned goals or not. A controller drives adaptations when goals are not met.},
	keywords = {component-based design, self-adaptive systems},
	issn = {1551-3688},
	doi = {http://dx.doi.org/10.1145/1851340.1851356},
	author = {Derin, Onur and Ferrante, Alberto}
}
@article {18064,
	title = {Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology},
	journal = {Springer Transactions on Computational Science},
	volume = {5430},
	year = {2009},
	month = {February},
	pages = {230{\textendash}243},
	author = {Regazzoni, Francesco and Eisenbarth, Thomas and Poschmann, Axel and Groschdl, Johann and Gurkaynak, Frank and Macchetti, Marco and Toprak, Zeynep and Pozzi, Laura and Paar, Christof and Leblebici, Yusuf and Ienne, Paolo}
}
@conference {102.LuKaMuBo09,
	title = {Functional requirements of embedded systems for monitoring and control structure of Virtual Power Plants},
	booktitle = {Proceedings of the 2009 IEEE Workshop on Environmental, Energy, and Structural Monitoring Systems},
	year = {2009},
	month = {September},
	address = {Crema, Italy},
	abstract = {Efficient integration of distributed renewable generation into a reliable single entity in technical and commercial terms is one of key issues for successful realization of smart-grids. The novel concept of Virtual Power Plants (VPP) emerges to be promising response to these needs. ICT is the enabling technology for VPP implementation. In fact, an efficient monitoring and control system coupled with appropriate communication structure must be designed in a scalable and modular way so that full interoperability among components of the system is achieved. On top of that, Control Center applications take care of power flow optimization (production, consumption, ancillary services) and high-level applications (e.g. energy trading, Demand Side Management etc.). In this work we focus on functional requirements for realization of such concept by means of embedded systems.},
	keywords = {monitoring and control, system level modeling, virtual power plants},
	doi = {http://dx.doi.org/10.1109/EESMS.2009.5341320},
	author = {Lukovi{\'c}, Slobodan and Kaitovi{\'c}, Igor and Mura, Marcello and Bondi, Umberto}
}
@inbook {17765,
	title = {IPSec Database Query Acceleration},
	booktitle = {E-business and Telecommunications},
	series = {Communications in Computer and Information Science},
	volume = {23},
	year = {2009},
	pages = {188-200},
	publisher = {Springer Berlin Heidelberg},
	organization = {Springer Berlin Heidelberg},
	isbn = {978-3-540-88652-5},
	doi = {10.1007/978-3-540-88653-2_14},
	url = {http://dx.doi.org/10.1007/978-3-540-88653-2_14},
	author = {Ferrante, Alberto and Chandra, Satish and Piuri, Vincenzo},
	editor = {Filipe, Joaquim and Obaidat, Mohammad}
}
@conference {101.MaPaSiZa209,
	title = {Meta-model Assisted Optimization for Design Space Exploration of Multi-Processor Systems-on-Chip},
	booktitle = {Euromicro Proceedings of DSD{\textquoteright}09 - Conference on Digital System Design},
	year = {2009},
	month = {August},
	address = {Patras, Greece},
	abstract = {Multi-processor Systems-on-chip are currently designed by using platform-based synthesis techniques. In this approach, a wide range of platform parameters are tuned to find the best trade-offs in terms of the selected system figures of merit (such as energy, delay and area). This optimization phase is called Design Space Exploration (DSE) and it generally consists of a Multi-Objective Optimization (MOO) problem. The design space of a Multi-processor architecture is too large to e evaluated comprehensively. So far, several heuristic techniques have been proposed to address the MOO problem, but they are haracterized by low efficiency to identify the Pareto front. In this paper, we address the MPSoC DSE problem by using an NSGA-II modified to be assisted by an Artificial Neural Network (ANN). In particular we exploit statistical methods to compute the prediction confidence intervals for the ANN approximations. These information are adopted in the evolution control strategy in order to carefully select which individuals should be simulated. Experimental results show that the proposed techniques is able to reduce the simulations needed for the optimization without decreasing the quality of the obtained Pareto Front. Results are compared with state of the art techniques to demonstrate that optimization time due to simulation can be speed up by adopting statistical methods during evolution control.},
	keywords = {artificial neural network, meta-model assisted optimization, multi-objective optimization, multiprocessor system-on-chip (MPSoC)},
	doi = {http://dx.doi.org/10.1109/DSD.2009.154},
	author = {Mariani, Giovanni and Palermo, Gianluca and Silvano, Cristina and Zaccaria, Vittorio}
}
@conference {95.FiPaSi09,
	title = {MPSoCs Run-Time Monitoring through Networks-on-Chip},
	booktitle = {The 2009 Conference on Design, Automation and Test In Europe (DATE{\textquoteright}09)},
	year = {2009},
	month = {April/2009},
	address = {Nice, France},
	abstract = {Networks-on-Chip (NoCs) have appeared as design strategy to overcome the limitations, in terms of scalability, efficiency, and power consumption of current buses. In this paper, we discuss the idea of using NoCs to monitor system behaviour at run-time by tracing activities at initiators and targets. Main goal of the monitoring system is to retrieve information useful for run-time optimization and resources allocation in adaptive systems. Information detected by probes embedded within NIs is sent to a central unit, in charge of collecting and elaborating the data. We detail the design of the basic blocks and analyse the overhead associated with the ASIC implementation of the monitoring system, as well as discussing implications in terms of the additional traffic generated in the NoC.},
	keywords = {monitoring, network-on-chip (NoC)},
	author = {Fiorin, Leandro and Palermo, Gianluca and Silvano, Cristina}
}
@conference {96.MaPaSiZa09.2,
	title = {Multicube Explorer - A Design Space Exploration Framework for Embedded Systems-on-Chip},
	booktitle = {Proceedings of the DATE{\textquoteright}09 workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications},
	year = {2009},
	month = {April},
	address = {Nice, France},
	abstract = {Multicube Explorer is a design space exploration tool for supporting platform-based design. It allows a fast optimization of parameterized system architecture towards a set of objective functions (e.g., energy, delay and area), by interacting with a system-level simulator. Multicube Explorer provides a set of innovative sampling and optimization techniques to help finding the best objective function trade-offs. It also provides an open XML interface for supporting new platforms/architectures.},
	keywords = {area, delay, energy, fast optimization, multicube explorer, optimization techniques, platform-based design, system-level simulator, XML},
	author = {Mariani, Giovanni and Palermo, Gianluca and Silvano, Cristina and Zaccaria, Vittorio}
}
@conference {97.Silvanoetal09,
	title = {MULTICUBE: Multi-Objective Design Space Exploration of Multiprocessor Architectures for Embedded Multimedia Applications},
	booktitle = {Proceedings of the DATE{\textquoteright}09 workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications},
	year = {2009},
	month = {April},
	address = {Nice, France},
	author = {Silvano, Cristina and Palermo, Gianluca and Zaccaria, Vittorio and Fornaciari, William and Zafalon, Roberto and Bocchio, Sara and Martinez, Marcos and Wouters, Maryse and Vanmeerbeeck, Geert and Avasare, Prabhat and Onesti, Luka and Kavka, Carlos and Bondi, Umberto and Mariani, Giovanni and Villar, Eugenio and Posadas, Hector and Wu, Chris and Dongrui, Fan and Hao, Zhang}
}
@conference {99.MaPaSiZa09,
	title = {Multiprocessor System-on-Chip Design Space Exploration based on Multi-level Modeling Techniques},
	booktitle = {Proceedings of IEEE IC-SAMOS{\textquoteright}09 - International Conference on Embedded Computer Systems: Architectures, MOdeling, and Simulation},
	year = {2009},
	month = {July},
	address = {Samos, Greece},
	abstract = {Multi-processor Systems-on-chip are currently designed by using platform-based synthesis techniques. In this approach, a wide range of platform parameters are tuned to find the best trade-offs in terms of the selected system figures of erit (such as energy, delay and area). This optimization phase is called Design Space Exploration (DSE) and it generally consists of a Multi-Objective Optimization (MOO) problem. The design space of a Multi-processor architecture is too large to be evaluated comprehensively. So far, several heuristic techniques have been proposed to address the MOO problem, but they are haracterized by low efficiency to identify the Pareto set. In this paper we propose a methodology for heuristic platform based design based on evolutionary algorithms and multi-level simulation techniques. In particular, we extend the NSGA-II with an approximate neural network meta-model for multi-processor architectures in order to replace expensive platform simulations with fast meta-model evaluation. The model accuracy and efficiency is improved by exploiting high-level platform simulation techniques. High-level simulation allows us to reduce the overall complexity of the neural network and improving its prediction power. Experimental results show that the proposed techniques is able to reduce the number of simulations needed for the optimization without decreasing the quality of the obtained Pareto set. Results are compared with state of the art echniques to demonstrate that optimization time due to simulation can be sped up by adopting multi-level simulation techniques.},
	keywords = {artificial neural network, design space exploration, genetic algorithm, multi level modelling, multiprocessor system-on-chip (MPSoC), platform-based design},
	doi = {http://dx.doi.org/10.1109/ICSAMOS.2009.5289222},
	author = {Mariani, Giovanni and Palermo, Gianluca and Silvano, Cristina and Zaccaria, Vittorio}
}
@conference {109.TaMaFe09,
	title = {Negotiation of Security Services: a Multi-criteria Decision Approach},
	booktitle = {Proceedings of the 4th Workshop on Embedded Systems Security},
	year = {2009},
	month = {October},
	address = {Grenoble, France},
	abstract = {Presently, one of the most important challenges in securing communications between resource-constrained mobile systems is the optimization of the trade-off between energy and performance of security services. Any adopted security solution should be able to negotiate the best security services in a dynamic and energy efficient way. In this paper, we propose an energy-aware adaptive protocol to negotiate security settings for communications. The protocol is based on a multi-criteria selection mechanism which provides the most profitable services related to nodes requirements and available resources.},
	keywords = {analytic hierarchy process (AHP), multi-criteria decision, security, security service selection},
	doi = {http://dx.doi.org/10.1145/1631716.1631720},
	author = {Taddeo, Antonio Vincenzo and Marcon, Pierpaolo and Ferrante, Alberto}
}
@conference {17995,
	title = {NPART - node placement algorithm for realistic topologies in wireless multihop network simulation},
	booktitle = {Proceedings of the 2nd International Conference on Simulation Tools and Techniques},
	year = {2009},
	publisher = {ICST (Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering)},
	organization = {ICST (Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering)},
	address = {ICST, Brussels, Belgium, Belgium},
	keywords = {node placement, simulation, topology generation, wireless multihop networks},
	isbn = {978-963-9799-45-5},
	doi = {10.4108/ICST.SIMUTOOLS2009.5669},
	url = {http://dx.doi.org/10.4108/ICST.SIMUTOOLS2009.5669},
	author = {Milic, Bratislav and Malek, Miroslaw}
}
@conference {110.CoKuLu09,
	title = {Prediction of the type of heating with EnergyPlus program and fuzzy logic},
	booktitle = {40th International Congress on Heating, Refrigerating and Air-conditioning (KGH Congress)},
	year = {2009},
	month = {12/2009},
	address = {Belgrade, Serbia},
	abstract = {The purpose of this work is prediction of the type of heating for the next few days in an office building using EnergyPlus program for simulation and fuzzy logic for determination. In this matter a program that binds weather forecast, created simulation model in EnergyPlus of a five story building in Belgrade, simulation in EnergyPlus and fuzzy logic, and as a result program gives the type of heating which is the most economic to use for the particular day, was built. Everything is done in the way of most efficient and rational use of energy.},
	author = {{\v C}ongradac, Velimir and Kuli{\'c}, Filip and Lukovi{\'c}, Slobodan}
}
@Patent {87.pat07301411.0-2413PATENT,
	title = {Programmable data protection device, secure programming manager system and process for controlling access to an interconnect network for an integrated circuit},
	number = {EP 20070301411},
	year = {2009},
	month = {04/2009},
	type = {Application},
	chapter = {EP 2043324 A1},
	abstract = {A data protection device for an interconnect network on chip (NoC) includes a header encoder that receives input requests for generating network packets. The encoder routes the input requests to a destination address. An access control unit controls and allows access to the destination address. The access control unit uses a memory to store access rules for controlling access to the network as a function of the destination address and of a source of the input request.},
	issn = {EP 2043324 A1},
	author = {Fiorin, Leandro and Palermo, Gianluca and Silvano, Cristina and Catalano, Valerio and Locatelli, Riccardo and Coppola, Marcello}
}
@conference {104.UpCaMaMaPo09,
	title = {Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering},
	booktitle = {Proceedings of the 19th international workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2009)},
	year = {2009},
	month = {September 9-11},
	address = {Delft, The Netherlands},
	abstract = {Clock-gating and power-gating have proven to be two of the most effective techniques for reducing dynamic and leakage power, respectively, in VLSI CMOS circuits. Most commercial synthesis tools do support such techniques individually, but their combined implementation is not available, since some open issues in terms of power/timing overhead associated to the control logic required for the integration are not yet solved. Moving from some recent work targeting clock-gating/power-gating integration, in this paper we present a solution for reducing the timing overhead that may occur when the integration is performed. In particular, we introduce a new, multilevel partitioning heuristic that increases the efficiency of the clustering phase, one of the key steps of our methodology. The results demonstrate the effectiveness of our solution; in fact, power-delay product and timing overhead of the circuits synthesized using the new clustering algorithm improve by 33\% and 24\%, respectively.},
	author = {Upasani, Gaurang and Calimera, Andrea and Macii, Alberto and Macii, Enrico and Poncino, Massimo}
}
@conference {107.TaFe209,
	title = {Run-time Selection of Security Algorithms For Networked Devices},
	booktitle = {5th ACM International Symposium on QoS and Security for Wireless and Mobile Networks},
	year = {2009},
	address = {Tenerife, Canary Islands, Spain},
	abstract = {One of the most important challenges that need to be currently faced in securing resource-constrained embedded systems is optimizing the trade-off between resources used (energy consumption and computational capabilities required) and security requirements for cryptographic algorithms: any adopted security solutions should guarantee an adequate level of protection, yet respecting constraints on computational resources and consumed power. These constraints are given by the kind of system considered and by the foreseen applications. In this paper, a generic, efficient, and energy-aware mechanism is proposed to face the problem of determining a correct trade off between security requirements and resources consumed. The solution proposed relies on Analytic Hierarchy Process (AHP) to define priorities among different requirements and to compare different security solutions. A knapsack problem is formulated to select the most relevant algorithms based on their utility and on available resources.},
	keywords = {adaptive systems, algorithm selection, protocol, quality of service (QoS), security},
	doi = {http://dx.doi.org/10.1145/1641944.1641963},
	author = {Taddeo, Antonio Vincenzo and Ferrante, Alberto}
}
@inbook {92.FiPaSi09.2,
	title = {Security in NoC},
	booktitle = {Networks-on-Chips: Theory and Practice},
	year = {2009},
	pages = {157-194},
	publisher = {Taylor and Francis Group, LLC - CRC Press},
	organization = {Taylor and Francis Group, LLC - CRC Press},
	abstract = {Future integrated systems will contain billion of transistors, composing tens to hundreds of IP cores. These IP cores, implementing emerging complex multimedia and network ap- plications, should be able to deliver rich multimedia and networking services. An efficient cooperation among these IP cores (e.g., efficient data transfers) can be achieved through utilization of the available resources. The design of such complex systems includes several challenges to be addressed. Among others one challenge is to design an on-chip interconnection network that should be able to efficiently connect the IP cores. Another challenge is to derive such an application mapping that will make efficient usage of the available hardware resources . An architecture that is able to accommodate such a high number of cores, satisfying the need for commu- nication and data transfers, is the Network-on-Chip (NoC) architecture. For these reasons Networks-on-Chip become a popular choice for designing the on-chip interconnect for Systems-on-Chip (MPSoCs), and are supported from the industry (such as the Ethereal NoC from Philips, the STNoC from STMicroelectronics and an 80-core NoC from Intel). As it is presented in , the key design challenges of emerging NoC design are a) the communication infrastructure, b) the communication paradigm selection and c) the application mapping optimization.},
	keywords = {network-on-chip (NoC), security},
	author = {Fiorin, Leandro and Palermo, Gianluca and Silvano, Cristina and Elmiligi, Haytham},
	editor = {Gebali, Fayez and El-Kharashi, Watheq}
}
@conference {17769,
	title = {A Security Service Protocol for MANETs},
	booktitle = {Consumer Communications and Networking Conference. CCNC 2009},
	year = {2009},
	month = {01/2009},
	publisher = {IEEE},
	organization = {IEEE},
	address = {in Las Vegas, Nevada, USA},
	abstract = {Mobile ad-hoc networks are composed of heterogeneous mobile systems. Securing their communications may be difficult due to differences in the supported algorithms and protocols. In this paper we propose a protocol to negotiate security settings for the communications. This protocol aims at minimizing the power consumption and at providing the highest possible security level associated with the communications.},
	keywords = {ad hoc networks, communication system security, data security, decision support systems, energy consumption, hardware, heterogeneous mobile systems, MANET, mobile ad-hoc networks, mobile communication, mobile radio, power consumption, power system security, protocol, quality of service (QoS), routing protocols, security service protocol, telecommunication security},
	doi = {10.1109/CCNC.2009.4784782},
	author = {Taddeo, Antonio Vincenzo and Ferrante, Alberto}
}
@conference {103.MuMuPr09,
	title = {Semi-Automated HW/SW Co-design for Embedded Systems: from MARTE Models to SystemC Simulators},
	booktitle = {FDL{\textquoteright}09 Proceedings},
	year = {2009},
	month = {September 22-24},
	address = {Sophia-Antipolis, France},
	abstract = {Although MDE and Hw/Sw Co-design are widely used to address the design complexity problem, the lack of design procedures and methodologies joining both concepts restrains their usage as complementary techniques, thus preventing the implementation of faster and more robust design cycles. In this paper we present a practical semi-automated design flow where both methodologies are merged and exploited to enable a fast design process targeting highly complex Real-Time Embedded Systems, executing several tasks on SoC and MPSoC devices, while allowing the usage of Design Space Exploration, Schedulability Analysis and Estimation techniques.},
	author = {Murillo, Luis Gabriel and Mura, Marcello and Prevostini, Mauro}
}
@conference {100.DeFe09,
	title = {Simulation of a Self-adaptive Run-time Environment with Hardware and Software Components},
	booktitle = {SINTER {\textquoteright}09: Proceedings of the 2009 ESEC/FSE workshop on Software integration and evolution @ runtime},
	year = {2009},
	month = {August},
	pages = {37{\textendash}40},
	publisher = {ACM},
	organization = {ACM},
	address = {Amsterdam, The Netherlands},
	abstract = {In this paper we describe a new way for simulating self-adaptive systems developed by relying on a component-based approach, this approach proves to be useful both in easing self-adaptivity and in providing the ability to mix hardware and software elements. Our simulation method is based on SACRE (Self-Adaptive Component Run-time Environment), a framework we have defined in Java for simulating self-adaptive systems.},
	keywords = {component-based design, HW/SW co-design, self-adaptive systems, simulation},
	isbn = {978-1-60558-681-6},
	doi = {http://doi.acm.org/10.1145/1596495.1596507},
	author = {Derin, Onur and Ferrante, Alberto}
}
@conference {111.ChPaSiZa10,
	title = {Yield Enhancement by Robust Application-specific Mapping on Network-on-Chips},
	booktitle = {NoCArc{\textquoteright}09: Proceedings of the Second International Workshop on Network on-Chip Architectures},
	year = {2009},
	month = {December},
	pages = {37{\textendash}42},
	address = {New York City, USA},
	abstract = {The current technological defect densities and production yields are a motivating factor supporting the introduction of design-for-manufacturability techniques during the highlevel design of complex, embedded systems based on networkon- chips (NoCs). In this context, we tackle the problem of mapping the IPs of a multi-processing system to the NoC nodes, by taking into account the effective robustness of the system with respect to permanent faults in the interconnection network due to manufacturing defects. In particular, we introduce an application specific methodology for identifying optimal NoCs mappings which minimize the variance of the system power and latency and maximizes the probability that the actual system will work when deployed, even in presence of faulty NoC links. We provide experimental results by comparing the proposed methodology with conventional mapping approaches, by highlighting benefits and drawbacks of both techniques},
	author = {Choudhury, Anirban Dutta and Palermo, Gianluca and Silvano, Cristina and Zaccaria, Vittorio}
}
@conference {82.BeBrFaRe08,
	title = {A 640 Mbit/s 32-bit Pipelined Implementation of the AES Algorithm},
	booktitle = {SECRYPT},
	year = {2008},
	month = {July 26},
	address = {Porto, Portugal},
	abstract = {Due to the diffusion of cryptography in real time applications, performances in cipher and decipher operations are nowadays more important than in the past. On the other side, while facing the problem for embedded systems, additional constraints of area and power consumption must be considered. Many optimized software implementations, instruction set extensions and co-processors, were studied in the past with the aim to either increase performances or to keep the cost low. This paper presents a co-processor that aims to be an intermediate solution, suitable for such applications that require a throughput in the Megabit range and where the die size is a bit relaxed as constraint. To achieve this goal, the core is designed to operate at 32 bits and the throughput is guaranteed by a 2 stage pipeline with data forwarding. The obtained results synthesizing our coprocessor by means of the CMOS $0.18$ $μ$m standard cell library show that the throughput reaches 640 Mbit/s while the circuit size is of only 20 K equivalent gates. },
	keywords = {cryptography, security},
	author = {Bertoni, Guido Marco and Breveglieri, Luca and Farina, Roberto and Regazzoni, Francesco}
}
@conference {75.BoPaSa08,
	title = {An adaptable FPGA-based System for Regular Expression Matching},
	booktitle = {Proceedings of Design, Automation and Test in Europe (DATE) Conference},
	year = {2008},
	month = {March 10-14},
	address = {Munich, Germany},
	abstract = {In many applications string pattern matching is one of the most intensive tasks in terms of computation time and memory accesses. Network Intrusion Detection Systems and DNA Sequence Matching are two examples. Since software solutions are not able to satisfy the performance requirements, specialized hardware architectures are required. In this paper we propose a complete framework for regular expression matching, both in its architecture and compiler. This special-purpose processor is programmed using regular expressions as programming language. With the parallelism exploited in the design it is possible to achieve a throughput greater than one character per clock cycle, requiring O(n) memory space. The VHDL description of the proposed architecture is fully configurable. A design space exploration to find the optimal architecture based on area and performance cost-function is presented.},
	keywords = {FPGA-based design, regular expression matching},
	doi = {http://dx.doi.org/10.1109/DATE.2008.4484852},
	author = {Bonesana, Ivano and Paolieri, Marco and Santambrogio, Marco Domenico}
}
@conference {80.LuFi08,
	title = {An Automated Design Flow for NoC-based MPSoCs on FPGA},
	booktitle = {RSP 2008, The 19th IEEE/IFIP International Symposium on Rapid System Prototyping},
	year = {2008},
	month = {June 2-5},
	address = {Monterey, USA/CA},
	abstract = {Increased dynamics of the embedded devices market makes reduced time-to-market emerge as one of most challenging tasks in modern embedded system design. The complexity of Multiprocessor Systems-on-Chip (MPSoCs) rapidly increases and Networks-on-Chips (NoCs) have emerged as design strategy to cope with it. In order to allow fast generation of these platforms in the development phase, a full design flow is required. On the other hand, modern FPGAs provide the possibility for fast and low-cost prototyping, representing an efficient response to these needs. In this paper we present a framework, based on the Xilinx Embedded Development Kit (EDK) design flow, for the generation of MPSoCs based on NoCs. The tool provides system designers with the possibility to easily and quickly generate desired architectures that can be helpful for testing, debugging and verifying purposes. Our integrated design flow takes as input a textual description of the system and produces as final result a configuration bitstream file. The framework has been tested and verified on a Xilinx Virtex-II Pro board.},
	keywords = {FPGA, multiprocessor system-on-chip (MPSoC), network-on-chip (NoC), reconfigurable systems, security},
	doi = {http://dx.doi.org/10.1109/RSP.2008.31},
	author = {Lukovi{\'c}, Slobodan and Fiorin, Leandro}
}
@conference {89.ReEiBrIeKo,
	title = {Can knowledge regarding the presence of countermeasures against fault attacks simplify power attacks on cryptographic devices?},
	booktitle = {Proceedings of 23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS 08)},
	year = {2008},
	month = {October 1-3},
	abstract = {Side-channel attacks are nowadays a serious concern when implementing cryptographic algorithms. Powerful ways for gaining information about the secret key as well as various countermeasures against such attacks have been recently developed. Although it is well known that such attacks can exploit information leaked from different sources, most prior works have only addressed the problem of protecting a cryptographic device against a single type of attack. Consequently, there is very little knowledge on how a scheme for protecting a device against one type of side-channel attack may affect its vulnerability to other types of side-channel attacks. In this paper we focus on devices that include protection against fault injection attacks (using different error detection schemes) and explore whether the presence of such fault detection circuits affects the resistance against attacks based on power analysis. Using the AES S-Box as an example, we performed attacks on the unprotected implementation as well as modified implementations with parity check circuits or residue check circuits (mod3 and mod7). In particular, we focus on the question whether the knowledge of the presence of error detection circuitry in the cryptographic device can help an attacker who attempts to mount a power attack on the device. Our results show that the presence of error detection circuitry helps the attacker even if he is unaware of this circuitry, and that the benefit to the attacker increases with the number of check bits used for the purpose of error detection.},
	author = {Regazzoni, Francesco and Eisenbarth, Thomas and Breveglieri, Luca and Ienne, Paolo and Koren, Israel}
}
@conference {85.MuSaParma08,
	title = {Code Generation from Statecharts: Simulation of Wireless Sensor Networks},
	booktitle = {Proceedings of DSD08},
	year = {2008},
	month = {September},
	address = {Parma, Italy},
	abstract = {Automatic generation of code starting from lightweight modeling languages such as UML is by now a widely adopted approach. In particular generation of executable SystemC models starting from StateCharts and other UML diagrams represents a promising research field. While RTL SystemC appears better suited for matching the StateCharts formalism (being intrinsically clocked), performances of the generated code suffer from the heavy overhead induced by time management, specially when the number of concurrent processes is high. In this paper we present a methodology that allows applying a solution mixing event based and clock-driven approach. More specifically, clock-driven simulation is activated only when the configuration of the system is identified to be evolving. When no events are present this fact is also detected (together with the interval of absence of events) so that no simulation is performed although the clock runs on. This solution is particularly suited for low duty cycle systems, as, e.g. when simulating Wireless Sensor Networks (WSN); in such instances, speedup of the generated code has been found to be well over two orders of magnitude. Application of the technique to the generation of a power simulator for the IEEE 802.15.4 networking protocol is used as a test case.},
	keywords = {low power design, modeling, protocol, wireless sensor networks},
	doi = {http://dx.doi.org/10.1109/DSD.2008.106},
	author = {Mura, Marcello and Sami, Mariagiovanna}
}
@conference {90.MaPaZaSi08,
	title = {An Efficient Design Space Exploration Methodology for Multi-Cluster VLIW Architectures based on Artificial Neural Networks},
	booktitle = {Proc. IFIP International Conference on Very Large Scale Integration VLSI - SoC 2008},
	year = {2008},
	month = {October 13-15},
	address = {Rhodes Island, Greece},
	abstract = {Multi-Cluster Very Long Instruction Word (VLIW) architectures are currently designed by using platform-based synthesis techniques. In these approaches, a wide range of platform parameters is tuned to find the best trade-offs in terms of the selected figures of merit (such as energy, delay and area). This optimization phase is called Design Space Exploration (DSE) and it generally consists of a Multi-Objective Optimization (MOO) problem. The design space for a Multi-Cluster architecture is too large to be evaluated comprehensively. So far, several heuristic techniques have been proposed to address the MOO problem, but they are characterized by low efficiency to identify the Pareto front. In this paper, we propose an efficient DSE methodology leveraging neural networks. In particular, an initial design-of-experiments phase is used for generating a coarse view of the target design space; neural networks are then trained and used to refine the exploration, by identifying efficiently the Pareto points of the design space. This process is iteratively repeated until the target criterion (convergence of the Pareto coverage) is satisfied. A set of experimental results are reported to trade-off accuracy and efficiency of the proposed techniques with actual workloads.},
	keywords = {design space exploration, multi-objective optimization, neural networks, response surface, system-on-chip (SoC), very long instruction words (VLIW)},
	author = {Mariani, Giovanni and Palermo, Gianluca and Zaccaria, Vittorio and Silvano, Cristina}
}
@conference {81.sliceb08,
	title = {An Enhanced Service Provider Communication Interface with Client Priorization},
	booktitle = {proceedings of IEEE/WFMC International Conference on e-Business},
	year = {2008},
	month = {July 26-29},
	abstract = {With the increased dynamics of modern life, the efficiency and reliability of everyday services is emerging to be a fundamental concern. On the other hand, modern telecommunication technologies, like wireless Internet access, are penetrating all segments of our life. However, many every day activities and services still do not fully exploit new technologies. We propose an approach that enables increased deployment of E-commerce concepts in the fields where their usage was either small or negligible. Moreover, in the scope of the same concept, we introduce prioritization of clients in services where it was not commonly present to date. A solution for enhanced communication interface between service provider and customers is developed. As a case study, the system is designed and optimized for an implementation in a fast-food chain. The proposed solution is aiming at increasing of quality of service for customers, and at the same time increasing the operational efficiency of the provider. The main idea behind this approach is to enable customers to use their mobile devices, such as cell phones or PDAs, for browsing offered services or goods, viewing current service conditions and placing orders. We will detail mathematical model underneath and describe the implementation on both server and client side.},
	author = {Lukovi{\'c}, Slobodan and Puzovi{\'c}, Nikola and Stanisavljevi{\'c}, Milo{\v s}}
}
@conference {74.Munich,
	title = {Executable Models and Verification from MARTE and SysML: a Comparative Study of Code Generation Capabilities},
	booktitle = {Proceedings of MARTE Workshop (DATE08)},
	year = {2008},
	month = {March},
	address = {Munich, Germany},
	abstract = {In this paper two well known UML profiles, namely SysML and MARTE are closely examined and compared. Both profiles are well suited for the description of embedded systems, although focusing on different aspects and can therefore be considered as complementary. While SysML targets system engineering descriptions in a high level of abstraction and provide diagrams for requirements specification, MARTE is tailored for systems in which Real Time constraints play a major role. Expressiveness of such profiles and their matching with languages that represent the next step in the development of Hardware/Software systems will be the main subject of this work. A Wireless Sensor Network scenario is taken as a reference case study and used to illustrate a practical application of MDA.},
	keywords = {automatic generation of code, high level design, profiling, unified modeling language (UML)},
	author = {Mura, Marcello and Panda, Amrit and Prevostini, Mauro}
}
@Patent {78.pat20080134187PATENT,
	title = {Hardware scheduled SMP architectures},
	number = {US 11/947,278},
	year = {2008},
	month = {06/2008},
	type = {Application},
	chapter = {US 20080134187 A1},
	abstract = {A symmetric multiprocessor system employing a hardware constituted real-time operating system.},
	issn = {US 20080134187 A1},
	author = {Lajolo, Marcello and Nacul, Andre Costi and Regazzoni, Francesco}
}
@conference {76.FiLuPa08,
	title = {Implementation of a Reconfigurable Data Protection Module for NoC-based MPSoCs},
	booktitle = {Proceedings of the 21st IPDPS 2007 Reconfigurable Architecture Workshop (RAW), 21th IEEE International Parallel and Distributed Processing Symposium},
	year = {2008},
	month = {April},
	address = {Miami, USA/FL},
	abstract = {Security issues are emerging to be a basic concern in modern SoC development. Since in the field of on-chip interconnections the security problem continues to remain mostly an unexplored topic, this paper proposes a novel technique for data protection that uses the communication subsystem as basis. The proposed architecture works as a firewall managing the memory accesses on the basis of a lookup table containing the access rights. This module, called Data Protection Unit (DPU), has been designed for MPSoC architectures and integrated in the Network Interfaces near the shared memory. We implement the DPU inside an MPSoC architecture on FPGA and we add features to the module to be aware of dynamic reconfiguration of the system software. Starting from a general overview of our design down to components structure, we introduce the place and the role of the DPU module inside the system for a reconfigurable secure implementation of a MPSoC on FPGA. The description of the DPU concept, its implementation, and integration into the system are described in detail. Finally, the architecture is fully implemented on FPGA and tested on a Xilinx Virtex-II Pro board.},
	keywords = {data protection, FPGA, multiprocessor system-on-chip (MPSoC), network-on-chip (NoC), reconfigurable systems, security},
	doi = {http://dx.doi.org/10.1109/IPDPS.2008.4536514},
	author = {Fiorin, Leandro and Lukovi{\'c}, Slobodan and Palermo, Gianluca}
}
@conference {83.Stuttgart,
	title = {Model-based Design Space Exploration for RTES with SysML and MARTE},
	booktitle = {Proceedings of FDL08},
	year = {2008},
	month = {September},
	address = {Stuttgart, Germany},
	abstract = {The features of the emerging modeling languages for system design allow designers to build models of almost any kind of heterogeneous hardware-software systems, including Real Time Embedded Systems (RTES). An important goal to achieve is the implementation and use of these models in all the steps of a common design flow. One of these steps is the Design Space Exploration (DSE), which helps designers in discovering the optimal solutions among all possible combinations after mapping functional to architectural specifications; for RTES this step is particularly hard as it should include scheduling analysis in order to proof the time validity after the mapping. This paper presents some guidelines on how to use SysML and MARTE profiles to identify design points fulfilling the timing constraints of an RTES, and thus allowing to automatize DSE analysis within the system design phase.},
	keywords = {high level design, unified modeling language (UML)},
	doi = {http://dx.doi.org/10.1109/FDL.2008.4641446},
	author = {Mura, Marcello and Murillo, Luis Gabriel and Prevostini, Mauro}
}
@conference {79.Ptsbrg,
	title = {Modelling the Power Cost of Security in Wireless Sensor Networks : the Case of 802.15.4},
	booktitle = {Proceedings of IEEE ICT08},
	year = {2008},
	month = {June},
	address = {Saint Petersburg, Russia},
	abstract = {Pervasive applications and in particular Wireless Sensors Networks have very strict requirements in terms of power consumption. It is well known that radio activity is very expensive in terms of energy; we show here that intensive processing activities (as security) represent a major contribution to power budget. In this paper we extend our methodology for analyzing the impact of Security related operations on power consumption and optimizing it. The analysis is based on experimental data and was validated with measurements on a real platform.},
	keywords = {low power design, modeling, protocol, wireless sensor networks},
	doi = {http://dx.doi.org/10.1109/ICTEL.2008.4652616},
	author = {Mura, Marcello and Fabbri, Fabio and Sami, Mariagiovanna}
}
@conference {91.FePoStTa08,
	title = {A Protocol For Pervasive Distributed Computing Reliability},
	booktitle = {SecPri_WiMob 2008},
	year = {2008},
	month = {10/2008},
	publisher = {IEEE},
	organization = {IEEE},
	address = {Avignon, France},
	abstract = {The adoption of new hardware and software architectures will make future generations of pervasive devices more flexible and extensible. Networks of computational nodes will be used to compose such systems. In these networks tasks will be delegated dynamically to different nodes (that may be either general purpose or specialized). Thus, a mechanism to verify the reliability of the nodes is required, especially when nodes are allowed to move in different networks. In this context, the reliability of nodes is determined by their ability to execute the tasks assigned to them with the promised performances. This paper proposes a protocol to evaluate the reliability of the different nodes in the network, thus providing a trusting mechanism among nodes which can also manage the soft/hard real-time constrains of task execution. Some simulation results are also shown to help describing the properties of the protocol.},
	keywords = {protocol, quality of service (QoS), security, trusting},
	author = {Ferrante, Alberto and Pompei, Roberto and Stulova, Anastasia and Taddeo, Antonio Vincenzo}
}
@article {84.AlGaSte2008,
	title = {Secure Memory Accesses on Networks-on-Chip},
	journal = {IEEE Transactions on Computers},
	volume = {57},
	number = {9},
	year = {2008},
	month = {September},
	pages = {1216-1229},
	abstract = {Security is gaining relevance in the development of embedded devices. Towards a secure system at each level of design, this paper addresses security aspects related to Network on Chip (NoC) architectures, foreseen as the communication infrastructure of next-generation embedded devices. In the context of NoC-based multiprocessor systems, we focus on the topic, not yet thoroughly faced, of data protection. In this paper, we present a secure NoC architecture composed of a set of Data Protection Units (DPUs) implemented within the Network Interfaces (NIs)1. The run-time configuration of the programmable part of the DPUs is managed by a central unit, the Network Security Manager (NSM). The DPU, similar to a firewall, can check and limit the access rights (none, read, write, or both) of processors accessing data and instructions in a shared memory. In particular, the DPU can distinguish between the operating roles (supervisor/user and secure/non secure) of the processing elements.We explore alternative implementations of the DPU and demonstrate how this unit does not affect the network latency if the memory request has the appropriate rights. We also focus on the dynamic updating of the DPUs to support their utilization in dynamic environments, and on the utilization of authentication techniques to increase the level of security.},
	keywords = {data protection, embedded systems, multiprocessor system-on-chip (MPSoC), network-on-chip (NoC), security},
	doi = {http://dx.doi.org/10.1109/TC.2008.69},
	author = {Fiorin, Leandro and Palermo, Gianluca and Lukovi{\'c}, Slobodan and Catalano, Valerio and Silvano, Cristina}
}
@conference {88.FiPaSi08,
	title = {A Security Monitoring Service for NoCs},
	booktitle = {Sixth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS{\textquoteright}08)},
	year = {2008},
	month = {10/2008},
	address = {Atlanta, Georgia, USA.},
	abstract = {As computing and communications increasingly pervade our lives, security and protection of sensitive data and systems are emerging as extremely important issues. Networks-on- Chip (NoCs) have appeared as design strategy to cope with the rapid increase in complexity of Multiprocessor Systems- on-Chip (MPSoCs), but only recently research community have addressed security on NoC-based architectures. In this paper, we present a monitoring system for NoC based architectures, whose goal is to help detect security violations carried out against the system.Information col- lected are sent to a central unit for efficiently counteracting actions performed by attackers.We detail the design of the basic blocks and analyse overhead associated with the ASIC implementation of the monitoring system, discussing type of security threats that it can help detect and counteract.},
	keywords = {embedded systems, multiprocessor system-on-chip (MPSoC), network-on-chip (NoC), security},
	doi = {http://dx.doi.org/10.1145/1450135.1450180},
	author = {Fiorin, Leandro and Palermo, Gianluca and Silvano, Cristina}
}
@conference {61.PaMaSiLo07,
	title = {Application-Specific Topology Design Customization for STNoC},
	booktitle = {DSD07, in proceedings of 10th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD 07)},
	year = {2007},
	month = {August 29-31},
	address = {L{\"u}beck, Germany},
	abstract = {Customized network-oriented communication architectures have recently become a must to support high bandwidth SoCs. To this end, a corresponding communication design flow is necessary to support the design space exploration of complex SoCs with tight design constraints. In order to exploit the benefits introduced by the NoC approach for the on-chip communication, the paper presents a Pareto Simulated Annealing (PSA) approach for the customization of the network topology. The proposed PSA approach has been applied to STNoC, the Network on Chip developed by STMicroelectronics. Starting from the ring topology, the proposed application-specific design flow tries to find a set of customized topologies (optimized in terms of performance and area/energy overhead) by adding custom links up to the spidergon topology.},
	keywords = {application specific design, mapping, network-on-chip (NoC), STNoC, topology customization},
	doi = {http://dx.doi.org/10.1109/DSD.2007.4341522},
	author = {Palermo, Gianluca and Mariani, Giovanni and Silvano, Cristina and Locatelli, Riccardo and Coppola, Marcello}
}
@conference {48.Giaconia2007,
	title = {Area and Power Efficient Synthesis of DPA-Resistant Cryptographic SBoxes},
	booktitle = {International Conference on VLSI Design \& Embedded Systems},
	year = {2007},
	month = {January 6-10},
	address = {Bangalore, India},
	abstract = {This paper presents a novel design methodology for the hardware implementation of non-linear bijective functions, commonly used in most symmetric-key cryptographic algorithms and known as substitution boxes (S-boxes). The proposed technique thwarts a particularly relevant class of side-channel attacks against cryptographic hardware, that of differential power analysis attacks (DPA). In the proposed approach, the cost of the countermeasure is kept low in terms of silicon process overheads (standard CMOS gates used), area requirement, power consumption and latency, when compared to existing countermeasures. Its effectiveness is proven by showing resistance to simulated DPA attacks using power curves derived with SPICE simulation.},
	keywords = {differential power analysis (DPA), low power design, side channel attacks},
	doi = {http://dx.doi.org/10.1109/VLSID.2007.44},
	author = {Giaconia, Matteo and Macchetti, Marco and Regazzoni, Francesco and Schramm, Kai}
}
@conference {68.FiPaLuSi07,
	title = {A Data protection Unit for NoC-based Architecture},
	booktitle = {CODES+ISSS 2007, in proceedings of the Fifth IEEE/ACM/FIP International Conference of Hardware/Software Codesign and System Synthesis (CODES+ISSS 2007)},
	year = {2007},
	month = {September 30},
	address = {Salzburg, Austria},
	abstract = {Security is gaining increasing relevance in the development of embedded devices. Towards a secure system at each level of design, this paper addresses the security aspects related to Network-on-Chip (NoC) architectures, foreseen as the communication infrastructure of next generation embedded devices. In the context of NoC-based Multiprocessor systems, we focus on the topic, not thoroughly faced yet, of data protection. We present the architecture of a Data Protection Unit (DPU) designed for implementation within the Network Interface (NI). The DPU supports the capability to check and limit the access rights(none, read, write or both) of processors requesting access to data locations in a shared memory - in particular distinguishing between the operating roles (supervisor or user) of processing elements. We explore different alternative implementations and demonstrate how the DPU unit does not affect the network latency if the memory request has the appropriate rights. In the experimental section we show synthesis results for different ASIC implementations of the Data Protection Unit.},
	keywords = {data protection, embedded systems, multiprocessor system-on-chip (MPSoC), network-on-chip (NoC), security},
	doi = {http://dx.doi.org/10.1145/1289816.1289858},
	author = {Fiorin, Leandro and Palermo, Gianluca and Lukovi{\'c}, Slobodan and Silvano, Cristina}
}
@conference {72.Ferrari2007,
	title = {Design exploration for an Ogg/Vorbis decoder for VLIW architectures},
	booktitle = {Workshop on Application Specific Processors (WASP {\textquoteright}07)},
	year = {2007},
	month = {October},
	address = {Salzburg, Austria},
	abstract = {Parallel processing architectures are set to be the dominating design approach for a plethora of application domains, mainly because of the eminent reach of the so-called power wall, and furthermore because of the evident gap between the application/software development growth and Moore{\textquoteright}s law. In this work a design space for an audio codec is explored, targeted at a VLIW architecture. The Ogg/Vorbis codec is first analyzed and optimized for exposing potential parallelism to the VEX tools for compilation and parallel architecture exploration. Furthermore, the use of custom instructions is assessed and important results are obtained by means of a modification on the toolchain to reveal dynamic profiling information},
	author = {Ferrari, Federico and Amador, Erick}
}
@conference {53.CoReLa07,
	title = {HardwareScheduling Support in SMP Architecture},
	booktitle = {Design, Automation and Test in Europe(DATE)},
	year = {2007},
	month = {April 16-20},
	address = {Nice, France},
	abstract = {In this paper the authors propose a hardware real time operating system (HW-RTOS) that implements the OS layer in a dual-processor SMP architecture. Intertask communication is specified by means of dedicated APIs and the HW-RTOS takes care of the communication requirements of the application and also implements the task scheduling algorithm. The HW-RTOS allows to have smaller footprints, since it avoids the need to link to the final executables traditional software RTOS libraries. Moreover, the HW-RTOS is able to exploit the easy task migration feature provided by an SMP architecture much more efficiently than a traditional software RTOS, due to its faster execution and the authors show how this significantly overcomes the performance achievable with optimal static task partitioning among two processors. Preliminary results show that the hardware overhead in a dual processor architecture is less than 20K gates.},
	keywords = {HW/SW co-design, multiprocessor system-on-chip (MPSoC), real time operating systems},
	doi = {http://dx.doi.org/10.1109/DATE.2007.364666},
	author = {Nacul, Andre Costi and Regazzoni, Francesco and Lajolo, Marcello}
}
@conference {54.FePi07,
	title = {High-level Architecture of an IPSec-dedicated System on Chip},
	booktitle = {proceedings of NGI 2007},
	year = {2007},
	month = {May},
	publisher = {IEEE Press},
	organization = {IEEE Press},
	address = {Trondheim, Norway},
	abstract = {IPSec is a suite of protocols which adds security to communications at the IP level. Protocols within the IPSec suite make extensive use of cryptographic algorithms. Since these algorithms are computationally very intensive, some hardware acceleration is needed to support high throughput. In this paper we propose a high level architecture of a System on Chip (SoC) which implements IPSec. This SoC has been thought to be placed on the main data path of the host machine (flow-through architecture), thus allowing for transparent processing of IPSec traffic. The functionalities of the different blocks and their interactions, along with an estimation of the internal memory size, are also shown.},
	keywords = {accelerator, IPSec, priority, quality of service (QoS), security, system-on-chip (SoC), SystemC},
	author = {Ferrante, Alberto and Piuri, Vincenzo}
}
@misc {52.Prevo2007MISC,
	title = {Introduction to SysML},
	year = {2007},
	month = {April 20},
	abstract = {The Systems Modeling Language (SysML) is a general-purpose graphical modeling language for specifying, analyzing, designing, and verifying complex systems that may include hardware, software, information, personnel, procedures, and facilities. It is a response to the UML for Systems Engineering RFP developed by OMG, INCOSE, and the ISO AP233 workgroup. In this presentation I will provide an overview of SysML in particular by showing the diagrams that describe the four pillars of SysML: Requirements, Behavior, Structure, and Parametrics. The diagrams will be shown by means of a simple case study in the field of Wireless Sensor Network.},
	keywords = {embedded systems, systems modeling language (SysML), wireless sensor networks},
	author = {Prevostini, Mauro}
}
@conference {63.Der2007,
	title = {Learning Java by a Card Game: A Case Study},
	booktitle = {LG2007: Proceedings of Learning with Games Conference},
	year = {2007},
	month = {September 24-27},
	pages = {221{\textendash}228},
	address = {Sophia Antipolis, France},
	abstract = {To teach Java programming language better and in a more enjoyable way, we developed a framework for card games that allows students to write and test their own intelligent players. This paper briefly describes the design of the framework, the advantages of using it to assign homework and reports our experience with a class carried out in our institute.},
	keywords = {assignment, card games, case study, java, pedagogy},
	isbn = {978-88-901168-0-3},
	author = {Derin, Onur},
	editor = {Taisch, Marco and Cassina, Jacopo}
}
@conference {57.PaMaSiLoCo07,
	title = {Mapping and Topology Customization Approaches for Application-Specific STNoC Designs},
	booktitle = {IEEE Proceedings of ASAP{\textquoteright}07 - 18th International Conference on Application-specific Systems, Architectures and Processors},
	year = {2007},
	month = {July},
	address = {Montr{\'e}al, Qu{\'e}bec, Canada},
	abstract = {Application-specific network-oriented communication architectures have recently become an effective solution to support high bandwidth Systems on-Chip. The Network on-Chip architectures considered so far range from regular to fully customized topologies for application specific designs requiring high-level bandwidth. To this end, a networkcentric design flow is necessary to support the design space exploration of complex SoCs with tight design constraints. This paper introduces four different approaches based on the orthogonalization of core mapping and topology customization applied to STNoC, the Network on-Chip developed by STMicroelecronics. The four methods are derived from the combination of the initial mappings to two standard topologies (ring and spidergon) with two types of topology customization based on the insertion of cross-links to reduce the network distance of standard topologies},
	keywords = {application specific design, mapping, network-on-chip (NoC), STNoC, topology customization},
	doi = {http://dx.doi.org/10.1109/ASAP.2007.4429959},
	author = {Palermo, Gianluca and Mariani, Giovanni and Silvano, Cristina and Locatelli, Riccardo and Coppola, Marcello}
}
@conference {55.DaFeMa,
	title = {A Memory Unit for Priority Management in IPSec Accelerators},
	booktitle = {proceedings of ICC07. Glasgow, Scotland: IEEE Communications Society},
	year = {2007},
	month = {June 24},
	address = {Glasgow, Scotland},
	abstract = {This paper introduces a hardware architecture for high speed network processors, focusing on support for Quality of Service in IPSec-dedicated systems. The effort is aimed at defining a secure system on chip environment, where the speed and security requirements are of utmost importance. In particular, a method is devised to introduce and support Quality of Service through priorities at this level. An architecture of a memory system that provides automatic priority management is proposed.},
	keywords = {accelerator, IPSec, priority, quality of service (QoS), security, system-on-chip (SoC), SystemC},
	doi = {http://dx.doi.org/10.1109/ICC.2007.257},
	author = {Dadda, Luigi and Ferrante, Alberto and Macchetti, Marco}
}
@conference {47.ZaJoHa07,
	title = {The Potential of Speculative Class-Loading},
	booktitle = {PPPJ 2007: Proceedings of the Principles and Practice of Programming in Java},
	year = {2007},
	address = {Lisbon, Portugal},
	abstract = {Platforms such as Java provide many software engineering benefits. However, these benefits often come at the cost of significant runtime overhead. In this paper we study the potential for hiding some of that overhead by employing speculative execution techniques. In particular, we study the predictability of class-loading requests and the potential benefits of speculatively preloading classes in interactive applications.},
	keywords = {markov predictor, speculative class-loading},
	author = {Zaparanuks, Dmitrijs and Jovi{\'c}, Milan and Hauswirth, Matthias}
}
@conference {67.ReEiGr07,
	title = {Power Attacks Resistance of Cryptographic S-boxes with added Error Detection Circuits},
	booktitle = {proceedings of: {\textquoteright}22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT{\textquoteright}07)},
	year = {2007},
	month = {September 26-28},
	address = {Rome, Italy},
	abstract = {Many side-channel attacks on implementations of cryptographic algorithms have been developed in recent years demonstrating the ease of extracting the secret key. In response, various schemes to protect cryptographic devices against such attacks have been devised and some implemented in practice. Almost all of these protection schemes target an individual side-channel attack and consequently, it is not obvious whether a scheme for protecting the device against one type of side-channel attacks may make the device more vulnerable to another type of side-channel attacks. We examine in this paper the possibility of such a negative impact for the case where fault detection circuitry is added to a device (to protect it against fault injection attacks) and analyze the resistance of the modified device to power attacks. To simplify the analysis we focus on only one component in the cryptographic device (namely, the S-box in the AES and Kasumi ciphers), and perform power attacks on the original implementation and on a modified implementation with an added parity check circuit. Our results show that the presence of the parity check circuitry has a negative impact on the resistance of the device to power analysis attacks.},
	keywords = {cryptography, fault tolerance, reliable applications, side channel attacks},
	author = {Regazzoni, Francesco and Eisenbarth, Thomas and Gro{\ss}sch{\"a}dl, Johann and Breveglieri, Luca and Ienne, Paolo and Koren, Israel and Paar, Christof}
}
@conference {49.MuPaNeSaFa07,
	title = {Power Modeling and Power Analysis for IEEE 802.15.4: a Concurrent State Machine Approach},
	booktitle = {Proceedings of CCNC 2007},
	year = {2007},
	month = {January 11-13},
	address = {Las Vegas, USA},
	abstract = {802.15.4 is a recent low-rate/low-power standard for wireless personal area and sensor networks. Its simple infrastructure, intermediate range and good power performance make it a candidate for applications that require a reasonably low throughput but a very high device lifetime and power efficiency. An experimental power analysis of an 802.15.4 implementation is carried out, providing a detailed power model of the protocol based on concurrent state machines; resulting power model is then used to generate a customized simulator. The model has been validated through a set of experiments and provides good accuracy; results are discussed, considering in particular use of the model as a basis for subsequent optimizations on 802.15.4 networks.},
	keywords = {low power design, modeling, wireless sensor networks},
	doi = {http://dx.doi.org/10.1109/CCNC.2007.135},
	author = {Mura, Marcello and Paolieri, Marco and Negri, Luca and Fabbri, Fabio and Sami, Mariagiovanna}
}
@conference {58.FeChPi07,
	title = {A Query Unit for the IPSec Databases},
	booktitle = {SECRYPT 2007},
	year = {2007},
	month = {07/2007},
	address = {Barcelona, Spain},
	abstract = {IPSec is a suite of protocols that adds security to communications at the IP level. Protocols within IPSec make extensive use of two databases, namely the Security Policy Database (SPD) and the Security Association Database (SAD). The ability to query the SPD quickly is fundamental as this operation needs to be done for each incoming or outgoing IP packet, even if no IPSec processing needs to be applied on it. This may easily result in millions of query per second in gigabit networks. Since the databases may be of several thousands of records on large secure gateways, a dedicated hardware solution is needed to support high throughput. In this paper we discuss an architecture for these query units, we propose different query methods for the two databases, and we compare them through simulation. Two different versions of the architecture are presented: the basic version is modified to support multithreading. As shown by the simulations, this technique is very effective in this case. The architecture that supports multithreading allows for 11 million queries per second in the best case.},
	keywords = {accelerator, database, IPSec, security, security association database (SAD), security policy database (SPD), system-on-chip (SoC), SystemC},
	author = {Ferrante, Alberto and Chandra, Satish and Piuri, Vincenzo}
}
@conference {65.GiTaVeBrKo07,
	title = {A Question Answering service for information retrieval in Cooper},
	booktitle = {COOPER Workshop in conjunction with EC-TEL07 Conference},
	year = {2007},
	month = {September 17},
	abstract = {In Cooper, part of the student support will be provided by a Question Answering application in the form of a webservice. Question Answering allows a user to use the content of project document as input to find related documents as well as related experts. Latent Semantic Analysis as an underlying technique is briefly discussed followed by a description of our Latent Semantic Analysis engine and the software architecture that was developed. Issues for further development are also mentioned. The final section contains a specific case study of an environment in which an implementation is planned.},
	keywords = {information retrieval, latent semantic analysis, question answering, singular value decomposition},
	author = {Giesbers, Bas and Taddeo, Antonio Vincenzo and Vegt, Wim and Bruggen, Jan and Koper, Rob}
}
@conference {73.OtReLa07,
	title = {Rapid Creation of Application Models from Bandwidth Aware Core Graphs},
	booktitle = {Proceedings of: IP Based SoC Design 2007},
	year = {2007},
	month = {December 5-6},
	address = {Grenoble, France},
	abstract = {We present a methodology that allows rapid creation of application models from bandwidth aware core graphs that are available in the literature for a wide range of applications and we discuss their applicability to the rapid exploration of multiple Networks on Chip (NoCs) layout organizations. In a bandwidth aware core graph, each node represents a core and the numbers on the edges represent the bandwidth requirements between cores. We describe core graphs in a UML object model diagram and we then have an automatic code generation tool which produces a SystemC description whose behaviour results in a packet generation on every output connection that respects the bandwidth requirements specified in the core graph. We can then rapidly derive a NoC mapping in which a specific floorplan of the cores can be evaluated and compared with alternate floorplan options for rapid design space exploration.},
	keywords = {network-on-chip (NoC), rapid prototyping},
	author = {Otero, Jo{\~a}o and Regazzoni, Francesco and Lajolo, Marcello}
}
@conference {70.PaBoSa07,
	title = {ReCPU: a Parallel and Pipelined Architecture for Regular Expression Matching},
	booktitle = {Proceedings of 15th Annual IFIP International Conference on Very Large Scale Integration {(IFIP-VLSI 07)},(best paper award)},
	year = {2007},
	month = {October 15-17},
	address = {Atlanta, Georgia, USA},
	abstract = {Text pattern matching is one of the main and most computation intensive parts of systems such as Network Intrusion Detection Systems and DNA Sequencing Matching. Soft- ware solutions to this are available but often they do not satisfy the requirements in terms of performance. This pa- per presents a new hardware approach for regular expression matching: ReCPU. The proposed solution is a parallel and pipelined architecture able to deal with the common regular expression semantics. This implementation based on several parallel units achieves a throughput of more than one char- acter per clock cycle (maximum performance of state of the art solutions) requiring just O(n) memory locations (where n is the length of the regular expression). Performance has been evaluated synthesizing the VHDL description. Area and time constraints have been analyzed. Experimental re- sults are obtained simulating the architecture.},
	doi = {http://dx.doi.org/10.1109/VLSISOC.2007.4402466},
	author = {Paolieri, Marco and Bonesana, Ivano and Santambrogio, Marco Domenico}
}
@conference {62.SaTa07,
	title = {Remote Cooperation on Project-centred Learning: a Working Implemented Solution in Academia},
	booktitle = {COOPER Workshop in conjunction with EC-TEL07 Conference},
	year = {2007},
	month = {September 17},
	abstract = {The paper aims at illustrating the original technical solution provided within an academic institute in order to manage teaching activities, encompassing the coordination of project-centred learning processes that run in parallel with the formal theoretical courses. Unlike the planning of the academic teaching that can be scheduled year by year, the development of a project cannot be defined over a long period, but it requires frequent report reviews and updating by the different actors involved in the project. From this consideration, and due to the peculiar context of the ALaRI institute, it was clear the necessity to manage asynchronous and synchronous communications occurring during the ongoing project, facilitating the team members{\textquoteright} remote interactions and cooperation. The provided solution within the EU COOPER project is the answer to more and more common scenarios of use, reflecting not only university requirements, but also industrial needs based on the cooperative teamwork among persons geographically dispersed and with heterogeneous competences.},
	keywords = {case study, project-centred learning, remote cooperation},
	author = {Salvioni, Carola and Taddeo, Antonio Vincenzo}
}
@conference {69.BoIoNeTaTo07,
	title = {Role Based Access Control for the interaction with Search Engines},
	booktitle = {COOPER Workshop in conjunction with EC-TEL07 Conference},
	year = {2007},
	month = {September 17},
	abstract = {Search engine-based features are a basic interaction mean for users to find information inside a Web-based Learning Management Systems (LMS); nonetheless, traditional solutions lack in mechanisms for access rights management for data contained in search engines{\textquoteright} indexes. This paper explores the integration of a Role Based Access Control (RBAC) mechanism for the interaction with a search engine in a Web-based LMS. We first outline a reference conceptual model for the design of Web-based LMSs exploiting RBAC by means of WebML, a visual modeling language for the high-level specification of data-intensive Web applications. Then, we propose a model-driven approach for the definition of a RBAC-driven interaction between users and search engines, extending WebML with new modeling primitives and outlining significative modeling patterns for the specification of the visibility and action access control levels.},
	keywords = {access control modeling, index modeling, search engine design, web engineering},
	author = {Bozzon, Alessandro and Iofciu, Tereza and Nejdl, Wolfgang and Taddeo, Antonio Vincenzo and Tonnies, Sascha}
}
@conference {64.Barcellona2,
	title = {SC2: State Charts to System C: Automatic Executable Models Generation},
	booktitle = {proceedings FDL07},
	year = {2007},
	month = {September},
	address = {Barcelona, Spain},
	abstract = {The recent development of embedded systems calls for the necessity of a complete framework for design and simulation of applications that span through all levels of system design. Desirable characteristics of such a framework are rapidity of use, simplicity and reusability. For this purpose we already introduced a generator that converts specifications written with a subset of StateCharts to behavioral SystemC [9] [11]. In this paper we present the new version of our tool: most of the limitations of the previous versions have been overcome, the considered subset of the StateCharts formalism has been extended and the target has been changed from behavioral to Register Tranfer Level (RTL) SystemC. A major enhancement of this new version is the possibility of obtaining various module instances starting from a single specification, which is vital in some contexts (e.g. Wireless Sensors Networks simulation). The semantics chosen for our StateCharts diagrams is clearly described. The generation of executable models as well as the kernel template of the generated code are discussed in detail.},
	keywords = {code generation, StateCharts, SystemC, unified modeling language (UML)},
	author = {Mura, Marcello and Paolieri, Marco}
}
@article {51.TaFe07,
	title = {Scheduling Small packets in IPSec Multi-accelerator Based Systems},
	journal = {Journal of Communication(JCM) Academy publisher},
	volume = {2},
	number = {2},
	year = {2007},
	month = {March},
	pages = {53-60},
	address = {Stresa, Italy},
	abstract = {IPSec is a suite of protocols that adds security to communications at the IP level. Protocols within the IPSec suite make extensive use of cryptographic algorithms. Since these algorithms are computationally very intensive, some hardware acceleration is needed to support high throughput. IPSec accelerator performance may heavily depend on the dimension of the packets to be processed. In fact, when packets are small, the time needed to transfer data and to set up the accelerators may exceed the one to process (e.g. to encrypt) the packets by software. In this paper we present a packet scheduling algorithm that tackles this problem. Packets belonging to the same Security Association are grouped before the transfer to the accelerators. Thus, the transfer and the initialization time have a lower influence on the total processing time of the packets. This algorithm also provides the capability of scheduling grouped packets over multiple cryptographic accelerators. High-level simulations of the scheduling algorithm have been performed and the results for a one-accelerator and for a two-accelerator system are also shown in this paper.},
	keywords = {accelerator, HW/SW co-design, IPSec, scheduling algorithm, security},
	author = {Taddeo, Antonio Vincenzo and Ferrante, Alberto}
}
@conference {60.FiSiSa07,
	title = {Security Aspects in Networks-on-Chips: Overview and Proposals for Secure Implementations},
	booktitle = {DSD07, in proceedings of 10th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD 07)},
	year = {2007},
	month = {August 29-31},
	address = {L{\"u}beck, Germany},
	abstract = {Security has gained increasing relevance in the development of embedded devices. Towards the aim of a secure system at each level of the design, in this paper we address security aspects related to Networks-on-Chips (NoCs) architectures. After presenting the attacks most likely to address NoCs, we survey existing academic and industrial secure architectures relevant to our case, focusing in particular on their communication infrastructure. We outline and propose possible solutions to contrast some of the attacks described and suggest the use of the NoC as a mean to monitor and detect unexpected system behaviors.},
	keywords = {embedded systems, multiprocessor system-on-chip (MPSoC), network-on-chip (NoC), security},
	doi = {http://dx.doi.org/10.1109/DSD.2007.4341520},
	author = {Fiorin, Leandro and Silvano, Cristina and Sami, Mariagiovanna}
}
@conference {56.FeTaSaMa07,
	title = {Self-adaptive Security at Application Level: a Proposal},
	booktitle = {ReCoSoC 2007, Jun. 2007, in proceedings of ReCoSoC 2007},
	year = {2007},
	month = {June},
	abstract = {Self-adaptive systems have the ability to adapt themselves to mutating external or internal conditions without requesting any intervention of the user; the security of such systems is influenced by those adaptations. Therefore, also the security mechanisms that are put in place by the operating system, should adapt to maintain the desired security level. This paper proposes a self-adaptive framework for the system security. This adaptation scheme allows the system to choose the best set of security policies at every given time; this set is determined by considering the system internal and external conditions as well as the application requirements. The proposed framework deals with self-adaptation at system level in order to provide both a domain independent and a flexible solution.},
	keywords = {autonomous systems, security, security policies, self-adaptive security, self-adaptive systems, system level design},
	author = {Ferrante, Alberto and Taddeo, Antonio Vincenzo and Sami, Mariagiovanna and Mantovani, Fabrizio and Fridkins, Jurijs}
}
@conference {59.ReBaEi07,
	title = {Simulation-based Methodology for Evaluating DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies},
	booktitle = {International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS IC 07)},
	year = {2007},
	month = {July 16-19},
	address = {Samos, Greece},
	abstract = {This paper explores the resistance of MOS Current Mode Logic (MCML) against Differential Power Analysis (DPA) attacks. Circuits implemented in MCML, in fact, have unique characteristics both in terms of power consumption and the dependency of the power profile from the input signal pattern. Therefore, MCML is suitable to protect cryptographic hardware from DPA and similar side-channel attacks. In order to demonstrate the effectiveness of different logic styles against power analysis attacks, the non-linear bijective function of the Kasumi algorithm (known as substitution box S7) was implemented with CMOS and MCML technology, and a set of attacks was performed using power traces derived from SPICE-level simulations. Although all keys were discovered for CMOS, only very few attacks to MCML were successful.},
	keywords = {current mode logic (CML), differential power analysis (DPA), power simulation, side channel attacks},
	author = {Regazzoni, Francesco and Badel, St{\'e}phane and Eisenbarth, Thomas and Gro{\ss}sch{\"a}dl, Johann and Poschmann, Axel and Toprak, Zeynep and Macchetti, Marco and Pozzi, Laura and Paar, Christof and Leblebici, Yusuf and Ienne, Paolo}
}
@conference {50.MuPaNeSa07,
	title = {StateCharts to SystemC: a High Level Hardware Simulation Approach},
	booktitle = {Proceedings of GLSVLSI 2007},
	year = {2007},
	month = {March 11-13},
	address = {Stresa, Italy},
	abstract = {In this paper we present a tool that converts specifications written with a subset of StateCharts into SystemC behavioral models. The main advantages of such an approachare rapidity of use, simplicity and reusability. Various systems can be modeled at different levels of abstraction and accuracy through StateCharts and different peculiar aspects (e.g. energy, performances) can be taken into consideration. Moreover different parts of the design can be identified at different detail levels. The kernel of the simulator is fully discussed together with its mapping to the semantics of our StateCharts diagrams. As a case study we present here a model of the IBM PowerPC 750 Cache system and the respective SystemC simulator automatically generated by our tool.},
	keywords = {code generation, StateCharts, SystemC, unified modeling language (UML)},
	doi = {http://dx.doi.org/10.1145/1228784.1228904},
	author = {Mura, Marcello and Paolieri, Marco and Negri, Luca and Sami, Mariagiovanna}
}
@conference {46.ReBoDjMa07,
	title = {Tairona, an Open Source Platform for Worldwide Meeting and Tutoring},
	booktitle = {World Conference on Educational Multimedia, Hypermedia and Telecommunications 7 (ED-MEDIA 07)},
	year = {2007},
	address = {Vancouver, Canada},
	abstract = {Tairona is a web-based platform for real time meeting and tutoring. It aims to provide a solution for face to face synchronous communication between the tutor and the students in remote faculties and similar environments where a life meeting in not possible. In particular the application is tailored on needs of a scenario that is very unique: in the considered institution in fact, teachers and students meet themselves only for the week necessary to complete the course. In this paper we present the requirements that led us to design and implement Taiorna.},
	keywords = {java, learning, remote application, voice over IP (VoIP)},
	author = {Regazzoni, Francesco and Bonesana, Ivano and Djakov, Maksim and Mattiuz, Amanda}
}
@conference {66.PaMaSi07,
	title = {A Topology Design Customization Approach for (STNoC)},
	booktitle = {Nano-Nets 07, in proceedings of 2nd International Conference on Nano-Networks (Nano-Nets 2007).},
	year = {2007},
	month = {September 24-26},
	address = {Catania, Italy},
	abstract = {To support high bandwidth SoCs, a communication design flow is necessary for the design space exploration respecting tight design requirements. In order to exploit the benefits introduced by the NoC approach for the on-chip communication, the paper presents a design flow for the core mapping and customization of the network topology applied to STNoC, the Network on-Chip developed by STMicroelectronics. Starting from ring topology, the proposed application-specific flow tries to find a set of customized topologies, optimized in terms of performance and area/energy overhead, by adding links. The generated STNoC custom topologies provide a reduced cost with respect to the spidergon topology.},
	keywords = {application specific design, mapping, network-on-chip (NoC), STNoC, topology customization},
	doi = {http://dx.doi.org/10.1109/ASAP.2007.4429959},
	author = {Palermo, Gianluca and Mariani, Giovanni and Silvano, Cristina and Locatelli, Riccardo and Coppola, Marcello}
}
@conference {71.pisa,
	title = {Ultra-low power optimizations for the IEEE 802.15.4 networking protocol},
	booktitle = {proceedings of MASS},
	year = {2007},
	month = {October},
	abstract = {A main challenge to be tackled in the area of Wireless Sensors Networks (WSN)s is related to the limited amount of energy available and the requirements in terms of lifetime. IEEE 802.15.4 is a recent low-rate/lowpower standard for wireless personal area and sensor networks. Its simple infrastructure, intermediate range and reasonable power performance make it a candidate for a wide range of applications that require a low throughput but a reasonable device lifetime and consequently a certain power efficiency. Anyway there are some main inefficiencies of the protocol that limit its power performance and cause unnecessary power waste in some situations. In this paper these limitations of the standard in terms of power performance are investigated. Possible optimizations that can be achieved with minimal or null changes on available 802.15.4 compliant hardware platforms are suggested.},
	keywords = {low power design, modeling, protocol, wireless sensor networks},
	doi = {http://dx.doi.org/10.1109/MOBHOC.2007.4428630},
	author = {Mura, Marcello}
}
@conference {42.MaChen2006,
	title = {ASIC Hardware Implementation of the IDEA NXT Encryption Algorithm},
	booktitle = {IEEE International Symposium on Circuits and Systems},
	year = {2006},
	month = {May 21-24},
	address = {Kos, Greece},
	abstract = {Symmetric-key block ciphers are often used to provide data confidentiality with low complexity, especially in the case of dedicated hardware implementations. IDEA NXT is a novel block cipher family, which has many interesting features and is targeted to multimedia streaming encryption. Different values can be assigned to the hardware architecture parameters in order to scale the security and the performance of the cipher. In this paper, we implement the IDEA NXT algorithm in custom silicon, using a commercial technology library; different optimizations are applied in order to satisfy different constraints in terms of latency and area occupation, maintaining a high level of security. After giving an overview of the IDEA NXT design, a discussion of the implementation choices and trade offs is given, highlighting the similarities and the main differences with regards to other block ciphers. To the authors{\textquoteright} knowledge this is the first paper describing such work.},
	doi = {http://dx.doi.org/10.1109/ISCAS.2006.1693715},
	author = {Macchetti, Marco and Chen, Wenyu}
}
@conference {44.SivaPrev2006,
	title = {Bridging the Gap between SysML and Design Space Exploration},
	booktitle = {FDL{\textquoteright}06 Proceedings},
	year = {2006},
	month = {September 19-22},
	pages = {389-394},
	address = {Darmstadt, Germany},
	abstract = {In the last few years the embedded systems design discipline required new design methodologies and new specification languages to support system engineers in developing heterogeneous systems where hardware and software are combined. One of the emerging modeling languages for system designers is the UML-based language called Systems Modeling Language (SysML). One of the most important tasks to be addressed early in the system design phase is the Design Space Exploration (DSE). DSE helps designers in discovering the optimal solutions among all possible combinations after mapping functional to architectural specifications. This paper describes an approach on how to use SysML for a DSE analysis within a system design phase.},
	keywords = {design space exploration, HW/SW co-design, modeling languages, systems modeling language (SysML)},
	author = {Sivakumar, Ganesan and Prevostini, Mauro}
}
@conference {45.BoTa2006,
	title = {COOPER: Towards A Collaborative Open Environment of Project-centred Learning},
	booktitle = {proceedings to EC-TEL{\textquoteright}06 conference},
	year = {2006},
	month = {October 1-4},
	address = {Crete, Greece},
	abstract = {Nowadays, engineering studies are characterized by high mobility of students, lecturers and workforce and by the dynamics of multi-national companies where classes or students{\textquoteright} teams composed of persons with different competencies and backgrounds, working together in projects to solve complex problems. Such an environment will become increasingly relevant in multinational universities and companies, and it has brought a number of challenges to existing e-learning technologies. COOPER is an ongoing project that focuses on developing and testing such a collaborative and project-centred leaning environment. This paper proposes a COOPER framework and shows its approaches to address the various research challenges.},
	keywords = {project-centred learning, remote cooperation},
	author = {Bongio, Aldo and Bruggen, Jan and Ceri, Stefano and Cristea, Valentin and Dolog, Peter and Hoffmann, Andreas and Matera, Maristella and Mura, Marzia and Taddeo, Antonio Vincenzo and Zhou, Xuan and Zoni, Larissa}
}
@conference {40.1127983,
	title = {Hardware/software partitioning of operating systems: a behavioral synthesis approach},
	booktitle = {GLSVLSI {\textquoteright}06: Proceedings of the 16th ACM Great Lakes symposium on VLSI},
	year = {2006},
	pages = {324{\textendash}329},
	publisher = {ACM Press, New York, USA},
	organization = {ACM Press, New York, USA},
	address = {Philadelphia, PA, USA},
	abstract = {In this paper we propose a hardware real time operating system(HW-RTOS) solution that makes use of a dedicated hardware in order to replace the standard support provided by the POSIX layer of a general purpose RTOS for implementing task synchronization and scheduling. By redefining only the I/O APIs of the tasks, the HW-RTOS then takes care of the communication requirements of the original application and also implements the task scheduling algorithm. The new software application can then be compiled without any need for POSIX support. The main advantages are smaller and faster executables. We present results that show how a small hardware area, less than 10K gates, can result in a 15X performance improvement when the original software scheduler is replaced by a dedicated HW-RTOS.},
	keywords = {HW/SW co-design, real time operating systems, system-on-chip (SoC)},
	isbn = {1-59593-347-6},
	doi = {http://doi.acm.org/10.1145/1127908.1127983},
	author = {Chandra, Satish and Regazzoni, Francesco and Lajolo, Marcello}
}
@conference {43.PeUpSa,
	title = {Particle Swarm Optimization with Discrete Recombination: An Online Optimizer for Evolvable Hardware},
	booktitle = {1st NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2006)},
	year = {2006},
	month = {June 16-18},
	address = {Istanbul, Turkey},
	abstract = {Self-reconfigurable adaptive systems have the possibility of adapting their own hardware configuration. This feature provides enhanced performance and flexibility, reflected in computational cost reductions. Self-reconfigurable adaptation requires powerful optimization algorithms in order to search in a space of possible hardware configurations. If such algorithms are to be implemented on chip, they must also be as simple as possible, so the best performance can be achieved with the less cost in terms of logic resources, convergence speed, and power consumption. This paper presents an hybrid bio-inspired optimization technique that introduces the concept of discrete recombination in a particle swarm optimizer, obtaining a simple and powerful algorithm, well suited for embedded applications. The proposed algorithm is validated using standard benchmark functions and used for training a neural network-based adaptive equalizer for communications systems.},
	author = {Pe{\~n}a, Jorge and Upegui, Andres and Sanchez, Eduardo}
}
@conference {38.1110115,
	title = {Power/Performance Tradeoffs in Bluetooth Sensor Networks},
	booktitle = {HICSS {\textquoteright}06: Proceedings of the 39th Annual Hawaii International Conference on System Sciences},
	year = {2006},
	pages = {236.2},
	publisher = {IEEE Computer Society},
	organization = {IEEE Computer Society},
	address = {Washington, DC, USA},
	abstract = {Low power consumption is a critical issue in wireless sensor networks. Over the past few years, a considerable number of ad-hoc architectures and communication protocols have been proposed for sensor network nodes. If on one hand custom solutions carry the greatest power optimization potential, widespread communication standards guarantee interoperability and ease of connection with existing devices. In this paper we present a variable-granularity power model of Bluetooth, and apply it to variable-complexity optimization scenarios, to devise optimal power management policies. These policies, if backed by hardware implementations that are more power-aggressive than those available, could make the protocol fit for a wider range of sensor networks than it is today.},
	isbn = {0-7695-2507-5},
	doi = {http://dx.doi.org/10.1109/HICSS.2006.383},
	author = {Negri, Luca and Zanetti, Davide}
}
@conference {41.TaFePi2006,
	title = {Scheduling Small Packets in IPSec-based Systems},
	booktitle = {CCNC},
	year = {2006},
	month = {January 8},
	address = {Las Vegas, NV, USA},
	abstract = {IPSec is a suite of protocols that adds security to communications at the IP level. Protocols within the IPSec suite make extensive use of cryptographic algorithms. Since these algorithms are computationally very intensive, some hardware acceleration is needed to support high throughput. IPSec accelerator performance may heavily depend on the dimension of the packets to be processed. When packets are small, the time needed to transfer data and to set up the accelerator may exceed the one to process the packets (e.g. to encrypt) by software. In this paper, we propose a solution for this problem. High-level simulations and the related results are provided to show the properties of the algorithm.},
	keywords = {accelerator, HW/SW co-design, IPSec, scheduling algorithm, security},
	doi = {http://dx.doi.org/10.1109/CCNC.2006.1593123},
	author = {Taddeo, Antonio Vincenzo and Ferrante, Alberto and Piuri, Vincenzo}
}
@conference {39.1169233,
	title = {Speeding Up AES By Extending a 32 bit Processor Instruction Set},
	booktitle = {ASAP {\textquoteright}06: Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP{\textquoteright}06)},
	year = {2006},
	pages = {275-282},
	publisher = {IEEE Computer Society},
	organization = {IEEE Computer Society},
	address = {Washington, DC, USA},
	abstract = {Nowadays the need of speed in cipher and decipher operations is more important than in the past. This is due to the diffusion of real time applications, which fact involves the use of cryptography. Many co-processors for cryptography were studied and presented in the past, but only few works were addressed to the enhancement of the instruction set architecture (ISA) of the embedded processor. This paper presents an extension of the ISA of a 32 bit processor, that aims at speeding up the software implementations of the AES algorithm. After the identification of the most frequently executed and the most time consuming sections of the algorithm, a set of dedicated instructions is designed in order to improve the performances of the cipher operations. We validate our instruction set extension by measuring the speed up for different optimized implementations of AES using an ARM processor simulator, but the enhancements we propose are general enough to be applied to almost all 32 bit processors.},
	keywords = {cryptography, HW/SW co-design, instruction set extension},
	isbn = {0-7695-2682-9},
	doi = {http://dx.doi.org/10.1109/ASAP.2006.62},
	author = {Bertoni, Guido Marco and Breveglieri, Luca and Farina, Roberto and Regazzoni, Francesco}
}
@conference {28.1049903,
	title = {Application-Driven Optimization of VLIW Architectures: A Hardware-Software Approach},
	booktitle = {RTAS {\textquoteright}05: Proceedings of the 11th IEEE Real Time on Embedded Technology and Applications Symposium},
	year = {2005},
	month = {03/2005},
	pages = {128{\textendash}137},
	publisher = {IEEE Computer Society},
	organization = {IEEE Computer Society},
	address = {Washington, DC, USA},
	abstract = {A large number of embedded multimedia applications are characterized by high instruction-level parallelism (ILP) expecially in the most critical internal loop bodies. Very Large Instruction Word (VLIW) architectures Application Specific Instruction Set Processors (ASIP) are best suited to exploit such parallelism. Fast design space exploration and optimization of VLIW architecture to a specific application target is increasingly becoming the crucial factor to achieve higher efficiency designs in a relatively small amount of time. In this paper we propose an example of VLIW architecture application driven optimization using the VEX (VLIW Example) system. A typical image processing application, the Imaging Pipeline, has been chosen as an example.},
	keywords = {design space exploration, embedded systems, HW/SW co-design, HW/SW partitioning, system level design, very long instruction words (VLIW)},
	isbn = {0-7695-2302-1},
	doi = {http://dx.doi.org/10.1109/RTAS.2005.9},
	author = {Ferrante, Alberto and Piscopo, Giuseppe and Scaldaferri, Stefano}
}
@conference {36.RegNacLaj2005,
	title = {Automatic Synthesis of the Hardware/Software Interface in Multiprocessor Architectures},
	booktitle = {FDL{\textquoteright}05 - Forum on Specification and Design Languages},
	year = {2005},
	month = {September 27-30},
	address = {Lausanne, Switzerland},
	abstract = {Although Moore{\textquoteright}s Law, in principle, enables a huge number of components to be integrated into a single chip, design methods that will allow system architects to put the components together to achieve cost, power and time-to-market targets are severely lacking. System-level design and optimization techniques can significantly reduce the design gap by providing solutions that achieve correct-by-construction rather than the correct-by-iteration approach. This paper presents a programmatic interface generation tool for automating the generation of the hardware/software interfaces in the context of multiprocessor Systems-On-Chips. The solutions that we present are of crucial importance in a platform based design environment for building a flexible system with reusable IPs and CPU cores.},
	keywords = {HW/SW co-design, system-on-chip (SoC)},
	author = {Regazzoni, Francesco and Nacul, Andre Costi and Lajolo, Marcello}
}
@conference {34.BaLaPrevos2005,
	title = {Design and Synthesis of Reusable Platforms with Programmable Interconnects},
	booktitle = {UML-SoC 2005},
	year = {2005},
	month = {June 12},
	pages = {43-48},
	address = {Anaheim, California},
	abstract = {Platform based design requires to restrict the number of possible design choices in order to make it possible to come up with programmable solutions able to cope with the current complexity of System-On-Chip (SoC) designs. Nowadays there is a general consensus toward the fact that an effective Electronic System Level (ESL) design methodology must provide a specific support for platform specification, hardware/software partitioning and programmatic interfaces synthesis in order to allow designers to exploit the potentials of state-of-the-art technologies. In this work we present a methodology that leverages on UML for building new architectural platforms to be used to be used in the system design process. We show how our methodology can allow to reuse pre-designed platforms by adding new architectural components and by customizing their interconnections},
	keywords = {HW/SW co-design, system-on-chip (SoC), unified modeling language (UML)},
	author = {Basu, Ananda Shankar and Lajolo, Marcello and Prevostini, Mauro}
}
@conference {31.1070384,
	title = {Flexible Power Modeling for Wireless Systems: Power Modeling and Optimization of two Bluetooth Implementations},
	booktitle = {WOWMOM {\textquoteright}05: Proceedings of the Sixth IEEE International Symposium on a World of Wireless Mobile and Multimedia Networks (WoWMoM{\textquoteright}05)},
	year = {2005},
	pages = {408{\textendash}416},
	publisher = {IEEE Computer Society},
	organization = {IEEE Computer Society},
	address = {Washington, DC, USA},
	abstract = {A large number of embedded multimedia applications are characterized by high instruction-level parallelism (ILP) expecially in the most critical internal loop bodies. Very Large Instruction Word (VLIW) architectures Application Specific Instruction Set Processors (ASIP) are best suited to exploit such parallelism. Fast design space exploration and optimization of VLIW architecture to a specific application target is increasingly becoming the crucial factor to achieve higher efficiency designs in a relatively small amount of time. In this paper we propose an example of VLIW architecture application driven optimization using the VEX (VLIW Example) system. A typical image processing application, the Imaging Pipeline, has been chosen as an example.},
	isbn = {0-7695-2342-0-01},
	doi = {http://dx.doi.org/10.1109/WOWMOM.2005.46},
	author = {Negri, Luca and Sami, Mariagiovanna and Tran, Que Dung and Zanetti, Davide}
}
@conference {32.Salvioni2005,
	title = {From a young academic institute a broad minded approach: the working and learning environment of the ALaRI Intranet tool (case study)},
	booktitle = {MICROLEARNING 2005: Learning \& Working in New Media Environments},
	year = {2005},
	month = {June 23-24},
	address = {Innsbruck, Austria},
	abstract = {The aim of this paper is to present an innovative approach to the working organization and learning environment, experimented at ALaRI (Advanced Learning and Research Institute), the academic institute at the Universit{\`a} della Svizzera italiana, in Switzerland, that, since 1999, promotes research and education in embedded systems design . Through the introduction and the use of an ad-hoc intranet tool, new social and technological dynamics have been developing at the institute, integrating learning in presence with remote cooperation in a complex and distributed reality. Presenting the practical experiences occurred within the ALaRI environment, through an analysis of the context needs and of the tool usability, the reader will discover the conditions and the reasons that have led to designing and implementing this intranet platform, but also troubles and limitations of the intranet will be explored from a usability and communication point of view. From these experiences a plentiful research material arises to investigate new workflows and new ideas for virtual workplace.},
	keywords = {case study, remote cooperation, virtual workplace, workplace studies},
	author = {Salvioni, Carola}
}
@conference {37.RegLaj2005,
	title = {Hardware/Software Partitioning and Interface Synthesis in Networks On Chip},
	booktitle = {IP Based SoC Design 2005},
	year = {2005},
	month = {December 7-8},
	address = {Grenoble, France},
	abstract = {With deep sub-micron technology, chip designers are expected to create System-On-Chip (SOC) solutions by connecting different Intellectual Property (IP) blocks using efficient and reliable interconnection schemes. On chip networks are quite compelling because, by applying networking techniques to on-chip communication, they allow to implement a fully distributed communication pattern with little or no global coordination. This avoids the problems due to the difficulty of implementing future chips with one single clock source and negligible skew. On the other hand, in order to benefit from the NOC communication paradigm, designers should perform a careful functional mapping for taking advantage of spatial locality, by placing the blocks that communicate more frequently closer together. This reduces the use of long global paths and the corresponding energy dissipation. In this work we show how a tile based NOC architecture can be exploited in order to support a flexible hardware/software partitioning of a system-level specification and we present a methodology for the automatic synthesis of the hardware/software interfaces.},
	keywords = {HW/SW co-design, network-on-chip (NoC), system-on-chip (SoC)},
	author = {Regazzoni, Francesco and Lajolo, Marcello}
}
@inbook {30.BaLaPre2005,
	title = {A Methodology for Bridging the Gap between UML and Codesign},
	booktitle = {UML for SOC Design},
	year = {2005},
	pages = {119-146},
	publisher = {Springer},
	organization = {Springer},
	address = {Dordrecht, The Netherlands},
	abstract = {The Unified Modeling Language (UML) is getting more popular among system designers due to the need to raise the level of abstraction in system specifications. We present here a methodology that integrates UML specifications with a hardware/software codesign platform. This work aims to give a contribution toward SoC Design Automation starting from system level specification down to hardware/software partitioning and integration.},
	keywords = {HW/SW co-design, methodology, system specifications, unified modeling language (UML)},
	author = {Basu, Ananda Shankar and Lajolo, Marcello and Prevostini, Mauro},
	editor = {Martin, Grant and Muller, Wolfgang}
}
@conference {33.MacDad2005,
	title = {Quasi-Pipelined Hash Circuits},
	booktitle = {IEEE ARITH 17},
	year = {2005},
	month = {June},
	pages = {222-229},
	address = {Cape Cod},
	abstract = {Hash functions are an important cryptographic primitive. They are used to obtain a fixed-size fingerprint, or hash value, of an arbitrary long message. We focus particularly on the class of dedicated hash functions, whose general construction is presented; the peculiar arrangement of sequential and combinational units makes the application of pipelining techniques to these constructions not trivial. We formalize an optimization technique called quasi-pipelining, whose goal is to optimize the critical path and thus to increase the clock frequency in dedicated hardware implementations. The SHA-2 algorithm has been previously examined by Dadda et al, with specific versions of quasi-pipelining; a full generalization of the technique is presented, along with application to the SHA-1 algorithm. Quasi-pipelining could be as well applied to future hashing algorithms, provided they are designed along the same lines as those of the SHA family.},
	doi = {http://dx.doi.org/10.1109/ARITH.2005.36},
	author = {Macchetti, Marco and Dadda, Luigi}
}
@conference {35.MacRiv2005,
	title = {Small-scale Variants of the Secure Hash Standard},
	booktitle = {ECRYPT workshop on RFID and lightweight cryptography},
	year = {2005},
	month = {July 14-15},
	address = {Graz, Austria},
	abstract = {In this paper we present effective small scale formulations of the Secure Hash Standard; we focus on the SHA-2 family of algo- rithms, introducing new compact instances baptized SHA-16, SHA-32, and SHA-64. These may be useful for computing hashes and Message Authentication Codes (MACs) on small platforms where only 8-bit pro- cessors are available, such as in the case of Radio Frequency Identifi- cation (RFID) devices and embedded systems. To prove the soundness of our scaling approach, we analyze the cryptographic properties of the proposed constructions in terms of adherence to the Strict Avalanche Criterion (SAC) and of robustness to birthday attacks, by also compar- ing the results with the expected values from random functions. As an additional contribution, we complete the theoretical results for the bal- ance property of random functions, thereby also calculating the expected robustness of the original SHA-2 family versus birthday attacks. Keywords: hash functions, balance, SAC, small scale, RFID.},
	keywords = {balance, hash functions, RFID, SAC, small scale},
	author = {Macchetti, Marco and Rivard, Philippe}
}
@conference {29.SaMaRe2005,
	title = {Speeding Security on the Intel StrongARM},
	booktitle = {Embedded Intel Solutions},
	year = {2005},
	pages = {31-33},
	abstract = {With the increasing use of portable and wireless devices in the business and daily life, protecting sensitive information via encryption is becoming more and more crucial. ALaRI (Advanced Learning and Research Institute) has been conducting research aimed at improving the execution of security algorithms in embedded systems. Thanks to a donation from Intel, ALaRI has been able to develop several recommendations for implementing security efficiently on the Intel StrongARM architecture.},
	keywords = {embedded processors, instruction set extension, security},
	author = {Sami, Mariagiovanna and Macchetti, Marco and Regazzoni, Francesco}
}
@conference {17.NegBon2004,
	title = {The ALaRI Intranet: a Remote Collaboration Platform for a Worldwide Learning and Research Network},
	booktitle = {World Conference on Educational Multimedia, Hypermedia and Telecommunications 04 (ED-MEDIA 04)},
	year = {2004},
	pages = {5042-5047},
	publisher = {AACE Press},
	organization = {AACE Press},
	address = {Lugano, Switzerland},
	abstract = {The ALaRI Intranet is a web-based remote learning, tutoring and collaboration platform that has been developed within the ANTITESYS project. ANTITESYS is a EU project involving some of the major academic and industrial institutions in Europe; its aim is to foster academic-industrial collaboration in the field of embedded systems whilst forming selected students by means of a one-year master program, held at the ALaRI institute sited in Lugano, Switzerland. What makes this scenario very unique lies in the roles played by the industrial and academic partners of ANTITESYS. The two sides contribute to the training of the master students in different ways, but both share the problem of integrating remote and face-to-face meetings with the students and with the other stakeholders. In this paper, we present the requirements gathering process and the design phase of the ALaRI Intranet, plus some details about its actual implementation and some initial usage figures.},
	keywords = {case study, remote cooperation},
	author = {Negri, Luca and Bondi, Umberto}
}
@conference {20.989053,
	title = {An ASIC design for a high speed implementation of the hash function SHA-256 (384, 512)},
	booktitle = {GLSVLSI {\textquoteright}04: Proceedings of the 14th ACM Great Lakes symposium on VLSI},
	year = {2004},
	pages = {421{\textendash}425},
	publisher = {ACM Press, New York, USA},
	organization = {ACM Press, New York, USA},
	address = {Boston, MA, USA},
	abstract = {An implementation of the hash functions SHA-256, 384 and 512 is presented, obtaining a high clock rate through a reduction of the critical path length, both in the Expander and in the Compressor of the hash scheme. The critical path is shown to be the smallest achievable. Synthesis results show that the new scheme can reach a clock rate well exceeding 1 GHz using a 0.13?m technology.},
	isbn = {1-58113-853-9},
	doi = {http://doi.acm.org/10.1145/988952.989053},
	author = {Dadda, Luigi and Macchetti, Marco and Owen, Jeff}
}
@conference {18.969266,
	title = {The Design of a High Speed ASIC Unit for the Hash Function SHA-256 (384,512)},
	booktitle = {DATE {\textquoteright}04: Proceedings of the conference on Design, automation and test in Europe},
	year = {2004},
	pages = {30070},
	publisher = {IEEE Computer Society},
	organization = {IEEE Computer Society},
	address = {Washington, DC, USA},
	abstract = {After recalling the basic algorithms published by NIST for implementing the hash functions SHA-256 (384, 512), a basic circuit characterized by a cascade of full adder arrays is given. Implementation options are discussed and two methods for improving speed are exposed: the delay balancing and the pipelining. An application of the former is first given, obtaining a circuit that reduces the length of the critical path by a full adder array. A pipelined version is then given, obtaining a reduction of two full adder arrays in the critical path. The two methods are afterwards combined and the results obtained through hardware synthesis are exposed, where a comparison between the new circuits is also given.},
	isbn = {0-7695-2085-5-3},
	doi = {http://dx.doi.org/10.1109/DATE.2004.1269207},
	author = {Dadda, Luigi and Macchetti, Marco and Owen, Jeff}
}
@conference {21.968073,
	title = {Efficient AES implementations for ARM based platforms},
	booktitle = {SAC {\textquoteright}04: Proceedings of the 2004 ACM symposium on Applied computing},
	year = {2004},
	pages = {841{\textendash}845},
	publisher = {ACM Press, New York, USA},
	organization = {ACM Press, New York, USA},
	address = {Nicosia, Cyprus},
	abstract = {The Advanced Encryption Standard (AES) contest, started by the U.S. National Institute of Standards and Technology (NIST), saw the Rijndael [13] algorithm as its winner [11]. Although the AES is fully defined in terms of functionality, it requires best exploitation of architectural parameters in order to reach the optimum performance on specific architectures. Our work concentrates on ARM cores [1] widely used in the embedded industry. Most promising implementation choices for the common ARM Instruction Set Architecture (ISA) are identified, and a new implementation for the linear mixing layer is proposed. The performance improvement over current implementations is demonstrated by a case study on the Intel StrongARM SA-1110 Microprocessor [2]. Further improvements based on exploitation of memory hierarchies are also described, and the corresponding performance figures are presented.},
	keywords = {advanced encryption standard (AES), ARM microprocessor, cache memories, code optimisation},
	isbn = {1-58113-812-1},
	doi = {http://doi.acm.org/10.1145/967900.968073},
	author = {Atasu, Kubilay and Breveglieri, Luca and Macchetti, Marco}
}
@conference {16.1013323,
	title = {FSM{\textendash}based power modeling of wireless protocols: the case of bluetooth},
	booktitle = {ISLPED {\textquoteright}04: Proceedings of the 2004 international symposium on Low power electronics and design},
	year = {2004},
	pages = {369-374},
	publisher = {ACM Press, New York, USA},
	organization = {ACM Press, New York, USA},
	address = {Newport Beach, California, USA},
	abstract = {The proliferation of pervasive computing applications relying on battery-powered devices and wireless connectivity is posing great emphasis on the issue of power optimization. While node-level models and approaches have been widely discussed, a problem requiring even greater attention is that of power associated with the communication protocols. We propose a high-level modeling methodology based on Finite State Machines useful to predict the energy consumption of given communication tasks with very low computational cost, which can be applied to any protocol. We use this methodology to create a power model of Bluetooth that we characterize and validate experimentally on a real implementation.},
	keywords = {bluetooth, power modeling, wireless protocols},
	isbn = {1-58113-929-2},
	doi = {http://dx.doi.org/10.1109/LPE.2004.1349368},
	author = {Negri, Luca and Sami, Mariagiovanna and Macii, David and Terranegra, Alessandra}
}
@conference {27.RegLaj2004,
	title = {Interface Synthesis in Multiprocessing Systems-on-Chips},
	booktitle = {IP Based SoC Design 2004},
	year = {2004},
	month = {December},
	address = {Grenoble},
	abstract = {Although Moore{\textquoteright}s Law, in principle, enables a huge number of components to be integrated into a single chip, design methods that will allow system architects to put the components together to achieve cost, power and time-to-market targets are severely lacking. System-level design and optimization techniques can significantly reduce the design gap by providing solutions that achieve correct-by-construction approach rather than the correct-by-iteration approach. This paper presents a programmatic interface generation tool for automating the generation of the hardware/software interfaces in the context of multi-processor Systems-On-Chips. The solutions that we present are of crucial importance in a platform based design environment for building a flexible system with reusable IPs and CPU cores.},
	keywords = {HW/SW co-design, system-on-chip (SoC)},
	author = {Regazzoni, Francesco and Lajolo, Marcello}
}
@Patent {22.pat20040228482PATENT,
	title = {Method of implementing one-to-one binary function and relative hardware device, especially for a Rijndael S-box},
	number = {US 10/816,791 -- 	EP 20030425211},
	year = {2004},
	month = {10/2004},
	type = {Grant},
	chapter = {US 7502464 B2 -- EP 1465365 A1 },
	abstract = {A method for implementing one-to-one binary functions defined on the Galois field GF(2^8) is very useful for forming fast and low power hardware devices regardless of the binary function. The method includes decoding an input byte for generating at least one bit string that contains only one active bit, and logically combining the bits of the bit string according to the binary function for generating a 256-bit string representing a corresponding output byte. The 256-bit string is then encoded in a byte for obtaining the output byte.},
	issn = {US 7502464 B2},
	author = {Macchetti, Marco and Fragneto, Pasqualina and Bertoni, Guido Marco}
}
@conference {26.BoFeDuPi2004,
	title = {A Methodology for Testing IPSec-based Systems},
	booktitle = {SoftCOM 2004},
	year = {2004},
	month = {October},
	pages = {22-26},
	address = {Split},
	abstract = {{IPSec is a suite of protocols adding security to communications at the IP level. This suite of protocols is becoming more and more important as it is included as mandatory security mechanism in IPv6. This paper focuses on a methodology for testing IPSec implementations. A UML model of the IPSec suite of protocols was developed. Test cases were obtained applying a coverage method on the same model.}},
	keywords = {encapsulating security payload (ESP), IPSec, security, testing, unified modeling language (UML)},
	author = {Boiko, Uljana and Ferrante, Alberto and Lo Duca, Antonietta and Piuri, Vincenzo}
}
@conference {23.BaLaPre2004,
	title = {UML in an Electronic System Level Design Methodology},
	booktitle = {UML-SOC{\textquoteright}04},
	year = {2004},
	month = {June 6},
	pages = {47-52},
	address = {San Diego, California},
	abstract = {The interest in System-On-Chip (SoC) design using the Unifed Modeling Language (UML) has been growing significantly during the last couple of years. In this paper we would like to present a methodology that aims to address embedded systems design issues at multiple levels of abstraction and to support a function/architecture codesign process. Our approach integrates UML with high-level synthesis and hardware/software co-verification techniques in order to provide an automated flow for SoC design starting from system-level specifications down to hardware/software partitioning and integration. UML has been selected because it is platform independent and helps team members to share very efficiently relevant information during the various design phases, while high-level synthesis helps to evaluate constraints that the embedded system must satisfy: e.g. performance, power and cost starting from behavioral specifications. The paper aims to give a contribution towards SoC Design automation from System-level specification to hardware/software partitioning.},
	keywords = {HW/SW co-design, methodology, system-on-chip (SoC), unified modeling language (UML)},
	author = {Basu, Ananda Shankar and Lajolo, Marcello and Prevostini, Mauro}
}
@conference {24.LaBaPre2004,
	title = {UML Specifications Towards a Codesign Environment},
	booktitle = {FDL{\textquoteright}04},
	year = {2004},
	month = {September 14-17},
	pages = {313-324},
	address = {Lille, France},
	abstract = {The Unified Modeling Language (UML) is receiving more and more attention from system designers that need to model both hardware and software related aspects of a system. On the ground of the growing consensus toward the need to raise the level of abstraction in system specifications, we would like to present a methodology that aims to address embedded systems design issues at multiple levels of abstraction and to support a function/architecture codesign process. Our approach integrates UML with high-level synthesis and hardware/software co-verification techniques in order to provide an automated flow for SoC design starting from system-level specifications down to hardware/software partitioning and integration. UML has been selected because it is platform independent and helps team member to share very efficiently relevant information during the various design phases, while high-level synthesis helps to evaluate constraints that the embedded system must satisfy: e.g. performance, power and cost starting from behavioral specifications.},
	keywords = {embedded systems, HW/SW co-design, system-on-chip (SoC), unified modeling language (UML)},
	author = {Lajolo, Marcello and Basu, Ananda Shankar and Prevostini, Mauro}
}
@conference {25.PiPreSte2004,
	title = {UML System-Level Analysis and Design of Secure Communication Schemes for Embedded Systems},
	booktitle = {FDL{\textquoteright}04},
	year = {2004},
	month = {September 14-17},
	pages = {301-312},
	address = {Lille, France},
	abstract = {In this work we develop a secure communication protocol in the context of a Remote Meter Reading (RMR) System. We first analyze existing standards in secure communication (e.g. IPsec, SSL/TSL) and existing implementations aimed at embedded systems with low-power constraints in general (e.g. lwIP, lwBT, ZigBee). Then, starting from a Platform Independent Modeling (PIM), we develop a protocol concept to address authentication, integrity and confidentiality, also covering battery lifetime checking and theft monitoring. Finally the protocol itself is described by means of UML. Limited resource and low-power constraints are taken into account when examining secure-transmission features. RMR is thus an example of an application requiring a light-weight protocol combined with security features. One of the future objectives is to switch from the PIM description to PSM implementation.},
	keywords = {embedded systems, low-power protocols, security, unified modeling language (UML)},
	author = {Piscopo, Giuseppe and Prevostini, Mauro and Stefanini, Ivan}
}
@inbook {19.1016432,
	title = {UML-based specifications of an embedded system oriented to HW/SW partitioning: a case study},
	booktitle = {Languages for system specification: Selected contributions on UML, systemC, system Verilog, mixed-signal systems, and property specification from FDL{\textquoteright}03},
	year = {2004},
	pages = {71-84},
	publisher = {Kluwer Academic Publishers},
	organization = {Kluwer Academic Publishers},
	address = {Norwell, MA, USA},
	abstract = {The Unified Modelling Language (UML) is a language for specifying, visualizing, constructing, and documenting the artefacts of software systems, as well as for modeling business and other non-software systems. The UML represents a collection of best engineering practices that succeeded in modelling large and complex systems; it is interesting to envision its extension for specification and modelling of hardware-software systems as well, starting with the first design phases, i.e. prior to hardware-software partitioning. This paper analyses the development of a solution able to define the hardware/software partitioning of an embedded system starting from its UML system specifications. The case study chosen is a Wireless Meter Reader (WMR) dedicated to the measurement of energy consumption. The designers evaluated the hardware/software partitioning solution in terms of cost, performance, size and consumption.},
	keywords = {embedded systems, HW/SW partitioning, system specifications, unified modeling language (UML)},
	isbn = {1-4020-7990-7},
	author = {Prevostini, Mauro and Balzarini, Francesco and Kostadinov, Atanas Nikolov and Mankan, Srinivas and Martinola, Aris and Minosi, Antonio}
}
@conference {11.BiMaBeBreZaFra2003,
	title = {About the Performances of the Advanced Encryption Standard in Embedded Systems with Cache Memory},
	booktitle = {ISCAS 2003},
	year = {2003},
	month = {May 25-28},
	pages = {145-148},
	address = {Bangkok},
	abstract = {Modern networked embedded systems represent a growing market segment in which security is becoming an essential requirement. The Advanced Encryption Standard (AES) specification is becoming the default choice for such type of systems; however, a proper software implementation of AES is of fundamental importance in order to achieve significant performance. Current implementations presented in literature differ in terms of the amount of look-up tables used for pre-computing the functions of the encryption/decryption phase. This raises some questions regarding which AES implementation is optimal for a specific system configuration that, up to now, have been only empirically solved. In this work, we present an analytical model to study and evaluate the performance of the possible AES implementations in the early phases of system development. We then show that the proposed high-level timing model captures, with significant accuracy, the actual performance of current AES applications and thus it can be used for early evaluation of optimal AES implementations and to support the design space exploration phase. Validating experiments have been carried out on the Lx architecture, a scalable and customizable VLIW architecture developed by STMicroelectronics and HP Labs. Some final considerations are eventually reported about the relevant characteristics of the analyzed implementations and the role of the cache memory.},
	doi = {http://dx.doi.org/10.1109/ISCAS.2003.1206212},
	author = {Bircan, Aril and Macchetti, Marco and Bertoni, Guido Marco and Breveglieri, Luca and Zaccaria, Vittorio and Fragneto, Pasqualina}
}
@article {15.AlGaSte2003,
	title = {An Application Level Synthesis Methodology for Multidimensional Embedded Processing Systems},
	journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
	volume = {22},
	number = {11},
	year = {2003},
	month = {November},
	pages = {1457-1470},
	abstract = {The implementation of multidimensional systems in embedded devices is a major design challenge due to the high algorithmic complexity of the applications. The authors suggest a novel application-level synthesis methodology for those parts of the embedded application which are characterized by being Lebesgue measurable (the computation involved in signal and image processing systems is Lebesgue measurable). The synthesis methodology, based on perturbation analysis, supports the design of analog, digital, or mixed implementations at the very high level of the system design cycle. The outputs of the methodology are quantitative indications regarding the maximum performance loss tolerable by the subsystems composing the application. Such information, augmented with a stochastic description of the tolerated perturbations, can be related to lower synthesis levels and guide the designer toward the final implementation of the embedded device. The perturbation analysis is based on randomized algorithms for an effective evaluation of the performance loss of the computational flow once affected by behavioral perturbations and a Tabu-search-inspired optimizing algorithm for distributing the tolerable performance loss at the system output along the computational subsystems composing the possibly multidimensional processing.},
	keywords = {application-level synthesis, multidimensional systems, randomized algorithms, robustness analysis, tabu search, yield maximization},
	doi = {http://dx.doi.org/10.1109/TCAD.2003.818304},
	author = {Alippi, Cesare and Galbusera, Andrea and Stellini, Marco}
}
@conference {8.752733,
	title = {Efficient Software Implementation of AES on 32-Bit Platforms},
	booktitle = {CHES {\textquoteright}02: Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems},
	year = {2003},
	pages = {159{\textendash}171},
	publisher = {Springer-Verlag},
	organization = {Springer-Verlag},
	address = {London, UK},
	abstract = {Rijndael is the winner algorithm of the AES contest; therefore it should become the most used symmetric-key cryptographic algorithm. One important application of this new standard is cryptography on smart cards. In this paper we present an optimisation of the Rijndael algorithm to speed up execution on 32-bits processors with memory constraints, such as those used in smart cards. First a theoretical analysis of the Rijndael algorithm and of the proposed optimisation is discussed, and then simulation results of the optimised algorithm on different processors are presented and compared with other reference implementations, as known from the technical literature.},
	isbn = {3-540-00409-2},
	author = {Bertoni, Guido Marco and Breveglieri, Luca and Fragneto, Pasqualina and Macchetti, Marco and Marchesin, Stefano}
}
@article {13.MaBer2003,
	title = {Hardware Implementation of the Rijndael Sbox: a Case Study},
	journal = {ST Journal of System Research},
	year = {2003},
	month = {July},
	pages = {84-91},
	abstract = {The Rijndael algorithm was officially selected as the Advanced Encryption Standard in 2001 and will replace the DES in all applications, including Smart Card based products. For this kind of platform, a compact, area efficient hardware implementation of the algorithm is highly desirable. This paper describes such an implementation, which we have based on GF(28) finite field decomposition. We present our results from mappings on the STMicroelectronics ASIC technology library and discuss area, timing and power consumption figures.},
	author = {Macchetti, Marco and Bertoni, Guido Marco}
}
@conference {12.MiMaMaPreKoBa2003,
	title = {Intelligent, low-power and low-cost measurement system for energy consumption},
	booktitle = {VECIMS 2003},
	year = {2003},
	month = {July 27-29},
	pages = {125-130},
	address = {Lugano},
	abstract = {In the area of utility measurement systems, there is increasing awareness to the importance of using intelligent and secure meter readers. The aim is not simply that of reducing operational costs; aspects such as availability of real-time determination of consumption (mainly in the case of energy meters, but potentially also for water consumption etc.) are relevant not only for actions such as real-time billing but also in view of an increasing environmental awareness leading to {\textquoteright}preferential{\textquoteright} billing in particular times of the day or of the week and requiring availability of fine-grained statistics. All these actions in turn involve the requirement of data integrity; when utilities other than power providers are considered, the device should be battery-powered (and very long battery life must be granted), so that low-power design becomes a further requirement while being permanently either in active or in standby mode; moreover, not being connected to the power network means that wireless connections for transmitting and receiving information must be taken into account. Finally, these devices should be made available to the general public and thus be low-cost ones. This paper describes how all the above constraints have been analyzed in the design of a wireless meter reading system.},
	keywords = {measurement systems, meter reading systems, power consumption},
	author = {Minosi, Antonio and Martinola, Aris and Mankan, Srinivas and Prevostini, Mauro and Kostadinov, Atanas Nikolov and Balzarini, Francesco}
}
@Patent {10.pat20030068036PATENT,
	title = {Method and circuit for data encryption/decryption},
	number = {US 09/974,705},
	year = {2003},
	month = {April},
	type = {Grant},
	chapter = {US7801301 B2},
	abstract = {Data are converted between an unencrypted and an encrypted format according to the Rijndael algorithm, including a plurality of rounds. Each round is comprised of fixed set of transformations applied to a two-dimensional array, designated state, of rows and columns of bit words. At least a part of said transformations are applied on a transposed version of the state, wherein rows and columns are transposed for the columns and rows, respectively.},
	issn = {US7801301B2},
	author = {Macchetti, Marco and Marchesin, Stefano and Bondi, Umberto and Breveglieri, Luca and Bertoni, Guido Marco and Fragneto, Pasqualina}
}
@conference {9.SaSaSciSiZaZa2003,
	title = {A Methodology for efficient architectural exploration of energy-delay trade-offs for embedded systems},
	booktitle = {SAC 2003},
	year = {2003},
	month = {March},
	pages = {672-678},
	address = {Melbourne},
	abstract = {The main goal of this paper is to identify the best architecture of an embedded system by considering at the same time energy and delay, avoiding the comprehensive analysis of the architectural design space. We adopt the Energy-Delay Product (EDP) as the evaluation metric to compare the alternative architectures of the target system. The paper analyzes an extended adaptive random search algorithm (ADGREED) to efficiently explore the architectural design space. The ADGREED algorithm is a pseudo-random optimization algorithm that combines the best potentialities of the adaptive random search (ADRAS) and the Greedy deterministic algorithm. The analysis has been carried out through the architectural optimization of the memory subsystem of a real-word embedded system executing the set of Mediabench benchmarks for multimedia applications. The reported experimental results have shown a reduction up to one order of magnitude of the number of design alternatives analyzed during the exploration phase, while maintaining very high accuracy.},
	keywords = {design space exploration, embedded systems},
	doi = {http://dx.doi.org/10.1145/952532.952664},
	author = {Salvemini, Lorenzo and Sami, Mariagiovanna and Sciuto, Donatella and Silvano, Cristina and Zaccaria, Vittorio and Zafalon, Roberto}
}
@conference {14.MiMaMaBaKoPre2003,
	title = {UML-based Specifications of an Embedded System Oriented to HW/SW Partitioning: a Case Study},
	booktitle = {FDL{\textquoteright}03},
	year = {2003},
	month = {September 23-26},
	pages = {226-237},
	address = {Frankfurt},
	abstract = {The Unified Modelling Language (UML) is a language for specifying, visualizing, constructing, and documenting the artefacts of software systems, as well as for modelling business and other non-software systems. The UML represents a collection of best engineering practices that succeeded in modelling large and complex systems; it is interesting to envision its extension for specification and modelling of hardware-software systems as well, starting with the first design phases, i.e. prior to hardware-software partitioning. This paper analyses the development of a solution able to define the hardware/software partitioning of an embedded system starting from its UML system specifications. The case study chosen is a Wireless Meter Reader (WMR) dedicated to the measurement of energy consumption. The designers evaluated the hard-ware/software partitioning solution in terms of cost, performance, size and consumption.},
	keywords = {embedded systems, HW/SW partitioning, unified modeling language (UML)},
	author = {Minosi, Antonio and Mankan, Srinivas and Martinola, Aris and Balzarini, Francesco and Kostadinov, Atanas Nikolov and Prevostini, Mauro}
}
@conference {5.AlGaSte2002,
	title = {An Application Level Synthesis Methodology for Embedded Systems},
	booktitle = {ISCAS 2002},
	year = {2002},
	month = {May 26-29},
	pages = {473-476},
	address = {Scottsdale},
	abstract = {Time-to-market, cost and power consumption requirements are pushing research in embedded systems towards the development of sophisticated CAD environments. The paper suggests a novel synthesis methodology for embedded devices based on an application level perturbation analysis. The methodology is based on randomised algorithms for evaluating the effective performance loss of the computational flow induced by perturbations and a Tabu-search optimising algorithm for distributing the tolerable performance loss along the computational subsystems composing the computation.},
	doi = {http://dx.doi.org/10.1109/ISCAS.2002.1010743},
	author = {Alippi, Cesare and Galbusera, Andrea and Stellini, Marco}
}
@conference {6.BoSaSciSiZaZa2002,
	title = {Energy Estimation and Optimization of Embedded VLIW Processors based on Instruction Clustering},
	booktitle = {39th Design Automation Conference},
	year = {2002},
	month = {June 10-14},
	pages = {886-891},
	address = {New Orleans},
	abstract = {Aim of this paper is to propose a methodology for the definition of an instruction-level energy estimation framework for VLIW (Very Long Instruction Word) processors. The power modeling methodology is the key issue to define an effective energy-aware software optimisation strategy for state-of-the-art ILP (Instruction Level Parallelism) processors. The methodology is based on an energy model for VLIW processors that exploits instruction clustering to achieve an efficient and fine grained energy estimation. The approach aims at reducing the complexity of the characterization problem for VLIW processors from exponential, with respect to the number of parallel operations in the same very long instruction, to quadratic, with respect to the number of instruction clusters. Furthermore, the paper proposes a spatial scheduling algorithm based on a low-power reordering of the parallel operations within the same long instruction. Experimental results have been carried out on the Lx processor, a 4-issue VLIW core jointly designed by HPLabs and STMicroelectronics. The results have shown an average error of 1:9\% between the cluster-based estimation model and the reference design, with a standard deviation of 5:8\%. For the Lx architecture, the spatial instruction scheduling algorithm provides an average energy saving of 12\%.},
	keywords = {power estimation, VLIW architectures},
	doi = {http://dx.doi.org/10.1109/DAC.2002.1012747},
	author = {Bona, Andrea and Sami, Mariagiovanna and Sciuto, Donatella and Silvano, Cristina and Zaccaria, Vittorio and Zafalon, Roberto}
}
@conference {4.BonaSaSciSiZaZa2002,
	title = {An Instruction-Level Methodology for Power Estimation and Optimization of Embedded VLIW cores},
	booktitle = {DATE 2002},
	year = {2002},
	month = {March 4-8},
	pages = {1128},
	address = {Paris},
	abstract = {The overall goal of this work is to define an instruction-level power macro-modeling and characterization methodology for VLIW embedded processor cores. The approach presented in this paper is a major extension of the work previously proposed in [1-3], targeting an instruction-level energy model to evaluate the energy consumption associated with a program execution on a pipelined VLIW core. Our first goal is the reduction of the complexity of the processor{\textquoteright}s energy model, without reducing the accuracy of the results. The second goal is to show how the energy model can be further simplified by introducing a methodology to automatically cluster the whole Instruction Set with respect to their average energy cost, in order to con verge to an highly effective design of experiments for the actual characterization task. The paper describes also the application of the proposed model to a real industrial VLIW core (the Lx Architecture developed by HP Labs and STMicroelectronics), to validate the effectiveness and accuracy of the proposed methodology.},
	doi = {http://dx.doi.org/10.1109/DATE.2002.998484},
	author = {Bona, Andrea and Sami, Mariagiovanna and Sciuto, Donatella and Silvano, Cristina and Zaccaria, Vittorio and Zafalon, Roberto}
}
@conference {7.MiMaMaPre,
	title = {System-level design of embedded applications by UML: the Wireless Meter Reading case},
	booktitle = {MSy2002 Workshop},
	year = {2002},
	month = {October 3-4},
	pages = {181-187},
	address = {Winterthur},
	abstract = {The Unified Modeling Language (UML) is a language for specifying, visualizing, constructing, and documenting the artifacts of software systems, as well as for business modeling and other non-software systems. The UML represents a collection of best engineering practices that have proven successful in the modeling of large and complex systems; it is interesting to envision its extension for specification and modeling of hardwaresoftware systems as well, since the first design phases, i.e. before hardware-software partitioning has been effected. This paper describes how UML has been used in the design of a wireless meter reading system consisting of hardware and software components.},
	keywords = {embedded applications, unified modeling language (UML), wireless meter reading},
	author = {Minosi, Antonio and Martinola, Aris and Mankan, Srinivas and Prevostini, Mauro}
}
@conference {1.371690,
	title = {Development cost and size estimation starting from high-level specifications},
	booktitle = {CODES {\textquoteright}01: Proceedings of the ninth international symposium on Hardware/software codesign},
	year = {2001},
	pages = {86-91},
	publisher = {ACM Press, New York, USA},
	organization = {ACM Press, New York, USA},
	address = {Copenhagen, Denmark},
	abstract = {This paper addresses the problem of estimating cost and development effort of a system, starting from its complete or partial high-level description. In addition, some modifications to evaluate the cost-effectiveness of reusing VHDL-based designs, are presented. The proposed approach has been formalized using an approach similar to the COCOMO analysis strategy, enhanced by a project size prediction methodology based on a VHDL function point metric. The proposed design size estimation methodology has been validated through a significant benchmark. The LEON-I microprocessor, whose VHDL description is of public domain.},
	keywords = {concurrent engineering, design reuse, process management, project size estimation, VHDL},
	isbn = {1-58113-364-2},
	doi = {http://dx.doi.org/10.1109/HSC.2001.924656},
	author = {Fornaciari, William and Salice, Fabio and Bondi, Umberto and Magini, Edi}
}
@conference {3.CaPoMaMaBeBreFra2001,
	title = {Efficient C implementation of the ECC and AES cryptographic systems},
	booktitle = {Technology Leadership Day - organized by the MicroSwiss Network},
	year = {2001},
	month = {October 10},
	address = {Fribourg},
	author = {Cassoli, Federico and Polloni, Flavio and Marchesin, Stefano and Macchetti, Marco and Bertoni, Guido Marco and Breveglieri, Luca and Fragneto, Pasqualina}
}
@conference {2.BoSaMa2001,
	title = {The {\textquoteright}Smart Card System{\textquoteright} project: From plastic money to mobile transaction support},
	booktitle = {Technology Leadership Day - organized by the MicroSwiss Network},
	year = {2001},
	month = {October 10},
	address = {Fribourg},
	author = {Bondi, Umberto and Saraceno, Giuseppe and Mazzoni, Luca}
}
