Export 144 results:
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"AETHER: Self-Adaptive Networked Entities: Autonomous Computing Elements for Future Pervasive Applications and Technologies",
Reconfigurable Computing: From FPGAs to Hardware/Software Codesign, New York, USA, Springer, pp. 149–184, 2011.
"A Design Flow and Evaluation Framework for DPA-resistant Instruction Set Extensions",
Cryptographic Hardware and Embedded Systems (CHES), vol. 5747, Lausanne, Switzerland, Springer Berlin Heidelberg, pp. 205-219, September, 2009.
"Fault Attacks, Injection Techniques and Tools for Simulation",
Hardware Security and Trust: Design and Deployment of Integrated Circuits in a Threatened Environment, First edition; 2016: Springer, pp. 149-167, 2017.
Hardware Security and Trust: Design and Deployment of Integrated Circuits in a Threatened Environment,
, First edition; 2016: Springer, 2017.
"Interaction between Fault Attack Countermeasures and the Resistance against Power Analysis Attacks",
Fault Analysis in Cryptography: Springer Berlin Heidelberg, pp. 257-272, 2012.
"Malware Threats and Solutions for Trustworthy Mobile Systems Design",
Hardware Security and Trust: Design and Deployment of Integrated Circuits in a Threatened Environment, First edition; 2016: Springer, pp. 149-167, 2017.
"Model-Driven Evaluation of User-Perceived Service Availability",
Dependable Computing, vol. 7869: Springer Berlin Heidelberg, pp. 39-53, May, 2013.
"Modeling Responsiveness of Decentralized Service Discovery in Wireless Mesh Networks",
MMB & DFT, vol. 8376: Springer International Publishing Switzerland, pp. 88-102, 2014.
"Optimization Algorithms for Embedded System Design Space Exploration",
Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach, New York, USA, Springer, 2011.
"Response Surface Modeling for Embedded System Design Space Exploration",
Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach, New York, USA, Springer, 2011.
"Security IPs and IP Security with FPGAs",
Secure Smart Embedded Devices Platform and Applications, 2014.
"Self-Organizing Real-Time Services in Mobile Ad Hoc Networks",
Self-Organization in Embedded Real-Time Systems: Springer New York, pp. 55-74, 2013.
"200 MS/s ADC implemented in a FPGA employing TDCs",
FPGA International Symposium on Field-Programmable Gate Arrays ACM/SIGDA 2015, Monterey, CA, USA, ACM, pp. 228-235, 02/2015.
"A 640 Mbit/s 32-bit Pipelined Implementation of the AES Algorithm",
SECRYPT, Porto, Portugal, July 26, 2008.
"Accelerating differential power analysis on heterogeneous systems",
The 9th Workshop on Embedded Systems Security (WESS) 2014, New Delhi, India, ACM, 10/2014.
"Adaptable AES implementation with power-gating support",
International Conference on Computing Frontiers CF'16, Como, Italy, ACM Ney York, NY, USA, pp. 331-334, 05/2016.
"Adaptable AES implementation with power-gating support",
International Conference on Computing Frontiers CF'16, Como, Italy, ACM Ney York, NY, USA, pp. 331-334, 05/2016.
"Area and Power Efficient Synthesis of DPA-Resistant Cryptographic SBoxes",
International Conference on VLSI Design & Embedded Systems, Bangalore, India, January 6-10, 2007.
"Atomic-AES: A Compact Implementation of the AES Encryption/Decryption Core",
Proceedings of 17th International Conference on Cryptology in India (INDOCRYPT) 2016, 2016.
"Automatic Synthesis of the Hardware/Software Interface in Multiprocessor Architectures",
FDL'05 - Forum on Specification and Design Languages, Lausanne, Switzerland, September 27-30, 2005.