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Education and Innovation in Embedded Systems Design

USI Università della Svizzera italiana, USI Faculty of Informatics, Advanced Learning and Research Institute USI Università della Svizzera italiana USI Faculty of Informatics USI Advanced Learning and Research Institute
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Book Chapter
Gamrat, C., J-M. Philippe, C. Jesshope, A. Shafarenko, L. Bisdounis, U. Bondi, A. Ferrante, J. Cabestany, M. Huebner, J. Parsinnen, et al., "AETHER: Self-Adaptive Networked Entities: Autonomous Computing Elements for Future Pervasive Applications and Technologies", Reconfigurable Computing: From FPGAs to Hardware/Software Codesign, New York, USA, Springer, pp. 149–184, 2011.
Gamrat, C., J-M. Philippe, C. Jesshope, A. Shafarenko, L. Bisdounis, U. Bondi, A. Ferrante, J. Cabestany, M. Huebner, J. Parsinnen, et al., "AETHER: Self-Adaptive Networked Entities: Autonomous Computing Elements for Future Pervasive Applications and Technologies", Reconfigurable Computing: From FPGAs to Hardware/Software Codesign, New York, USA, Springer, pp. 149–184, 2011.
Kavka, C., A. Turco, G. Palermo, C. Silvano, V. Zaccaria, G. Mariani, S. Bocchio, and F. Dongrui, "Design Space Exploration of Parallel Architectures", Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach, New York, USA, Springer, 2011.
Sklavos, N., R. Chaves, G. Di Natale, and F. Regazzoni, Hardware Security and Trust: Design and Deployment of Integrated Circuits in a Threatened Environment, , First edition; 2016: Springer, 2017.
Dittrich, A., and R. Rezende, "Model-Driven Evaluation of User-Perceived Service Availability", Dependable Computing, vol. 7869: Springer Berlin Heidelberg, pp. 39-53, May, 2013.
Dittrich, A., B. Lichtblau, R. Rezende, and M. Malek, "Modeling Responsiveness of Decentralized Service Discovery in Wireless Mesh Networks", MMB & DFT, vol. 8376: Springer International Publishing Switzerland, pp. 88-102, 2014.
Silvano, C., W. Fornaciari, G. Palermo, V. Zaccaria, F. Castro, M. Martinez, S. Bocchio, R. Zafalon, P. Avasare, G. Vanmeerbeeck, et al., "The MULTICUBE Design Flow", Multi-objective Design Space Exploration of Multiprocessor SoC Architectures: Springer New York, pp. 3-17, 2011.
Silvano, C., W. Fornaciari, G. Palermo, V. Zaccaria, F. Castro, M. Martinez, S. Bocchio, R. Zafalon, P. Avasare, G. Vanmeerbeeck, et al., "MULTICUBE: Multi-Objective Design Space Exploration of Multi-Core Architectures", VLSI 2010 Annual Symposium, vol. 105, Netherlands, Springer, pp. 47-63, 2011.
Durvaux, F., S. Kerckhof, F. Regazzoni, and F-X. Standaert, "Security IPs and IP Security with FPGAs", Secure Smart Embedded Devices Platform and Applications, 2014.
Derin, O., and L. Fiorin, "Towards a Reliability-aware Design Flow for Kahn Process Networks on NoC-based Multiprocessors", 10th Workshop on Dependability and Fault Tolerance (ARCS/VERFE'14), Lübeck, Germany, Springer, 2014.
Conference Paper
Dadda, L., M. Macchetti, and J. Owen, "An ASIC design for a high speed implementation of the hash function SHA-256 (384, 512)", GLSVLSI '04: Proceedings of the 14th ACM Great Lakes symposium on VLSI, Boston, MA, USA, ACM Press, New York, USA, pp. 421–425, 2004.
Bailey, D. V., B. Baldwin, L. Batina, D. J. Bernstein, P. Birkner, J. W. Bos, G. van Damme, G. de Meulenaer, J. Fan, F. Gurkaynak, et al., "The Certicom Challenges ECC2-X", Workshop on Special Purpose Hardware for Attacking Cryptographic Systems (SHARCS), Lausanne, Switzerland, September, 2009.
Regazzoni, F., R. Graves, G. Di Natale, L. Batina, S. Bhasin, B. Ege, A. P. Fournaris, N. Mentens, S. Picek, V. Rozic, et al., "Challenges in designing trustworthy cryptographic co-processors", IEEE International Symposium on Circuits and Systems (ISCAS) 2015, Lisbon, Portugal, IEEE, pp. 2009-2012, 09/2015.
Bongio, A., J. van Bruggen, S. Ceri, V. Cristea, P. Dolog, A. Hoffmann, M. Matera, M. Mura, A V. Taddeo, X. Zhou, et al., "COOPER: Towards A Collaborative Open Environment of Project-centred Learning", proceedings to EC-TEL'06 conference, Crete, Greece, October 1-4, 2006.
Masin, M., F. Palumbo, H. Myrhaug, J. A. de Oliv Filho, M. Pastena, M. Pelcat, L. Raffo, F. Regazzoni, A. A. Sanchez, A. Toffetti, et al., "Cross-layer Design of Reconfigurable Cyber-Physical Systems", Proceedings of Design, Automation and Test in Europe (DATE) 2017, 2017.
Dadda, L., M. Macchetti, and J. Owen, "The Design of a High Speed ASIC Unit for the Hash Function SHA-256 (384,512)", DATE '04: Proceedings of the conference on Design, automation and test in Europe, Washington, DC, USA, IEEE Computer Society, pp. 30070, 2004.
Alippi, C., V. D'Alto, M. Falchetto, D. Pau, and M. Roveri, "Detecting changes at the sensor level in cyber-physical systems: Methodology and technological implementation", 2017 International Joint Conference on Neural Networks (IJCNN), May, 2017.
Baddour, R., A. Chiumento, and C. Desset, "Energy-Throughput Simulation Approach for Heterogeneous LTE scenarios", ISWCS'11: Proceedings of The Eighth International Symposium on Wireless Communication Systems, Aachen, Germany, pp. 1–5, November 6-9, 2011.
Dittrich, A., S. Wanja, and M. Malek, "ExCovery – A Framework for Distributed System Experiments and a Case Study of Service Discovery", 28th International Parallel & Distributed Processing Symposium, Workshops and Phd Forum (IPDPSW), Phoenix, AZ, USA, IEEE Computer Society, 05/2014.
Derin, O., "Learning Java by a Card Game: A Case Study", LG2007: Proceedings of Learning with Games Conference, Sophia Antipolis, France, pp. 221–228, September 24-27, 2007.

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