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"Customized Instructions for Protection Against Memory Integrity Attacks", IEEE Embedded Systems Letters, In Press.
"Optimization Algorithms for Embedded System Design Space Exploration", Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach, New York, USA, Springer, 2011.
"User-Perceived Instantaneous Service Availability Evaluation", 19th Pacific Rim International Symposium on Dependable Computing (PRDC), Vancouver, British Columbia, Canada, IEEE Computer Society, 12/2013.
"FPGA Implementations of the AES Masked Against Power Analysis Attacks", 2nd International Workshop on Constructive Side-Channel Analysis and Secure Design (COSADE), Darmstadt, Germany, February, 2011.
"A Design Flow and Evaluation Framework for DPA-resistant Instruction Set Extensions", Cryptographic Hardware and Embedded Systems (CHES), vol. 5747, Lausanne, Switzerland, Springer Berlin Heidelberg, pp. 205-219, September, 2009.
"Security: The Dark Side of Approximate Computing?", Proceedings of the International Conference on Computer-Aided Design, New York, NY, USA, ACM, 11/2018.
"Simulation-based Methodology for Evaluating DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies", International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS IC 07), Samos, Greece, July 16-19, 2007.
"Challenges in designing trustworthy cryptographic co-processors", IEEE International Symposium on Circuits and Systems (ISCAS) 2015, Lisbon, Portugal, IEEE, pp. 2009-2012, 09/2015.
"Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology", Springer Transactions on Computational Science, vol. 5430, pp. 230–243, February, 2009.
"Interface Synthesis in Multiprocessing Systems-on-Chips", IP Based SoC Design 2004, Grenoble, December, 2004.
"Physical Attacks and Beyond", Proceedings of the Selected Areas in Cryptography: 23nd International Conference (SAC) 2016, 2016.
"Power Attacks Resistance of Cryptographic S-boxes with added Error Detection Circuits", proceedings of: '22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'07), Rome, Italy, September 26-28, 2007.
"Instruction Set Extensions for secure applications", Design, Automation Test in Europe Conference DATE 2016, Dresden, Germany, IEEE, pp. 1529-1534, 03/2016.
"Hardware/Software Partitioning and Interface Synthesis in Networks On Chip", IP Based SoC Design 2005, Grenoble, France, December 7-8, 2005.
"Can knowledge regarding the presence of countermeasures against fault attacks simplify power attacks on cryptographic devices?", Proceedings of 23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS 08), October 1-3, 2008.
"Midori: (A) Block Cipher for Low Energy (Extended Version)", (IACR) Cryptology ePrint Archive, vol. 2015, 12/2015.
"Automatic Synthesis of the Hardware/Software Interface in Multiprocessor Architectures", FDL'05 - Forum on Specification and Design Languages, Lausanne, Switzerland, September 27-30, 2005.
"Single-Photon Avalanche Diodes (SPADs) for quantum random number generators and beyond", 19th Asia and South Pacific Design Automation Conference (ASP-DAC) 2014, Singapore, IEEE, 01/2014.
"Interaction between Fault Attack Countermeasures and the Resistance against Power Analysis Attacks", Fault Analysis in Cryptography: Springer Berlin Heidelberg, pp. 257-272, 2012.
"Quantum Era Challenges for Classical Computers", Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, New York, NY, USA, ACM, 2018.