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Education and Innovation in Embedded Systems Design

USI Università della Svizzera italiana, USI Faculty of Informatics, Advanced Learning and Research Institute USI Università della Svizzera italiana USI Faculty of Informatics USI Advanced Learning and Research Institute
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Author Title Type [ Year(Asc)]
2011
Fiorin, L., L. Micconi, and M. Sami, "Design of Fault Tolerant Network Interfaces for NoCs", Proceedings of 14th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD'11), Oulu, Finland, September, 2011.
Mariani, G., P. Avasare, C. Ykman-Couvreur, G. Vanmeerbeeck, G. Palermo, C. Silvano, and V. Zaccaria, "Design Space Exploration for Run-Time Management of a Reconfigurable System for Video Streaming", Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach, 1: Springer, pp. 189-204, 2011.
Mariani, G., P. Avasare, C. Ykman-Couvreur, G. Vanmeerbeeck, G. Palermo, C. Silvano, and V. Zaccaria, "Design Space Exploration of a Reconfigurable System for Supporting Video Streaming Run-time Management", Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach, New York, USA, Springer, 2011.
Kavka, C., A. Turco, G. Palermo, C. Silvano, V. Zaccaria, G. Mariani, S. Bocchio, and F. Dongrui, "Design Space Exploration of Parallel Architectures", Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach, New York, USA, Springer, 2011.
Avasare, P., C. Ykman-Couvreur, G. Vanmeerbeeck, G. Mariani, G. Palermo, C. Silvano, and V. Zaccaria, "Design Space Exploration Supporting Run-time Resource Management", Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach, New York, USA, Springer, 2011.
Baddour, R., A. Chiumento, and C. Desset, "Energy-Throughput Simulation Approach for Heterogeneous LTE scenarios", ISWCS'11: Proceedings of The Eighth International Symposium on Wireless Communication Systems, Aachen, Germany, pp. 1–5, November 6-9, 2011.
Barenghi, A., C. Hocquet, D. Bol, F-X. Standaert, F. Regazzoni, and I. Koren, "Exploring the Feasibility of Low Cost Fault Injection Attacks on Sub-Threshold Devices through an Example of a 65nm AES Implementation", 7th Workshop on RFID Security and Privacy (RFIDSec), Amherst, Massachussets, USA, June, 2011.
Bayrak, A. Galip, F. Regazzoni, P. Brisk, F-X. Standaert, and P. Ienne, "A First Step Towards Automatic Application of Power Analysis Countermeasures", 48th Design Automation Conference (DAC), San Diego, Califorina, June, 2011.
Regazzoni, F., W. Yi, and F-X. Standaert, "FPGA Implementations of the AES Masked Against Power Analysis Attacks", 2nd International Workshop on Constructive Side-Channel Analysis and Secure Design (COSADE), Darmstadt, Germany, February, 2011.
Taddeo, A V., L G G. Morales, and A. Ferrante, "A Framework for Security and Workload Gradual Adaptation", SECRYPT, Seville, Spain, ICETE, 07/2011.
Medwed, M., C. Petit, F. Regazzoni, M. Renauld, and F-X. Standaert, "Fresh Re-Keying II: Securing Multiple Parties against Side-Channel and Fault Attacks", 10th Smart Card Research and Advanced Application Conference (CARDIS), Leuven, Belgium, September, 2011.
Hocquet, C., D. Kamel, F. Regazzoni, J-D. Legat, D. Flandre, D. Bol, and F-X. Standaert, "Harvesting the potential of nano-CMOS for lightweight cryptography: An ultra-low-voltage 65 nm AES coprocessor for passive RFID tags", Springer Journal of Cryptographic Engineering, vol. 1, issue 1, 2011.
Ykman-Couvreur, C., P. Avasare, G. Mariani, V. Zaccaria, G. Palermo, and C. Silvano, "Linking run-time resource management of embedded multi-core platforms with automated design-time exploration", IET Computers and Digital Techniques, vol. 5, no. -, pp. 123–135, 2011.
Kerckhof, S., F. Durvaux, N. Veyrat-Charvillon, F. Regazzoni, G. Meurice de Dormale, and F-X. Standaert, "Low Cost FPGA Implementations of the SHA-3 Finalists", 10th Smart Card Research and Advanced Application Conference (CARDIS), Leuven, Belgium, September, 2011.
Derin, O., E. Diken, and L. Fiorin, "A Middleware Approach to Achieving Fault-tolerance of Kahn Process Networks on Networks-on-Chips", International Journal of Reconfigurable Computing, vol. 2011, no. Article ID 295385: Hindawi, pp. 14 pages, February, 2011.
Cannella, E., O. Derin, and T. Stefanov, "Middleware Approaches for Adaptivity of Kahn Process Networks on Networks-on-Chip", DASIP'11: Proceedings of the Conference on Design and Architectures for Signal and Image Processing, Tampere, Finland, pp. 1–8, November 2-4, 2011.
Silvano, C., W. Fornaciari, G. Palermo, V. Zaccaria, F. Castro, M. Martinez, S. Bocchio, R. Zafalon, P. Avasare, G. Vanmeerbeeck, et al., "The MULTICUBE Design Flow", Multi-objective Design Space Exploration of Multiprocessor SoC Architectures: Springer New York, pp. 3-17, 2011.
Silvano, C., W. Fornaciari, G. Palermo, V. Zaccaria, F. Castro, M. Martinez, S. Bocchio, R. Zafalon, P. Avasare, G. Vanmeerbeeck, et al., "MULTICUBE: Multi-Objective Design Space Exploration of Multi-Core Architectures", VLSI 2010 Annual Symposium, vol. 105, Netherlands, Springer, pp. 47-63, 2011.
Derin, O., D. Kabakci, and L. Fiorin, "Online Task Remapping Strategies for Fault-tolerant Network-on-Chip Multiprocessors", NOCS '11: Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip, Pittsburgh, Pennsylvania, USA, pp. 1–8, 05/2011.
Rigoni, E., C. Kavka, A. Turco, G. Palermo, C. Silvano, V. Zaccaria, and G. Mariani, "Optimization Algorithms for Embedded System Design Space Exploration", Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach, New York, USA, Springer, 2011.

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